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From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: mathieu.poirier@linaro.org, anshuman.khandual@arm.com,
	coresight@lists.linaro.org,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-kernel@vger.kernel.org, leo.yan@linaro.org,
	mike.leach@linaro.org
Subject: [PATCH v6 12/26] coresight: etm4x: Check for Software Lock
Date: Thu,  7 Jan 2021 12:38:45 +0000	[thread overview]
Message-ID: <20210107123859.674252-13-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20210107123859.674252-1-suzuki.poulose@arm.com>

The Software lock is not implemented for system instructions
based accesses. So, skip the lock register access in such
cases.

Cc: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 .../coresight/coresight-etm4x-core.c          | 40 ++++++++++++-------
 1 file changed, 26 insertions(+), 14 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index da0b64dd51d0..f947d6ddf9e3 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -133,6 +133,21 @@ static void etm4_os_lock(struct etmv4_drvdata *drvdata)
 	isb();
 }
 
+static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
+			 struct csdev_access *csa)
+{
+	/* Software Lock is only accessible via memory mapped interface */
+	if (csa->io_mem)
+		CS_LOCK(csa->base);
+}
+
+static void etm4_cs_unlock(struct etmv4_drvdata *drvdata,
+			 struct csdev_access *csa)
+{
+	if (csa->io_mem)
+		CS_UNLOCK(csa->base);
+}
+
 static bool etm4_arch_supported(u8 arch)
 {
 	/* Mask out the minor version number */
@@ -263,7 +278,8 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
 	struct device *etm_dev = &csdev->dev;
 	struct csdev_access *csa = &csdev->access;
 
-	CS_UNLOCK(drvdata->base);
+
+	etm4_cs_unlock(drvdata, csa);
 	etm4_enable_arch_specific(drvdata);
 
 	etm4_os_unlock(drvdata);
@@ -366,7 +382,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
 	isb();
 
 done:
-	CS_LOCK(drvdata->base);
+	etm4_cs_lock(drvdata, csa);
 
 	dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
 		drvdata->cpu, rc);
@@ -623,7 +639,7 @@ static void etm4_disable_hw(void *info)
 	struct csdev_access *csa = &csdev->access;
 	int i;
 
-	CS_UNLOCK(drvdata->base);
+	etm4_cs_unlock(drvdata, csa);
 	etm4_disable_arch_specific(drvdata);
 
 	if (!drvdata->skip_power_up) {
@@ -665,8 +681,7 @@ static void etm4_disable_hw(void *info)
 	}
 
 	coresight_disclaim_device_unlocked(csdev);
-
-	CS_LOCK(drvdata->base);
+	etm4_cs_lock(drvdata, csa);
 
 	dev_dbg(&drvdata->csdev->dev,
 		"cpu: %d disable smp call done\n", drvdata->cpu);
@@ -776,8 +791,7 @@ static void etm4_init_arch_data(void *info)
 
 	/* Make sure all registers are accessible */
 	etm4_os_unlock_csa(drvdata, csa);
-
-	CS_UNLOCK(drvdata->base);
+	etm4_cs_unlock(drvdata, csa);
 
 	/* find all capabilities of the tracing unit */
 	etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
@@ -942,7 +956,7 @@ static void etm4_init_arch_data(void *info)
 	drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
 	/* NUMCNTR, bits[30:28] number of counters available for tracing */
 	drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
-	CS_LOCK(drvdata->base);
+	etm4_cs_lock(drvdata, csa);
 }
 
 /* Set ELx trace filter access in the TRCVICTLR register */
@@ -1323,8 +1337,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
 	dsb(sy);
 	isb();
 
-	CS_UNLOCK(drvdata->base);
-
+	etm4_cs_unlock(drvdata, csa);
 	/* Lock the OS lock to disable trace and external debugger access */
 	etm4_os_lock(drvdata);
 
@@ -1437,7 +1450,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
 		etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU),
 				      TRCPDCR);
 out:
-	CS_LOCK(drvdata->base);
+	etm4_cs_lock(drvdata, csa);
 	return ret;
 }
 
@@ -1448,8 +1461,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
 	struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base);
 	struct csdev_access *csa = &tmp_csa;
 
-	CS_UNLOCK(drvdata->base);
-
+	etm4_cs_unlock(drvdata, csa);
 	etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
 
 	etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR);
@@ -1534,7 +1546,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
 
 	/* Unlock the OS lock to re-enable trace and external debug access */
 	etm4_os_unlock(drvdata);
-	CS_LOCK(drvdata->base);
+	etm4_cs_lock(drvdata, csa);
 }
 
 static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
-- 
2.24.1


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  parent reply	other threads:[~2021-01-07 12:43 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-07 12:38 [PATCH v6 00/26] coresight: etm4x: Support for system instructions Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 01/26] coresight: etm4x: Handle access to TRCSSPCICRn Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 02/26] coresight: etm4x: Skip accessing TRCPDCR in save/restore Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 03/26] coresight: Introduce device access abstraction Suzuki K Poulose
2021-01-07 23:38   ` Mathieu Poirier
2021-01-07 12:38 ` [PATCH v6 04/26] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 05/26] coresight: Convert coresight_timeout to use " Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 06/26] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 07/26] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 08/26] coresight: etm4x: Convert all register accesses Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 09/26] coresight: etm4x: Add commentary on the registers Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 10/26] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 11/26] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose
2021-01-07 12:38 ` Suzuki K Poulose [this message]
2021-01-08  0:18   ` [PATCH v6 12/26] coresight: etm4x: Check for Software Lock Mathieu Poirier
2021-01-07 12:38 ` [PATCH v6 13/26] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 14/26] coresight: etm4x: Clean up " Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 15/26] coresight: etm4x: Handle ETM architecture version Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 16/26] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 17/26] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 18/26] coresight: etm4x: Expose trcdevarch via sysfs Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 19/26] coresight: etm4x: Add necessary synchronization for sysreg access Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 20/26] coresight: etm4x: Detect system instructions support Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 21/26] coresight: etm4x: Refactor probing routine Suzuki K Poulose
2021-01-08  0:38   ` Mathieu Poirier
2021-01-07 12:38 ` [PATCH v6 22/26] coresight: etm4x: Run arch feature detection on the CPU Suzuki K Poulose
2021-01-08  0:49   ` Mathieu Poirier
2021-01-07 12:38 ` [PATCH v6 23/26] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose
2021-01-08  0:55   ` Mathieu Poirier
2021-01-07 12:38 ` [PATCH v6 24/26] dts: bindings: coresight: ETM system register access only units Suzuki K Poulose
2021-01-07 12:38 ` [PATCH v6 25/26] arm64: Add TRFCR_ELx definitions Suzuki K Poulose
2021-01-08  1:01   ` Mathieu Poirier
2021-01-07 12:38 ` [PATCH v6 26/26] coresight: Add support for v8.4 SelfHosted tracing Suzuki K Poulose
2021-01-08  1:02   ` Mathieu Poirier
2021-01-08  1:09 ` [PATCH v6 00/26] coresight: etm4x: Support for system instructions Mathieu Poirier
2021-01-08  9:08   ` Suzuki K Poulose
2021-01-08 14:15     ` Suzuki K Poulose

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