[v7,0/2] introduce TI reset controller for MT8192 SoC

[v7,0/2] introduce TI reset controller for MT8192 SoC

[Crystal Guo]

v7:
1. [v7,1/2] remove "mediatek,reset-bit" property from mediatek-syscon-reset.yaml in [v6,1/3]
2. [v7,2/2] use the flag "MTK_SYSCON_RESET_FLAG" to determine whether to call "mtk_syscon_reset",
which integrate assert and deassert together.
3. The patch "[v6,3/3] reset-controller:ti:force the write operation when assert or deassert" has been applied

v6:
fix the format error of mediatek-syscon-reset.yaml

v5:
1. revert ti-syscon-reset.txt, and add a new mediatek reset binding.
2. split the patch [v4, 3/4] with the change to force write and the
change to integrate assert and deassert together.
3. separate the dts patch from this patch sets

v4:
fix typos on v3 commit message.

v3:
1. revert v2 changes.
2. add 'reset-duration-us' property to declare a minimum delay,
which needs to be waited between assert and deassert.
3. add 'mediatek,infra-reset' to compatible.

v2 changes:
https://patchwork.kernel.org/patch/11697371/
1. add 'assert-deassert-together' property to introduce a new reset handler,
which allows device to do serialized assert and deassert operations in a single
step by 'reset' method.
2. add 'update-force' property to introduce force-update method, which forces
the write operation in case the read already happens to return the correct value.
3. add 'generic-reset' to compatible

v1 changes:
https://patchwork.kernel.org/patch/11690523/
https://patchwork.kernel.org/patch/11690527/


Crystal Guo (2):
  dt-binding: reset-controller: mediatek: add YAML schemas
  reset-controller: ti: introduce an integrated reset handler

 .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++++++++++++++++++
 drivers/reset/reset-ti-syscon.c               | 39 ++++++++++++++
 2 files changed, 90 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
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[v7,1/2] dt-binding: reset-controller: mediatek: add YAML schemas

[Crystal Guo]

Add a YAML documentation for Mediatek, which uses ti reset-controller
driver directly. The TI reset controller provides a common reset
management, and is suitable for Mediatek SoCs.

Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>
---
 .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++++++++++++++++++
 1 file changed, 51 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml

diff --git a/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
new file mode 100644
index 000000000000..85d241cdb0ea
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/mediatek-syscon-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Reset Controller
+
+maintainers:
+  - Crystal Guo <crystal.guo@mediatek.com>
+
+description:
+  The bindings describe the reset-controller for Mediatek SoCs,
+  which is based on TI reset controller. For more detail, please
+  visit Documentation/devicetree/bindings/reset/ti-syscon-reset.txt.
+
+properties:
+  compatible:
+    const: mediatek,syscon-reset
+
+  '#reset-cells':
+    const: 1
+
+  ti,reset-bits:
+    description: >
+      Contains the reset control register information, please refer to
+      Documentation/devicetree/bindings/reset/ti-syscon-reset.txt.
+
+required:
+  - compatible
+  - '#reset-cells'
+  - ti,reset-bits
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/reset/ti-syscon.h>
+    infracfg: infracfg@10001000 {
+        compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
+        reg = <0 0x10001000>;
+        #clock-cells = <1>;
+
+        infracfg_rst: reset-controller {
+            compatible = "mediatek,syscon-reset";
+            #reset-cells = <1>;
+            ti,reset-bits = <
+               0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE)
+            >;
+        };
+    };
-- 
2.18.0
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[v7,2/2] reset-controller: ti: introduce an integrated reset handler

[Crystal Guo]

Introduce ti_syscon_reset() to integrate assert and deassert together.
If some modules need do serialized assert and deassert operations
to reset itself, reset_control_reset can be called for convenience.

Such as reset-qcom-aoss.c, it integrates assert and deassert together
by 'reset' method. MTK Socs also need this method to perform reset.

Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>
---
 drivers/reset/reset-ti-syscon.c | 39 +++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c
index 218370faf37b..a30cb17362a4 100644
--- a/drivers/reset/reset-ti-syscon.c
+++ b/drivers/reset/reset-ti-syscon.c
@@ -15,15 +15,24 @@
  * GNU General Public License for more details.
  */
 
+#include <linux/delay.h>
 #include <linux/mfd/syscon.h>
 #include <linux/module.h>
 #include <linux/of.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
 #include <linux/reset-controller.h>
 
 #include <dt-bindings/reset/ti-syscon.h>
 
+#define MTK_SYSCON_RESET_FLAG	BIT(0)
+#define MT_RESET_DURATION	10
+
+struct mediatek_reset_data {
+	unsigned int flag;
+};
+
 /**
  * struct ti_syscon_reset_control - reset control structure
  * @assert_offset: reset assert control register offset from syscon base
@@ -56,6 +65,7 @@ struct ti_syscon_reset_data {
 	struct regmap *regmap;
 	struct ti_syscon_reset_control *controls;
 	unsigned int nr_controls;
+	const struct mediatek_reset_data *reset_data;
 };
 
 #define to_ti_syscon_reset_data(rcdev)	\
@@ -158,9 +168,32 @@ static int ti_syscon_reset_status(struct reset_controller_dev *rcdev,
 		!(control->flags & STATUS_SET);
 }
 
+static int mtk_syscon_reset(struct reset_controller_dev *rcdev, unsigned long id)
+{
+	int ret;
+
+	ret = ti_syscon_reset_assert(rcdev, id);
+	if (ret)
+		return ret;
+	usleep_range(MT_RESET_DURATION, MT_RESET_DURATION * 2);
+
+	return ti_syscon_reset_deassert(rcdev, id);
+}
+
+static int ti_syscon_reset(struct reset_controller_dev *rcdev, unsigned long id)
+{
+	struct ti_syscon_reset_data *data = to_ti_syscon_reset_data(rcdev);
+
+	if (data->reset_data && data->reset_data->flag & MTK_SYSCON_RESET_FLAG)
+		return mtk_syscon_reset(rcdev, id);
+	else
+		return -ENOTSUPP;
+}
+
 static const struct reset_control_ops ti_syscon_reset_ops = {
 	.assert		= ti_syscon_reset_assert,
 	.deassert	= ti_syscon_reset_deassert,
+	.reset		= ti_syscon_reset,
 	.status		= ti_syscon_reset_status,
 };
 
@@ -182,6 +215,7 @@ static int ti_syscon_reset_probe(struct platform_device *pdev)
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
 
+	data->reset_data = of_device_get_match_data(&pdev->dev);
 	list = of_get_property(np, "ti,reset-bits", &size);
 	if (!list || (size / sizeof(*list)) % 7 != 0) {
 		dev_err(dev, "invalid DT reset description\n");
@@ -217,8 +251,13 @@ static int ti_syscon_reset_probe(struct platform_device *pdev)
 	return devm_reset_controller_register(dev, &data->rcdev);
 }
 
+static const struct mediatek_reset_data mtk_reset_data = {
+	.flag = MTK_SYSCON_RESET_FLAG,
+};
+
 static const struct of_device_id ti_syscon_reset_of_match[] = {
 	{ .compatible = "ti,syscon-reset", },
+	{ .compatible = "mediatek,syscon-reset", .data = &mtk_reset_data},
 	{ /* sentinel */ },
 };
 MODULE_DEVICE_TABLE(of, ti_syscon_reset_of_match);
-- 
2.18.0
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Re: [v7, 1/2] dt-binding: reset-controller: mediatek: add YAML schemas

[Ikjoon Jang]

On Fri, Jan 15, 2021 at 7:23 PM Crystal Guo <crystal.guo@mediatek.com> wrote:
>
> Add a YAML documentation for Mediatek, which uses ti reset-controller
> driver directly. The TI reset controller provides a common reset
> management, and is suitable for Mediatek SoCs.
>
> Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>
> ---
>  .../bindings/reset/mediatek-syscon-reset.yaml | 51 +++++++++++++++++++
>  1 file changed, 51 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
>
> diff --git a/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
> new file mode 100644
> index 000000000000..85d241cdb0ea
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/mediatek-syscon-reset.yaml
> @@ -0,0 +1,51 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/mediatek-syscon-reset.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Reset Controller
> +
> +maintainers:
> +  - Crystal Guo <crystal.guo@mediatek.com>
> +
> +description:
> +  The bindings describe the reset-controller for Mediatek SoCs,
> +  which is based on TI reset controller. For more detail, please
> +  visit Documentation/devicetree/bindings/reset/ti-syscon-reset.txt.
> +
> +properties:
> +  compatible:
> +    const: mediatek,syscon-reset
> +
> +  '#reset-cells':
> +    const: 1
> +
> +  ti,reset-bits:
> +    description: >
> +      Contains the reset control register information, please refer to
> +      Documentation/devicetree/bindings/reset/ti-syscon-reset.txt.
> +

I remember that Rob didn't like adding new users of this property,

How about removing this from here and using a hardcoded version of
register layouts into driver code (and match it with compatible) ?

e.g.
struct ti_syscon_reset_data mt8192_reset_data { ... }

> +required:
> +  - compatible
> +  - '#reset-cells'
> +  - ti,reset-bits
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/reset/ti-syscon.h>
> +    infracfg: infracfg@10001000 {
> +        compatible = "mediatek,mt8192-infracfg", "syscon", "simple-mfd";
> +        reg = <0 0x10001000>;
> +        #clock-cells = <1>;
> +
> +        infracfg_rst: reset-controller {
> +            compatible = "mediatek,syscon-reset";
> +            #reset-cells = <1>;
> +            ti,reset-bits = <
> +               0x140 15 0x144 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE)
> +            >;
> +        };
> +    };
> --
> 2.18.0
>

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