* [PATCH v2 0/3] Enable 8D-8D-8D mode on J721E, J7200, AM654
@ 2021-03-05 15:39 Pratyush Yadav
2021-03-05 15:39 ` [PATCH v2 1/3] arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPI Pratyush Yadav
` (3 more replies)
0 siblings, 4 replies; 12+ messages in thread
From: Pratyush Yadav @ 2021-03-05 15:39 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Rob Herring, linux-arm-kernel,
devicetree, linux-kernel
Cc: Pratyush Yadav, Vignesh Raghavendra
Hi,
Now that the OSPI controller driver and the SPI NOR core have support
for 8D-8D-8D mode, the device tree can be updated to allow Octal DTR
transactions.
Pratyush Yadav (3):
arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPI
arm64: dts: ti: am654-base-board: Enable 8D-8D-8D mode on OSPI
arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0
.../arm64/boot/dts/ti/k3-am654-base-board.dts | 4 +--
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 17 +++++++++
arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 36 +++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 4 +--
4 files changed, 57 insertions(+), 4 deletions(-)
--
2.30.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 1/3] arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPI 2021-03-05 15:39 [PATCH v2 0/3] Enable 8D-8D-8D mode on J721E, J7200, AM654 Pratyush Yadav @ 2021-03-05 15:39 ` Pratyush Yadav 2021-03-05 16:12 ` Vignesh Raghavendra 2021-03-05 15:39 ` [PATCH v2 2/3] arm64: dts: ti: am654-base-board: " Pratyush Yadav ` (2 subsequent siblings) 3 siblings, 1 reply; 12+ messages in thread From: Pratyush Yadav @ 2021-03-05 15:39 UTC (permalink / raw) To: Nishanth Menon, Tero Kristo, Rob Herring, linux-arm-kernel, devicetree, linux-kernel Cc: Pratyush Yadav, Vignesh Raghavendra Set the Tx bus width to 8 so 8D-8D-8D mode can be selected. Change the frequency to 25 MHz. This is the frequency that the flash has been successfully tested with in Octal DTR mode. The total performance should still increase since 8D-8D-8D mode should be at least twice as fast as 1S-1S-8S mode. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> --- Notes: No changes in v2. arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 57720e6a04c5..2fee2906183d 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -174,9 +174,9 @@ &ospi0 { flash@0{ compatible = "jedec,spi-nor"; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; - spi-max-frequency = <40000000>; + spi-max-frequency = <25000000>; cdns,tshsl-ns = <60>; cdns,tsd2d-ns = <60>; cdns,tchsh-ns = <60>; -- 2.30.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 1/3] arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPI 2021-03-05 15:39 ` [PATCH v2 1/3] arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPI Pratyush Yadav @ 2021-03-05 16:12 ` Vignesh Raghavendra 0 siblings, 0 replies; 12+ messages in thread From: Vignesh Raghavendra @ 2021-03-05 16:12 UTC (permalink / raw) To: Pratyush Yadav, Nishanth Menon, Tero Kristo, Rob Herring, linux-arm-kernel, devicetree, linux-kernel On 3/5/21 9:09 PM, Pratyush Yadav wrote: > Set the Tx bus width to 8 so 8D-8D-8D mode can be selected. Change the > frequency to 25 MHz. This is the frequency that the flash has been > successfully tested with in Octal DTR mode. The total performance should > still increase since 8D-8D-8D mode should be at least twice as fast as > 1S-1S-8S mode. > > Signed-off-by: Pratyush Yadav <p.yadav@ti.com> > --- > Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> > Notes: > No changes in v2. > > arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi > index 57720e6a04c5..2fee2906183d 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi > @@ -174,9 +174,9 @@ &ospi0 { > flash@0{ > compatible = "jedec,spi-nor"; > reg = <0x0>; > - spi-tx-bus-width = <1>; > + spi-tx-bus-width = <8>; > spi-rx-bus-width = <8>; > - spi-max-frequency = <40000000>; > + spi-max-frequency = <25000000>; > cdns,tshsl-ns = <60>; > cdns,tsd2d-ns = <60>; > cdns,tchsh-ns = <60>; > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 2/3] arm64: dts: ti: am654-base-board: Enable 8D-8D-8D mode on OSPI 2021-03-05 15:39 [PATCH v2 0/3] Enable 8D-8D-8D mode on J721E, J7200, AM654 Pratyush Yadav 2021-03-05 15:39 ` [PATCH v2 1/3] arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPI Pratyush Yadav @ 2021-03-05 15:39 ` Pratyush Yadav 2021-03-05 16:12 ` Vignesh Raghavendra 2021-03-05 15:39 ` [PATCH v2 3/3] arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0 Pratyush Yadav 2021-03-11 14:17 ` [PATCH v2 0/3] Enable 8D-8D-8D mode on J721E, J7200, AM654 Nishanth Menon 3 siblings, 1 reply; 12+ messages in thread From: Pratyush Yadav @ 2021-03-05 15:39 UTC (permalink / raw) To: Nishanth Menon, Tero Kristo, Rob Herring, linux-arm-kernel, devicetree, linux-kernel Cc: Pratyush Yadav, Vignesh Raghavendra Set the Tx bus width to 8 so 8D-8D-8D mode can be selected. Change the frequency to 25 MHz. This is the frequency that the flash has been successfully tested with in Octal DTR mode. The total performance should still increase since 8D-8D-8D mode should be at least twice as fast as 1S-1S-8S mode. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> --- Notes: No changes in v2. arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index fe3043943906..9e87fb313a54 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -483,9 +483,9 @@ &ospi0 { flash@0{ compatible = "jedec,spi-nor"; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <8>; spi-rx-bus-width = <8>; - spi-max-frequency = <40000000>; + spi-max-frequency = <25000000>; cdns,tshsl-ns = <60>; cdns,tsd2d-ns = <60>; cdns,tchsh-ns = <60>; -- 2.30.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: ti: am654-base-board: Enable 8D-8D-8D mode on OSPI 2021-03-05 15:39 ` [PATCH v2 2/3] arm64: dts: ti: am654-base-board: " Pratyush Yadav @ 2021-03-05 16:12 ` Vignesh Raghavendra 0 siblings, 0 replies; 12+ messages in thread From: Vignesh Raghavendra @ 2021-03-05 16:12 UTC (permalink / raw) To: Pratyush Yadav, Nishanth Menon, Tero Kristo, Rob Herring, linux-arm-kernel, devicetree, linux-kernel On 3/5/21 9:09 PM, Pratyush Yadav wrote: > Set the Tx bus width to 8 so 8D-8D-8D mode can be selected. Change the > frequency to 25 MHz. This is the frequency that the flash has been > successfully tested with in Octal DTR mode. The total performance should > still increase since 8D-8D-8D mode should be at least twice as fast as > 1S-1S-8S mode. > > Signed-off-by: Pratyush Yadav <p.yadav@ti.com> > --- > Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> > Notes: > No changes in v2. > > arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts > index fe3043943906..9e87fb313a54 100644 > --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts > +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts > @@ -483,9 +483,9 @@ &ospi0 { > flash@0{ > compatible = "jedec,spi-nor"; > reg = <0x0>; > - spi-tx-bus-width = <1>; > + spi-tx-bus-width = <8>; > spi-rx-bus-width = <8>; > - spi-max-frequency = <40000000>; > + spi-max-frequency = <25000000>; > cdns,tshsl-ns = <60>; > cdns,tsd2d-ns = <60>; > cdns,tchsh-ns = <60>; > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 3/3] arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0 2021-03-05 15:39 [PATCH v2 0/3] Enable 8D-8D-8D mode on J721E, J7200, AM654 Pratyush Yadav 2021-03-05 15:39 ` [PATCH v2 1/3] arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPI Pratyush Yadav 2021-03-05 15:39 ` [PATCH v2 2/3] arm64: dts: ti: am654-base-board: " Pratyush Yadav @ 2021-03-05 15:39 ` Pratyush Yadav 2021-03-05 16:13 ` Vignesh Raghavendra 2021-03-09 17:01 ` Nishanth Menon 2021-03-11 14:17 ` [PATCH v2 0/3] Enable 8D-8D-8D mode on J721E, J7200, AM654 Nishanth Menon 3 siblings, 2 replies; 12+ messages in thread From: Pratyush Yadav @ 2021-03-05 15:39 UTC (permalink / raw) To: Nishanth Menon, Tero Kristo, Rob Herring, linux-arm-kernel, devicetree, linux-kernel Cc: Pratyush Yadav, Vignesh Raghavendra TI J7200 has the Cadence OSPI controller for interfacing with OSPI flashes. Add its node to allow using SPI flashes. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> --- Notes: Changes in v2: - Do not force a pulldown on the DQS line because it already has a pulldown resistor. .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 17 +++++++++ arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 36 +++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 359e3e8a8cd0..5408ec815d58 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -269,6 +269,23 @@ hbmc: hyperbus@47034000 { #size-cells = <1>; mux-controls = <&hbmc_mux 0>; }; + + ospi0: spi@47040000 { + compatible = "ti,am654-ospi"; + reg = <0x0 0x47040000 0x0 0x100>, + <0x5 0x00000000 0x1 0x0000000>; + interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 103 0>; + assigned-clocks = <&k3_clks 103 0>; + assigned-clock-parents = <&k3_clks 103 2>; + assigned-clock-rates = <166666666>; + power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + }; }; tscadc0: tscadc@40200000 { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index a988e2ab2ba1..34724440171a 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -100,6 +100,22 @@ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ >; }; + + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ + J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ + J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ + J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ + J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ + J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ + J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ + J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ + J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ + J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ + J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ + >; + }; }; &main_pmx0 { @@ -235,3 +251,23 @@ exp_som: gpio@21 { "GPIO_LIN_EN", "CAN_STB"; }; }; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; -- 2.30.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0 2021-03-05 15:39 ` [PATCH v2 3/3] arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0 Pratyush Yadav @ 2021-03-05 16:13 ` Vignesh Raghavendra 2021-03-11 13:22 ` Nishanth Menon 2021-03-09 17:01 ` Nishanth Menon 1 sibling, 1 reply; 12+ messages in thread From: Vignesh Raghavendra @ 2021-03-05 16:13 UTC (permalink / raw) To: Pratyush Yadav, Nishanth Menon, Tero Kristo, Rob Herring, linux-arm-kernel, devicetree, linux-kernel On 3/5/21 9:09 PM, Pratyush Yadav wrote: > TI J7200 has the Cadence OSPI controller for interfacing with OSPI > flashes. Add its node to allow using SPI flashes. > > Signed-off-by: Pratyush Yadav <p.yadav@ti.com> > --- Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> > > Notes: > Changes in v2: > - Do not force a pulldown on the DQS line because it already has a > pulldown resistor. > > .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 17 +++++++++ > arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 36 +++++++++++++++++++ > 2 files changed, 53 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi > index 359e3e8a8cd0..5408ec815d58 100644 > --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi > @@ -269,6 +269,23 @@ hbmc: hyperbus@47034000 { > #size-cells = <1>; > mux-controls = <&hbmc_mux 0>; > }; > + > + ospi0: spi@47040000 { > + compatible = "ti,am654-ospi"; > + reg = <0x0 0x47040000 0x0 0x100>, > + <0x5 0x00000000 0x1 0x0000000>; > + interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; > + cdns,fifo-depth = <256>; > + cdns,fifo-width = <4>; > + cdns,trigger-address = <0x0>; > + clocks = <&k3_clks 103 0>; > + assigned-clocks = <&k3_clks 103 0>; > + assigned-clock-parents = <&k3_clks 103 2>; > + assigned-clock-rates = <166666666>; > + power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > }; > > tscadc0: tscadc@40200000 { > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi > index a988e2ab2ba1..34724440171a 100644 > --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi > @@ -100,6 +100,22 @@ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ > J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ > >; > }; > + > + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { > + pinctrl-single,pins = < > + J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ > + J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ > + J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ > + J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ > + J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ > + J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ > + J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ > + J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ > + J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ > + J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ > + J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ > + >; > + }; > }; > > &main_pmx0 { > @@ -235,3 +251,23 @@ exp_som: gpio@21 { > "GPIO_LIN_EN", "CAN_STB"; > }; > }; > + > +&ospi0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; > + > + flash@0{ > + compatible = "jedec,spi-nor"; > + reg = <0x0>; > + spi-tx-bus-width = <8>; > + spi-rx-bus-width = <8>; > + spi-max-frequency = <25000000>; > + cdns,tshsl-ns = <60>; > + cdns,tsd2d-ns = <60>; > + cdns,tchsh-ns = <60>; > + cdns,tslch-ns = <60>; > + cdns,read-delay = <4>; > + #address-cells = <1>; > + #size-cells = <1>; > + }; > +}; > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0 2021-03-05 16:13 ` Vignesh Raghavendra @ 2021-03-11 13:22 ` Nishanth Menon 2021-03-11 13:41 ` Pratyush Yadav 0 siblings, 1 reply; 12+ messages in thread From: Nishanth Menon @ 2021-03-11 13:22 UTC (permalink / raw) To: Vignesh Raghavendra Cc: Pratyush Yadav, Tero Kristo, Rob Herring, linux-arm-kernel, devicetree, linux-kernel On 21:43-20210305, Vignesh Raghavendra wrote: > > > On 3/5/21 9:09 PM, Pratyush Yadav wrote: > > TI J7200 has the Cadence OSPI controller for interfacing with OSPI > > flashes. Add its node to allow using SPI flashes. > > > > Signed-off-by: Pratyush Yadav <p.yadav@ti.com> > > --- > > Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> > > > > > > > Notes: > > Changes in v2: > > - Do not force a pulldown on the DQS line because it already has a > > pulldown resistor. > > > > .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 17 +++++++++ > > arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 36 +++++++++++++++++++ > > 2 files changed, 53 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi > > index 359e3e8a8cd0..5408ec815d58 100644 > > --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi > > +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi > > @@ -269,6 +269,23 @@ hbmc: hyperbus@47034000 { > > #size-cells = <1>; > > mux-controls = <&hbmc_mux 0>; > > }; > > + > > + ospi0: spi@47040000 { > > + compatible = "ti,am654-ospi"; > > + reg = <0x0 0x47040000 0x0 0x100>, > > + <0x5 0x00000000 0x1 0x0000000>; > > + interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; > > + cdns,fifo-depth = <256>; > > + cdns,fifo-width = <4>; > > + cdns,trigger-address = <0x0>; > > + clocks = <&k3_clks 103 0>; > > + assigned-clocks = <&k3_clks 103 0>; > > + assigned-clock-parents = <&k3_clks 103 2>; > > + assigned-clock-rates = <166666666>; > > + power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > }; > > > > tscadc0: tscadc@40200000 { > > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi > > index a988e2ab2ba1..34724440171a 100644 > > --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi > > +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi > > @@ -100,6 +100,22 @@ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ > > J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ > > >; > > }; > > + > > + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { > > + pinctrl-single,pins = < > > + J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ > > + J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ > > + J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ > > + J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ > > + J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ > > + J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ > > + J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ > > + J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ > > + J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ > > + J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ > > + J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ > > + >; > > + }; > > }; > > > > &main_pmx0 { > > @@ -235,3 +251,23 @@ exp_som: gpio@21 { > > "GPIO_LIN_EN", "CAN_STB"; > > }; > > }; > > + > > +&ospi0 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; > > + > > + flash@0{ > > + compatible = "jedec,spi-nor"; > > + reg = <0x0>; > > + spi-tx-bus-width = <8>; > > + spi-rx-bus-width = <8>; > > + spi-max-frequency = <25000000>; > > + cdns,tshsl-ns = <60>; > > + cdns,tsd2d-ns = <60>; > > + cdns,tchsh-ns = <60>; > > + cdns,tslch-ns = <60>; > > + cdns,read-delay = <4>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + }; I see this: +/workdir/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dt.yaml: flash@0: 'cdns,read-delay', 'cdns,tchsh-ns', 'cdns,tsd2d-ns', 'cdns,tshsl-ns', 'cdns,tslch-ns' do not match any of the regexes: '^partition@', 'pinctrl-[0-9]+' And that is because Documentation/devicetree/bindings/spi/cadence-quadspi.txt is not converted to yaml. Following the new stringent rules, yaml please? -- Regards, Nishanth Menon Key (0xDDB5849D1736249D)/Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0 2021-03-11 13:22 ` Nishanth Menon @ 2021-03-11 13:41 ` Pratyush Yadav 2021-03-11 13:49 ` Nishanth Menon 0 siblings, 1 reply; 12+ messages in thread From: Pratyush Yadav @ 2021-03-11 13:41 UTC (permalink / raw) To: Nishanth Menon Cc: Vignesh Raghavendra, Tero Kristo, Rob Herring, linux-arm-kernel, devicetree, linux-kernel On 11/03/21 07:22AM, Nishanth Menon wrote: > On 21:43-20210305, Vignesh Raghavendra wrote: > > > > > > On 3/5/21 9:09 PM, Pratyush Yadav wrote: > > > TI J7200 has the Cadence OSPI controller for interfacing with OSPI > > > flashes. Add its node to allow using SPI flashes. > > > > > > Signed-off-by: Pratyush Yadav <p.yadav@ti.com> > > > --- > > > > Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> > > > > > > > > > > > > Notes: > > > Changes in v2: > > > - Do not force a pulldown on the DQS line because it already has a > > > pulldown resistor. > > > > > > .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 17 +++++++++ > > > arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 36 +++++++++++++++++++ > > > 2 files changed, 53 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi > > > index 359e3e8a8cd0..5408ec815d58 100644 > > > --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi > > > +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi > > > @@ -269,6 +269,23 @@ hbmc: hyperbus@47034000 { > > > #size-cells = <1>; > > > mux-controls = <&hbmc_mux 0>; > > > }; > > > + > > > + ospi0: spi@47040000 { > > > + compatible = "ti,am654-ospi"; > > > + reg = <0x0 0x47040000 0x0 0x100>, > > > + <0x5 0x00000000 0x1 0x0000000>; > > > + interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; > > > + cdns,fifo-depth = <256>; > > > + cdns,fifo-width = <4>; > > > + cdns,trigger-address = <0x0>; > > > + clocks = <&k3_clks 103 0>; > > > + assigned-clocks = <&k3_clks 103 0>; > > > + assigned-clock-parents = <&k3_clks 103 2>; > > > + assigned-clock-rates = <166666666>; > > > + power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + }; > > > }; > > > > > > tscadc0: tscadc@40200000 { > > > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi > > > index a988e2ab2ba1..34724440171a 100644 > > > --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi > > > +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi > > > @@ -100,6 +100,22 @@ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ > > > J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ > > > >; > > > }; > > > + > > > + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { > > > + pinctrl-single,pins = < > > > + J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ > > > + J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ > > > + J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ > > > + J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ > > > + J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ > > > + J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ > > > + J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ > > > + J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ > > > + J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ > > > + J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ > > > + J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ > > > + >; > > > + }; > > > }; > > > > > > &main_pmx0 { > > > @@ -235,3 +251,23 @@ exp_som: gpio@21 { > > > "GPIO_LIN_EN", "CAN_STB"; > > > }; > > > }; > > > + > > > +&ospi0 { > > > + pinctrl-names = "default"; > > > + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; > > > + > > > + flash@0{ > > > + compatible = "jedec,spi-nor"; > > > + reg = <0x0>; > > > + spi-tx-bus-width = <8>; > > > + spi-rx-bus-width = <8>; > > > + spi-max-frequency = <25000000>; > > > + cdns,tshsl-ns = <60>; > > > + cdns,tsd2d-ns = <60>; > > > + cdns,tchsh-ns = <60>; > > > + cdns,tslch-ns = <60>; > > > + cdns,read-delay = <4>; > > > + #address-cells = <1>; > > > + #size-cells = <1>; > > > + }; > I see this: > +/workdir/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dt.yaml: flash@0: 'cdns,read-delay', 'cdns,tchsh-ns', 'cdns,tsd2d-ns', 'cdns,tshsl-ns', 'cdns,tslch-ns' do not match any of the regexes: '^partition@', 'pinctrl-[0-9]+' > > > And that is because > Documentation/devicetree/bindings/spi/cadence-quadspi.txt is not > converted to yaml. Following the new stringent rules, yaml please? Ok. I am working on the conversion. Will send it soon. -- Regards, Pratyush Yadav Texas Instruments Inc. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0 2021-03-11 13:41 ` Pratyush Yadav @ 2021-03-11 13:49 ` Nishanth Menon 0 siblings, 0 replies; 12+ messages in thread From: Nishanth Menon @ 2021-03-11 13:49 UTC (permalink / raw) To: Pratyush Yadav Cc: Vignesh Raghavendra, Tero Kristo, Rob Herring, linux-arm-kernel, devicetree, linux-kernel On 19:11-20210311, Pratyush Yadav wrote: > On 11/03/21 07:22AM, Nishanth Menon wrote: > > On 21:43-20210305, Vignesh Raghavendra wrote: > > > > > > > > > On 3/5/21 9:09 PM, Pratyush Yadav wrote: > > > > TI J7200 has the Cadence OSPI controller for interfacing with OSPI > > > > flashes. Add its node to allow using SPI flashes. > > > > > > > > Signed-off-by: Pratyush Yadav <p.yadav@ti.com> > > > > --- > > > > > > Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> > > > > > > > > > > > > > > > > > Notes: > > > > Changes in v2: > > > > - Do not force a pulldown on the DQS line because it already has a > > > > pulldown resistor. > > > > > > > > .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 17 +++++++++ > > > > arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 36 +++++++++++++++++++ > > > > 2 files changed, 53 insertions(+) > > > > > > > > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi > > > > index 359e3e8a8cd0..5408ec815d58 100644 > > > > --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi > > > > +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi > > > > @@ -269,6 +269,23 @@ hbmc: hyperbus@47034000 { > > > > #size-cells = <1>; > > > > mux-controls = <&hbmc_mux 0>; > > > > }; > > > > + > > > > + ospi0: spi@47040000 { > > > > + compatible = "ti,am654-ospi"; > > > > + reg = <0x0 0x47040000 0x0 0x100>, > > > > + <0x5 0x00000000 0x1 0x0000000>; > > > > + interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; > > > > + cdns,fifo-depth = <256>; > > > > + cdns,fifo-width = <4>; > > > > + cdns,trigger-address = <0x0>; > > > > + clocks = <&k3_clks 103 0>; > > > > + assigned-clocks = <&k3_clks 103 0>; > > > > + assigned-clock-parents = <&k3_clks 103 2>; > > > > + assigned-clock-rates = <166666666>; > > > > + power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; > > > > + #address-cells = <1>; > > > > + #size-cells = <0>; > > > > + }; > > > > }; > > > > > > > > tscadc0: tscadc@40200000 { > > > > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi > > > > index a988e2ab2ba1..34724440171a 100644 > > > > --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi > > > > +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi > > > > @@ -100,6 +100,22 @@ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ > > > > J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ > > > > >; > > > > }; > > > > + > > > > + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { > > > > + pinctrl-single,pins = < > > > > + J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */ > > > > + J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ > > > > + J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* MCU_OSPI0_D0 */ > > > > + J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* MCU_OSPI0_D1 */ > > > > + J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* MCU_OSPI0_D2 */ > > > > + J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* MCU_OSPI0_D3 */ > > > > + J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* MCU_OSPI0_D4 */ > > > > + J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* MCU_OSPI0_D5 */ > > > > + J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* MCU_OSPI0_D6 */ > > > > + J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* MCU_OSPI0_D7 */ > > > > + J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* MCU_OSPI0_DQS */ > > > > + >; > > > > + }; > > > > }; > > > > > > > > &main_pmx0 { > > > > @@ -235,3 +251,23 @@ exp_som: gpio@21 { > > > > "GPIO_LIN_EN", "CAN_STB"; > > > > }; > > > > }; > > > > + > > > > +&ospi0 { > > > > + pinctrl-names = "default"; > > > > + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; > > > > + > > > > + flash@0{ > > > > + compatible = "jedec,spi-nor"; > > > > + reg = <0x0>; > > > > + spi-tx-bus-width = <8>; > > > > + spi-rx-bus-width = <8>; > > > > + spi-max-frequency = <25000000>; > > > > + cdns,tshsl-ns = <60>; > > > > + cdns,tsd2d-ns = <60>; > > > > + cdns,tchsh-ns = <60>; > > > > + cdns,tslch-ns = <60>; > > > > + cdns,read-delay = <4>; > > > > + #address-cells = <1>; > > > > + #size-cells = <1>; > > > > + }; > > I see this: > > +/workdir/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dt.yaml: flash@0: 'cdns,read-delay', 'cdns,tchsh-ns', 'cdns,tsd2d-ns', 'cdns,tshsl-ns', 'cdns,tslch-ns' do not match any of the regexes: '^partition@', 'pinctrl-[0-9]+' > > > > > > And that is because > > Documentation/devicetree/bindings/spi/cadence-quadspi.txt is not > > converted to yaml. Following the new stringent rules, yaml please? > > Ok. I am working on the conversion. Will send it soon. OK I am keeping to our old rule that as long as binding is pre-existing and they are in Documentation/devicetree/ we are picking the node up.. new bindings absolutely must be in yaml. But really, it is high time these txt files get converted to yaml.. Lets use this current collection for 5.13-rc1 cycle as the last window where we permit this. * 5.14-rc1 cycle patches, lets make sure: no txt file bindings, yaml at least in next * 5.15-rc1 cycle patches, yaml binding must be in master OR a immutable tag from subsystem maintainer. new bindings already need to be yaml. -- Regards, Nishanth Menon Key (0xDDB5849D1736249D)/Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 3/3] arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0 2021-03-05 15:39 ` [PATCH v2 3/3] arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0 Pratyush Yadav 2021-03-05 16:13 ` Vignesh Raghavendra @ 2021-03-09 17:01 ` Nishanth Menon 1 sibling, 0 replies; 12+ messages in thread From: Nishanth Menon @ 2021-03-09 17:01 UTC (permalink / raw) To: Pratyush Yadav Cc: Tero Kristo, Rob Herring, linux-arm-kernel, devicetree, linux-kernel, Vignesh Raghavendra On 21:09-20210305, Pratyush Yadav wrote: > TI J7200 has the Cadence OSPI controller for interfacing with OSPI > flashes. Add its node to allow using SPI flashes. > > Signed-off-by: Pratyush Yadav <p.yadav@ti.com> > --- > > Notes: > Changes in v2: > - Do not force a pulldown on the DQS line because it already has a > pulldown resistor. > > .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 17 +++++++++ > arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi | 36 +++++++++++++++++++ > 2 files changed, 53 insertions(+) I see this with dtbs_check on v5.12-rc2: /workdir/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dt.yaml: flash@0: 'cdns,read-delay', 'cdns,tchsh-ns', 'cdns,tsd2d-ns', 'cdns,tshsl-ns', 'cdns,tslch-ns' do not match any of the regexes: '^partition@', 'pinctrl-[0-9]+' -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 0/3] Enable 8D-8D-8D mode on J721E, J7200, AM654 2021-03-05 15:39 [PATCH v2 0/3] Enable 8D-8D-8D mode on J721E, J7200, AM654 Pratyush Yadav ` (2 preceding siblings ...) 2021-03-05 15:39 ` [PATCH v2 3/3] arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0 Pratyush Yadav @ 2021-03-11 14:17 ` Nishanth Menon 3 siblings, 0 replies; 12+ messages in thread From: Nishanth Menon @ 2021-03-11 14:17 UTC (permalink / raw) To: Pratyush Yadav, Rob Herring, devicetree, linux-kernel, linux-arm-kernel, Tero Kristo Cc: Nishanth Menon, Vignesh Raghavendra On Fri, 5 Mar 2021 21:09:23 +0530, Pratyush Yadav wrote: > Now that the OSPI controller driver and the SPI NOR core have support > for 8D-8D-8D mode, the device tree can be updated to allow Octal DTR > transactions. > > Pratyush Yadav (3): > arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPI > arm64: dts: ti: am654-base-board: Enable 8D-8D-8D mode on OSPI > arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0 > > [...] Hi Pratyush Yadav, I have applied the following to branch ti-k3-dts-next on [1]. Thank you! [1/3] arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPI commit: 4c20ee99dd1a36ab89c6a8c51ed25e9328d8a8cc [2/3] arm64: dts: ti: am654-base-board: Enable 8D-8D-8D mode on OSPI commit: 7c172b30a540644fa53051e947d6712be5d6d6ce [3/3] arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0 commit: efbdf2e9183bd5e75c64d251c6b673ca61ea01b3 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent up the chain during the next merge window (or sooner if it is a relevant bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. [1] git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux.git -- Regards, Nishanth Menon Key (0xDDB5849D1736249D)/Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2021-03-11 14:18 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-03-05 15:39 [PATCH v2 0/3] Enable 8D-8D-8D mode on J721E, J7200, AM654 Pratyush Yadav 2021-03-05 15:39 ` [PATCH v2 1/3] arm64: dts: ti: k3-j721e-som-p0: Enable 8D-8D-8D mode on OSPI Pratyush Yadav 2021-03-05 16:12 ` Vignesh Raghavendra 2021-03-05 15:39 ` [PATCH v2 2/3] arm64: dts: ti: am654-base-board: " Pratyush Yadav 2021-03-05 16:12 ` Vignesh Raghavendra 2021-03-05 15:39 ` [PATCH v2 3/3] arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0 Pratyush Yadav 2021-03-05 16:13 ` Vignesh Raghavendra 2021-03-11 13:22 ` Nishanth Menon 2021-03-11 13:41 ` Pratyush Yadav 2021-03-11 13:49 ` Nishanth Menon 2021-03-09 17:01 ` Nishanth Menon 2021-03-11 14:17 ` [PATCH v2 0/3] Enable 8D-8D-8D mode on J721E, J7200, AM654 Nishanth Menon
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).