[boot-wrapper PATCH 0/5] Add Armv8-R AArch64 support

[boot-wrapper PATCH 0/5] Add Armv8-R AArch64 support

[Jaxson Han]

Currently, we cannot boot Linux with boot-wrapper on Armv8-R AArch64:
1. The Armv8-R AArch64 profile does not support the EL3.
2. The Armv8-R AArch64 EL2 only supports a PMSA, which Linux does not 
support. So it's necessary to drop into EL1 before entering the kernel.
3. There is no EL2 booting code for Armv8-R AArch64 and no
configuration for dropping to EL1 in boot-wrapper.

These patches enable boot-wrapper booting Linux with Armv8-R AArch64:
Patch 1 allows boot-wrapper to boot on more platforms.
Patch 2 renames some labels as preparations for booting from lower EL.
Patch 3 prepares for GICv3 initialization with EL2.
Patch 4 adds necessary EL2 registers.
Patch 5 adds auto-detection for Armv8-R AArch64 to drop into EL1
before entering the kernel.

Refs: Arm Architecture Reference Manual Supplement - Armv8, for
Armv8-R AArch64 architecture profile
[https://developer.arm.com/documentation/ddi0600/latest/]

Jaxson Han (5):
  Decouple V2M_SYS config by auto-detect dtb node
  aarch64: Rename labels and prepare for lower EL booting
  gic-v3: Prepare for gicv3 with EL2
  aarch64: Prepare for booting with EL2
  aarch64: Introduce EL2 boot code for Armv8-R AArch64

 Makefile.am                       |   2 +-
 arch/aarch32/include/asm/gic-v3.h |   7 ++
 arch/aarch64/boot.S               | 105 ++++++++++++++++++++++++++----
 arch/aarch64/include/asm/cpu.h    |   3 +
 arch/aarch64/include/asm/gic-v3.h |  38 ++++++++++-
 arch/aarch64/psci.S               |  13 ++--
 arch/aarch64/spin.S               |   8 +--
 arch/aarch64/utils.S              |  10 ++-
 gic-v3.c                          |   2 +-
 platform.c                        |   4 ++
 10 files changed, 162 insertions(+), 30 deletions(-)

-- 
2.25.1


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[boot-wrapper PATCH 1/5] Decouple V2M_SYS config by auto-detect dtb node

[Jaxson Han]

An auto-detect switch is added to make it an option to enable/disable
'arm,vexpress-sysreg', because not all platforms support this feature.

Signed-off-by: Jaxson Han <jaxson.han@arm.com>
---
 Makefile.am | 2 +-
 platform.c  | 4 ++++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/Makefile.am b/Makefile.am
index af694b7..e131207 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -19,7 +19,7 @@ NR_CPUS         := $(shell echo $(CPU_IDS) | tr ',' ' ' | wc -w)
 DEFINES		= -DCNTFRQ=$(CNTFRQ)
 DEFINES		+= -DCPU_IDS=$(CPU_IDS)
 DEFINES		+= -DNR_CPUS=$(NR_CPUS)
-DEFINES		+= -DSYSREGS_BASE=$(SYSREGS_BASE)
+DEFINES		+= $(if $(SYSREGS_BASE), -DSYSREGS_BASE=$(SYSREGS_BASE), )
 DEFINES		+= -DUART_BASE=$(UART_BASE)
 DEFINES		+= -DSTACK_SIZE=256
 
diff --git a/platform.c b/platform.c
index a528a55..d11f568 100644
--- a/platform.c
+++ b/platform.c
@@ -23,10 +23,12 @@
 
 #define PL011(reg)	((void *)UART_BASE + PL011_##reg)
 
+#ifdef SYSREGS_BASE
 #define V2M_SYS_CFGDATA		0xa0
 #define V2M_SYS_CFGCTRL		0xa4
 
 #define V2M_SYS(reg)	((void *)SYSREGS_BASE + V2M_SYS_##reg)
+#endif
 
 static void print_string(const char *str)
 {
@@ -59,6 +61,7 @@ void init_platform(void)
 
 	print_string("Boot-wrapper v0.2\r\n\r\n");
 
+#ifdef SYSREGS_BASE
 	/*
 	 * CLCD output site MB
 	 */
@@ -66,4 +69,5 @@ void init_platform(void)
 	/* START | WRITE | MUXFPGA | SITE_MB */
 	raw_writel((1 << 31) | (1 << 30) | (7 << 20) | (0 << 16),
 				V2M_SYS(CFGCTRL));
+#endif
 }
-- 
2.25.1


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Re: [boot-wrapper PATCH 1/5] Decouple V2M_SYS config by auto-detect dtb node

[Andre Przywara]

On Tue, 20 Apr 2021 15:24:34 +0800
Jaxson Han <jaxson.han@arm.com> wrote:

Hi,

> An auto-detect switch is added to make it an option to enable/disable
> 'arm,vexpress-sysreg', because not all platforms support this feature.

The change itself is fine, only has the side effect of now printing an
message about the missing node:
No matching devices found at ./findbase.pl line 37.

I will have a look if we can avoid this, or we drop this message in findbase.pl at all.

But for the sake of this patch:

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> Signed-off-by: Jaxson Han <jaxson.han@arm.com>
> ---
>  Makefile.am | 2 +-
>  platform.c  | 4 ++++
>  2 files changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/Makefile.am b/Makefile.am
> index af694b7..e131207 100644
> --- a/Makefile.am
> +++ b/Makefile.am
> @@ -19,7 +19,7 @@ NR_CPUS         := $(shell echo $(CPU_IDS) | tr ',' ' ' | wc -w)
>  DEFINES		= -DCNTFRQ=$(CNTFRQ)
>  DEFINES		+= -DCPU_IDS=$(CPU_IDS)
>  DEFINES		+= -DNR_CPUS=$(NR_CPUS)
> -DEFINES		+= -DSYSREGS_BASE=$(SYSREGS_BASE)
> +DEFINES		+= $(if $(SYSREGS_BASE), -DSYSREGS_BASE=$(SYSREGS_BASE), )
>  DEFINES		+= -DUART_BASE=$(UART_BASE)
>  DEFINES		+= -DSTACK_SIZE=256
>  
> diff --git a/platform.c b/platform.c
> index a528a55..d11f568 100644
> --- a/platform.c
> +++ b/platform.c
> @@ -23,10 +23,12 @@
>  
>  #define PL011(reg)	((void *)UART_BASE + PL011_##reg)
>  
> +#ifdef SYSREGS_BASE
>  #define V2M_SYS_CFGDATA		0xa0
>  #define V2M_SYS_CFGCTRL		0xa4
>  
>  #define V2M_SYS(reg)	((void *)SYSREGS_BASE + V2M_SYS_##reg)
> +#endif
>  
>  static void print_string(const char *str)
>  {
> @@ -59,6 +61,7 @@ void init_platform(void)
>  
>  	print_string("Boot-wrapper v0.2\r\n\r\n");
>  
> +#ifdef SYSREGS_BASE
>  	/*
>  	 * CLCD output site MB
>  	 */
> @@ -66,4 +69,5 @@ void init_platform(void)
>  	/* START | WRITE | MUXFPGA | SITE_MB */
>  	raw_writel((1 << 31) | (1 << 30) | (7 << 20) | (0 << 16),
>  				V2M_SYS(CFGCTRL));
> +#endif
>  }


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RE: [boot-wrapper PATCH 1/5] Decouple V2M_SYS config by auto-detect dtb node

[Jaxson Han]

Hi Andre,

> -----Original Message-----
> From: Andre Przywara <andre.przywara@arm.com>
> Sent: Monday, April 26, 2021 7:30 PM
> To: Jaxson Han <Jaxson.Han@arm.com>
> Cc: Mark Rutland <Mark.Rutland@arm.com>; linux-arm-
> kernel@lists.infradead.org; Wei Chen <Wei.Chen@arm.com>
> Subject: Re: [boot-wrapper PATCH 1/5] Decouple V2M_SYS config by auto-
> detect dtb node
> 
> On Tue, 20 Apr 2021 15:24:34 +0800
> Jaxson Han <jaxson.han@arm.com> wrote:
> 
> Hi,
> 
> > An auto-detect switch is added to make it an option to enable/disable
> > 'arm,vexpress-sysreg', because not all platforms support this feature.
> 
> The change itself is fine, only has the side effect of now printing an message
> about the missing node:
> No matching devices found at ./findbase.pl line 37.
> 
> I will have a look if we can avoid this, or we drop this message in findbase.pl
> at all.

Thanks, if you have any suggestions, please let me know:)

> 
> But for the sake of this patch:
> 
> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
> 
> Cheers,
> Andre

Thanks!
Jaxson

> 
> > Signed-off-by: Jaxson Han <jaxson.han@arm.com>
> > ---
> >  Makefile.am | 2 +-
> >  platform.c  | 4 ++++
> >  2 files changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/Makefile.am b/Makefile.am index af694b7..e131207 100644
> > --- a/Makefile.am
> > +++ b/Makefile.am
> > @@ -19,7 +19,7 @@ NR_CPUS         := $(shell echo $(CPU_IDS) | tr ',' ' ' | wc
> -w)
> >  DEFINES		= -DCNTFRQ=$(CNTFRQ)
> >  DEFINES		+= -DCPU_IDS=$(CPU_IDS)
> >  DEFINES		+= -DNR_CPUS=$(NR_CPUS)
> > -DEFINES		+= -DSYSREGS_BASE=$(SYSREGS_BASE)
> > +DEFINES		+= $(if $(SYSREGS_BASE), -
> DSYSREGS_BASE=$(SYSREGS_BASE), )
> >  DEFINES		+= -DUART_BASE=$(UART_BASE)
> >  DEFINES		+= -DSTACK_SIZE=256
> >
> > diff --git a/platform.c b/platform.c
> > index a528a55..d11f568 100644
> > --- a/platform.c
> > +++ b/platform.c
> > @@ -23,10 +23,12 @@
> >
> >  #define PL011(reg)	((void *)UART_BASE + PL011_##reg)
> >
> > +#ifdef SYSREGS_BASE
> >  #define V2M_SYS_CFGDATA		0xa0
> >  #define V2M_SYS_CFGCTRL		0xa4
> >
> >  #define V2M_SYS(reg)	((void *)SYSREGS_BASE + V2M_SYS_##reg)
> > +#endif
> >
> >  static void print_string(const char *str)  { @@ -59,6 +61,7 @@ void
> > init_platform(void)
> >
> >  	print_string("Boot-wrapper v0.2\r\n\r\n");
> >
> > +#ifdef SYSREGS_BASE
> >  	/*
> >  	 * CLCD output site MB
> >  	 */
> > @@ -66,4 +69,5 @@ void init_platform(void)
> >  	/* START | WRITE | MUXFPGA | SITE_MB */
> >  	raw_writel((1 << 31) | (1 << 30) | (7 << 20) | (0 << 16),
> >  				V2M_SYS(CFGCTRL));
> > +#endif
> >  }


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Re: [boot-wrapper PATCH 1/5] Decouple V2M_SYS config by auto-detect dtb node

[Andre Przywara]

On Wed, 28 Apr 2021 03:23:18 +0000
Jaxson Han <Jaxson.Han@arm.com> wrote:

Hi Jaxson,

> Hi Andre,
> 
> > -----Original Message-----
> > From: Andre Przywara <andre.przywara@arm.com>
> > Sent: Monday, April 26, 2021 7:30 PM
> > To: Jaxson Han <Jaxson.Han@arm.com>
> > Cc: Mark Rutland <Mark.Rutland@arm.com>; linux-arm-
> > kernel@lists.infradead.org; Wei Chen <Wei.Chen@arm.com>
> > Subject: Re: [boot-wrapper PATCH 1/5] Decouple V2M_SYS config by auto-
> > detect dtb node
> > 
> > On Tue, 20 Apr 2021 15:24:34 +0800
> > Jaxson Han <jaxson.han@arm.com> wrote:
> > 
> > Hi,
> >   
> > > An auto-detect switch is added to make it an option to enable/disable
> > > 'arm,vexpress-sysreg', because not all platforms support this feature.  
> > 
> > The change itself is fine, only has the side effect of now printing an message
> > about the missing node:
> > No matching devices found at ./findbase.pl line 37.
> > 
> > I will have a look if we can avoid this, or we drop this message in findbase.pl
> > at all.  
> 
> Thanks, if you have any suggestions, please let me know:)

As Mark suggested, you can just add " 2> /dev/null" at the end of the
findbase.pl call. That allows to do this warning suppression on a
case-by-case base, and is preferred over dropping this message in
general.

Cheers,
Andre

> 
> > 
> > But for the sake of this patch:
> > 
> > Reviewed-by: Andre Przywara <andre.przywara@arm.com>
> > 
> > Cheers,
> > Andre  
> 
> Thanks!
> Jaxson
> 
> >   
> > > Signed-off-by: Jaxson Han <jaxson.han@arm.com>
> > > ---
> > >  Makefile.am | 2 +-
> > >  platform.c  | 4 ++++
> > >  2 files changed, 5 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/Makefile.am b/Makefile.am index af694b7..e131207 100644
> > > --- a/Makefile.am
> > > +++ b/Makefile.am
> > > @@ -19,7 +19,7 @@ NR_CPUS         := $(shell echo $(CPU_IDS) | tr ',' ' ' | wc  
> > -w)  
> > >  DEFINES		= -DCNTFRQ=$(CNTFRQ)
> > >  DEFINES		+= -DCPU_IDS=$(CPU_IDS)
> > >  DEFINES		+= -DNR_CPUS=$(NR_CPUS)
> > > -DEFINES		+= -DSYSREGS_BASE=$(SYSREGS_BASE)
> > > +DEFINES		+= $(if $(SYSREGS_BASE), -  
> > DSYSREGS_BASE=$(SYSREGS_BASE), )  
> > >  DEFINES		+= -DUART_BASE=$(UART_BASE)
> > >  DEFINES		+= -DSTACK_SIZE=256
> > >
> > > diff --git a/platform.c b/platform.c
> > > index a528a55..d11f568 100644
> > > --- a/platform.c
> > > +++ b/platform.c
> > > @@ -23,10 +23,12 @@
> > >
> > >  #define PL011(reg)	((void *)UART_BASE + PL011_##reg)
> > >
> > > +#ifdef SYSREGS_BASE
> > >  #define V2M_SYS_CFGDATA		0xa0
> > >  #define V2M_SYS_CFGCTRL		0xa4
> > >
> > >  #define V2M_SYS(reg)	((void *)SYSREGS_BASE + V2M_SYS_##reg)
> > > +#endif
> > >
> > >  static void print_string(const char *str)  { @@ -59,6 +61,7 @@ void
> > > init_platform(void)
> > >
> > >  	print_string("Boot-wrapper v0.2\r\n\r\n");
> > >
> > > +#ifdef SYSREGS_BASE
> > >  	/*
> > >  	 * CLCD output site MB
> > >  	 */
> > > @@ -66,4 +69,5 @@ void init_platform(void)
> > >  	/* START | WRITE | MUXFPGA | SITE_MB */
> > >  	raw_writel((1 << 31) | (1 << 30) | (7 << 20) | (0 << 16),
> > >  				V2M_SYS(CFGCTRL));
> > > +#endif
> > >  }  
> 


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RE: [boot-wrapper PATCH 1/5] Decouple V2M_SYS config by auto-detect dtb node

[Jaxson Han]

Hi Andre,

> -----Original Message-----
> From: Andre Przywara <andre.przywara@arm.com>
> Sent: Monday, May 10, 2021 4:31 PM
> To: Jaxson Han <Jaxson.Han@arm.com>
> Cc: Mark Rutland <Mark.Rutland@arm.com>; linux-arm-
> kernel@lists.infradead.org; Wei Chen <Wei.Chen@arm.com>
> Subject: Re: [boot-wrapper PATCH 1/5] Decouple V2M_SYS config by auto-
> detect dtb node
> 
> On Wed, 28 Apr 2021 03:23:18 +0000
> Jaxson Han <Jaxson.Han@arm.com> wrote:
> 
> Hi Jaxson,
> 
> > Hi Andre,
> >
> > > -----Original Message-----
> > > From: Andre Przywara <andre.przywara@arm.com>
> > > Sent: Monday, April 26, 2021 7:30 PM
> > > To: Jaxson Han <Jaxson.Han@arm.com>
> > > Cc: Mark Rutland <Mark.Rutland@arm.com>; linux-arm-
> > > kernel@lists.infradead.org; Wei Chen <Wei.Chen@arm.com>
> > > Subject: Re: [boot-wrapper PATCH 1/5] Decouple V2M_SYS config by
> > > auto- detect dtb node
> > >
> > > On Tue, 20 Apr 2021 15:24:34 +0800
> > > Jaxson Han <jaxson.han@arm.com> wrote:
> > >
> > > Hi,
> > >
> > > > An auto-detect switch is added to make it an option to
> > > > enable/disable 'arm,vexpress-sysreg', because not all platforms support
> this feature.
> > >
> > > The change itself is fine, only has the side effect of now printing
> > > an message about the missing node:
> > > No matching devices found at ./findbase.pl line 37.
> > >
> > > I will have a look if we can avoid this, or we drop this message in
> > > findbase.pl at all.
> >
> > Thanks, if you have any suggestions, please let me know:)
> 
> As Mark suggested, you can just add " 2> /dev/null" at the end of the
> findbase.pl call. That allows to do this warning suppression on a case-by-case
> base, and is preferred over dropping this message in general.

Got it, thanks for the information :)

Cheers,
Jaxson

> 
> Cheers,
> Andre
> 
> >
> > >
> > > But for the sake of this patch:
> > >
> > > Reviewed-by: Andre Przywara <andre.przywara@arm.com>
> > >
> > > Cheers,
> > > Andre
> >
> > Thanks!
> > Jaxson
> >
> > >
> > > > Signed-off-by: Jaxson Han <jaxson.han@arm.com>
> > > > ---
> > > >  Makefile.am | 2 +-
> > > >  platform.c  | 4 ++++
> > > >  2 files changed, 5 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/Makefile.am b/Makefile.am index af694b7..e131207
> > > > 100644
> > > > --- a/Makefile.am
> > > > +++ b/Makefile.am
> > > > @@ -19,7 +19,7 @@ NR_CPUS         := $(shell echo $(CPU_IDS) | tr ',' ' ' |
> wc
> > > -w)
> > > >  DEFINES		= -DCNTFRQ=$(CNTFRQ)
> > > >  DEFINES		+= -DCPU_IDS=$(CPU_IDS)
> > > >  DEFINES		+= -DNR_CPUS=$(NR_CPUS)
> > > > -DEFINES		+= -DSYSREGS_BASE=$(SYSREGS_BASE)
> > > > +DEFINES		+= $(if $(SYSREGS_BASE), -
> > > DSYSREGS_BASE=$(SYSREGS_BASE), )
> > > >  DEFINES		+= -DUART_BASE=$(UART_BASE)
> > > >  DEFINES		+= -DSTACK_SIZE=256
> > > >
> > > > diff --git a/platform.c b/platform.c index a528a55..d11f568 100644
> > > > --- a/platform.c
> > > > +++ b/platform.c
> > > > @@ -23,10 +23,12 @@
> > > >
> > > >  #define PL011(reg)	((void *)UART_BASE + PL011_##reg)
> > > >
> > > > +#ifdef SYSREGS_BASE
> > > >  #define V2M_SYS_CFGDATA		0xa0
> > > >  #define V2M_SYS_CFGCTRL		0xa4
> > > >
> > > >  #define V2M_SYS(reg)	((void *)SYSREGS_BASE + V2M_SYS_##reg)
> > > > +#endif
> > > >
> > > >  static void print_string(const char *str)  { @@ -59,6 +61,7 @@
> > > > void
> > > > init_platform(void)
> > > >
> > > >  	print_string("Boot-wrapper v0.2\r\n\r\n");
> > > >
> > > > +#ifdef SYSREGS_BASE
> > > >  	/*
> > > >  	 * CLCD output site MB
> > > >  	 */
> > > > @@ -66,4 +69,5 @@ void init_platform(void)
> > > >  	/* START | WRITE | MUXFPGA | SITE_MB */
> > > >  	raw_writel((1 << 31) | (1 << 30) | (7 << 20) | (0 << 16),
> > > >  				V2M_SYS(CFGCTRL));
> > > > +#endif
> > > >  }
> >


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[boot-wrapper PATCH 2/5] aarch64: Rename labels and prepare for lower EL booting

[Jaxson Han]

Prepare for booting from lower EL. Rename *_el3 relavant labels with
*_el_max and *_no_el3 with *_keep_el. Since the original _no_el3 means
"We neither do init sequence at this highest EL nor drop to lower EL
when entering to kernel", we rename it with _keep_el to make it more
clear for lower EL initialisation.
Also in jump_kernel, skip sctlr_el2 initialisation when CurrentEL < EL2.

Signed-off-by: Jaxson Han <jaxson.han@arm.com>
---
 arch/aarch64/boot.S            | 54 +++++++++++++++++++++++++---------
 arch/aarch64/include/asm/cpu.h |  3 ++
 arch/aarch64/psci.S            | 13 ++++----
 arch/aarch64/spin.S            |  8 ++---
 4 files changed, 54 insertions(+), 24 deletions(-)

diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
index e47cf59..f7dbf3f 100644
--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
@@ -12,7 +12,7 @@
 	.section .init
 
 	.globl	_start
-	.globl jump_kernel
+	.globl	jump_kernel
 
 _start:
 	cpuid	x0, x1
@@ -22,20 +22,30 @@ _start:
 	bl	setup_stack
 
 	/*
-	 * EL3 initialisation
+	 * Boot sequence
+	 * If CurrentEL == EL3, then goto EL3 initialisation and drop to
+	 *   lower EL before entering the kernel.
+	 * Else, no initialisation and keep the current EL before
+	 *   entering the kernel.
 	 */
 	mrs	x0, CurrentEL
 	cmp	x0, #CURRENTEL_EL3
-	b.eq	1f
+	beq	el3_init
 
+	/*
+	 * We stay in the current EL for entering the kernel
+	 */
 	mov	w0, #1
-	ldr	x1, =flag_no_el3
+	ldr	x1, =flag_keep_el
 	str	w0, [x1]
 
-	bl	setup_stack
-	b	start_no_el3
+	b	start_keep_el
 
-1:	mov	x0, #0x30			// RES1
+	/*
+	 * EL3 initialisation
+	 */
+el3_init:
+	mov	x0, #0x30			// RES1
 	orr	x0, x0, #(1 << 0)		// Non-secure EL1
 	orr	x0, x0, #(1 << 8)		// HVC enable
 
@@ -93,13 +103,23 @@ _start:
 	mov	x0, #ZCR_EL3_LEN_MASK		// SVE: Enable full vector len
 	msr	ZCR_EL3, x0			// for EL2.
 
-1:
+	/*
+	 * Save SPSR_KERNEL into spsr_to_elx.
+	 * The jump_kernel will load spsr_to_elx into spsr_el3
+	 */
+1:	mov	w0, #SPSR_KERNEL
+	ldr	x1, =spsr_to_elx
+	str	w0, [x1]
+	b	el_max_init
+
+el_max_init:
 	ldr	x0, =CNTFRQ
 	msr	cntfrq_el0, x0
+	isb
 
 	bl	gic_secure_init
 
-	b	start_el3
+	b	start_el_max
 
 err_invalid_id:
 	b	.
@@ -119,14 +139,18 @@ jump_kernel:
 	ldr	x0, =SCTLR_EL1_RESET
 	msr	sctlr_el1, x0
 
+	mrs	x0, CurrentEL
+	cmp	x0, #CURRENTEL_EL2
+	b.lt	1f
+
 	ldr	x0, =SCTLR_EL2_RESET
 	msr	sctlr_el2, x0
 
-	cpuid	x0, x1
+1:	cpuid	x0, x1
 	bl	find_logical_id
 	bl	setup_stack		// Reset stack pointer
 
-	ldr	w0, flag_no_el3
+	ldr	w0, flag_keep_el
 	cmp	w0, #0			// Prepare Z flag
 
 	mov	x0, x20
@@ -135,9 +159,9 @@ jump_kernel:
 	mov	x3, x23
 
 	b.eq	1f
-	br	x19			// No EL3
+	br	x19			// Keep current EL
 
-1:	mov	x4, #SPSR_KERNEL
+1:	ldr	w4, spsr_to_elx
 
 	/*
 	 * If bit 0 of the kernel address is set, we're entering in AArch32
@@ -153,5 +177,7 @@ jump_kernel:
 
 	.data
 	.align 3
-flag_no_el3:
+flag_keep_el:
+	.long 0
+spsr_to_elx:
 	.long 0
diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index ccb5397..2b3a0a4 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -11,6 +11,7 @@
 
 #define MPIDR_ID_BITS		0xff00ffffff
 
+#define CURRENTEL_EL2		(2 << 2)
 #define CURRENTEL_EL3		(3 << 2)
 
 /*
@@ -24,6 +25,7 @@
 #define SPSR_I			(1 << 7)	/* IRQ masked */
 #define SPSR_F			(1 << 6)	/* FIQ masked */
 #define SPSR_T			(1 << 5)	/* Thumb */
+#define SPSR_EL1H		(5 << 0)	/* EL1 Handler mode */
 #define SPSR_EL2H		(9 << 0)	/* EL2 Handler mode */
 #define SPSR_HYP		(0x1a << 0)	/* M[3:0] = hyp, M[4] = AArch32 */
 
@@ -42,6 +44,7 @@
 #else
 #define SCTLR_EL1_RESET		SCTLR_EL1_RES1
 #define SPSR_KERNEL		(SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL2H)
+#define SPSR_KERNEL_EL1		(SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL1H)
 #endif
 
 #ifndef __ASSEMBLY__
diff --git a/arch/aarch64/psci.S b/arch/aarch64/psci.S
index 01ebe7d..ae02fd6 100644
--- a/arch/aarch64/psci.S
+++ b/arch/aarch64/psci.S
@@ -45,8 +45,8 @@ vector:
 
 	.text
 
-	.globl start_no_el3
-	.globl start_el3
+	.globl start_keep_el
+	.globl start_el_max
 
 err_exception:
 	b err_exception
@@ -101,7 +101,7 @@ smc_exit:
 	eret
 
 
-start_el3:
+start_el_max:
 	ldr	x0, =vector
 	bl	setup_vector
 
@@ -111,10 +111,11 @@ start_el3:
 	b	psci_first_spin
 
 /*
- * This PSCI implementation requires EL3. Without EL3 we'll only boot the
- * primary cpu, all others will be trapped in an infinite loop.
+ * This PSCI implementation requires the highest EL(EL3 or Armv8-R EL2).
+ * Without the highest EL, we'll only boot the primary cpu, all others
+ * will be trapped in an infinite loop.
  */
-start_no_el3:
+start_keep_el:
 	cpuid	x0, x1
 	bl	find_logical_id
 	cbz	x0, psci_first_spin
diff --git a/arch/aarch64/spin.S b/arch/aarch64/spin.S
index 72603cf..533177c 100644
--- a/arch/aarch64/spin.S
+++ b/arch/aarch64/spin.S
@@ -11,11 +11,11 @@
 
 	.text
 
-	.globl start_no_el3
-	.globl start_el3
+	.globl start_keep_el
+	.globl start_el_max
 
-start_el3:
-start_no_el3:
+start_el_max:
+start_keep_el:
 	cpuid	x0, x1
 	bl	find_logical_id
 
-- 
2.25.1


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Re: [boot-wrapper PATCH 2/5] aarch64: Rename labels and prepare for lower EL booting

[Andre Przywara]

On Tue, 20 Apr 2021 15:24:35 +0800
Jaxson Han <jaxson.han@arm.com> wrote:

> Prepare for booting from lower EL. Rename *_el3 relavant labels with
> *_el_max and *_no_el3 with *_keep_el. Since the original _no_el3 means
> "We neither do init sequence at this highest EL nor drop to lower EL
> when entering to kernel", we rename it with _keep_el to make it more
> clear for lower EL initialisation.

So this cleanup and rename is fine, however the patch is hard to read
since various other changes are mixed in.
Can you try to isolate this more? If this patch would just rename the
labels, and wouldn't carry any functional change, it might be easier to
reason about. At least the SPSR value change should be separate.

Some more below:

> Also in jump_kernel, skip sctlr_el2 initialisation when CurrentEL < EL2.
> 
> Signed-off-by: Jaxson Han <jaxson.han@arm.com>
> ---
>  arch/aarch64/boot.S            | 54 +++++++++++++++++++++++++---------
>  arch/aarch64/include/asm/cpu.h |  3 ++
>  arch/aarch64/psci.S            | 13 ++++----
>  arch/aarch64/spin.S            |  8 ++---
>  4 files changed, 54 insertions(+), 24 deletions(-)
> 
> diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
> index e47cf59..f7dbf3f 100644
> --- a/arch/aarch64/boot.S
> +++ b/arch/aarch64/boot.S
> @@ -12,7 +12,7 @@
>  	.section .init
>  
>  	.globl	_start
> -	.globl jump_kernel
> +	.globl	jump_kernel
>  
>  _start:
>  	cpuid	x0, x1
> @@ -22,20 +22,30 @@ _start:
>  	bl	setup_stack
>  
>  	/*
> -	 * EL3 initialisation
> +	 * Boot sequence
> +	 * If CurrentEL == EL3, then goto EL3 initialisation and drop to
> +	 *   lower EL before entering the kernel.
> +	 * Else, no initialisation and keep the current EL before
> +	 *   entering the kernel.
>  	 */
>  	mrs	x0, CurrentEL
>  	cmp	x0, #CURRENTEL_EL3
> -	b.eq	1f
> +	beq	el3_init
>  
> +	/*
> +	 * We stay in the current EL for entering the kernel
> +	 */
>  	mov	w0, #1
> -	ldr	x1, =flag_no_el3
> +	ldr	x1, =flag_keep_el
>  	str	w0, [x1]
>  
> -	bl	setup_stack

I think this is indeed redundant, but can you either make this a
separate patch or at least mention it in the commit message?

> -	b	start_no_el3
> +	b	start_keep_el
>  
> -1:	mov	x0, #0x30			// RES1
> +	/*
> +	 * EL3 initialisation
> +	 */
> +el3_init:
> +	mov	x0, #0x30			// RES1
>  	orr	x0, x0, #(1 << 0)		// Non-secure EL1
>  	orr	x0, x0, #(1 << 8)		// HVC enable
>  
> @@ -93,13 +103,23 @@ _start:
>  	mov	x0, #ZCR_EL3_LEN_MASK		// SVE: Enable full vector len
>  	msr	ZCR_EL3, x0			// for EL2.
>  
> -1:
> +	/*
> +	 * Save SPSR_KERNEL into spsr_to_elx.
> +	 * The jump_kernel will load spsr_to_elx into spsr_el3
> +	 */
> +1:	mov	w0, #SPSR_KERNEL
> +	ldr	x1, =spsr_to_elx
> +	str	w0, [x1]
> +	b	el_max_init

This (and the other SPSR related changes below) should be in a separate
patch.

> +
> +el_max_init:
>  	ldr	x0, =CNTFRQ
>  	msr	cntfrq_el0, x0
> +	isb

Why this isb here? I don't see that we would require this?

>  	bl	gic_secure_init
>  
> -	b	start_el3
> +	b	start_el_max
>  
>  err_invalid_id:
>  	b	.
> @@ -119,14 +139,18 @@ jump_kernel:
>  	ldr	x0, =SCTLR_EL1_RESET
>  	msr	sctlr_el1, x0
>  
> +	mrs	x0, CurrentEL
> +	cmp	x0, #CURRENTEL_EL2
> +	b.lt	1f
> +

This is also a change which might be separate.

Cheers,
Andre


>  	ldr	x0, =SCTLR_EL2_RESET
>  	msr	sctlr_el2, x0
>  
> -	cpuid	x0, x1
> +1:	cpuid	x0, x1
>  	bl	find_logical_id
>  	bl	setup_stack		// Reset stack pointer
>  
> -	ldr	w0, flag_no_el3
> +	ldr	w0, flag_keep_el
>  	cmp	w0, #0			// Prepare Z flag
>  
>  	mov	x0, x20
> @@ -135,9 +159,9 @@ jump_kernel:
>  	mov	x3, x23
>  
>  	b.eq	1f
> -	br	x19			// No EL3
> +	br	x19			// Keep current EL
>  
> -1:	mov	x4, #SPSR_KERNEL
> +1:	ldr	w4, spsr_to_elx
>  
>  	/*
>  	 * If bit 0 of the kernel address is set, we're entering in AArch32
> @@ -153,5 +177,7 @@ jump_kernel:
>  
>  	.data
>  	.align 3
> -flag_no_el3:
> +flag_keep_el:
> +	.long 0
> +spsr_to_elx:
>  	.long 0
> diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
> index ccb5397..2b3a0a4 100644
> --- a/arch/aarch64/include/asm/cpu.h
> +++ b/arch/aarch64/include/asm/cpu.h
> @@ -11,6 +11,7 @@
>  
>  #define MPIDR_ID_BITS		0xff00ffffff
>  
> +#define CURRENTEL_EL2		(2 << 2)
>  #define CURRENTEL_EL3		(3 << 2)
>  
>  /*
> @@ -24,6 +25,7 @@
>  #define SPSR_I			(1 << 7)	/* IRQ masked */
>  #define SPSR_F			(1 << 6)	/* FIQ masked */
>  #define SPSR_T			(1 << 5)	/* Thumb */
> +#define SPSR_EL1H		(5 << 0)	/* EL1 Handler mode */
>  #define SPSR_EL2H		(9 << 0)	/* EL2 Handler mode */
>  #define SPSR_HYP		(0x1a << 0)	/* M[3:0] = hyp, M[4] = AArch32 */
>  
> @@ -42,6 +44,7 @@
>  #else
>  #define SCTLR_EL1_RESET		SCTLR_EL1_RES1
>  #define SPSR_KERNEL		(SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL2H)
> +#define SPSR_KERNEL_EL1		(SPSR_A | SPSR_D | SPSR_I | SPSR_F | SPSR_EL1H)
>  #endif
>  
>  #ifndef __ASSEMBLY__
> diff --git a/arch/aarch64/psci.S b/arch/aarch64/psci.S
> index 01ebe7d..ae02fd6 100644
> --- a/arch/aarch64/psci.S
> +++ b/arch/aarch64/psci.S
> @@ -45,8 +45,8 @@ vector:
>  
>  	.text
>  
> -	.globl start_no_el3
> -	.globl start_el3
> +	.globl start_keep_el
> +	.globl start_el_max
>  
>  err_exception:
>  	b err_exception
> @@ -101,7 +101,7 @@ smc_exit:
>  	eret
>  
>  
> -start_el3:
> +start_el_max:
>  	ldr	x0, =vector
>  	bl	setup_vector
>  
> @@ -111,10 +111,11 @@ start_el3:
>  	b	psci_first_spin
>  
>  /*
> - * This PSCI implementation requires EL3. Without EL3 we'll only boot the
> - * primary cpu, all others will be trapped in an infinite loop.
> + * This PSCI implementation requires the highest EL(EL3 or Armv8-R EL2).
> + * Without the highest EL, we'll only boot the primary cpu, all others
> + * will be trapped in an infinite loop.
>   */
> -start_no_el3:
> +start_keep_el:
>  	cpuid	x0, x1
>  	bl	find_logical_id
>  	cbz	x0, psci_first_spin
> diff --git a/arch/aarch64/spin.S b/arch/aarch64/spin.S
> index 72603cf..533177c 100644
> --- a/arch/aarch64/spin.S
> +++ b/arch/aarch64/spin.S
> @@ -11,11 +11,11 @@
>  
>  	.text
>  
> -	.globl start_no_el3
> -	.globl start_el3
> +	.globl start_keep_el
> +	.globl start_el_max
>  
> -start_el3:
> -start_no_el3:
> +start_el_max:
> +start_keep_el:
>  	cpuid	x0, x1
>  	bl	find_logical_id
>  


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RE: [boot-wrapper PATCH 2/5] aarch64: Rename labels and prepare for lower EL booting

[Jaxson Han]

Hi Andre,

> -----Original Message-----
> From: Andre Przywara <andre.przywara@arm.com>
> Sent: Monday, April 26, 2021 7:41 PM
> To: Jaxson Han <Jaxson.Han@arm.com>
> Cc: Mark Rutland <Mark.Rutland@arm.com>; linux-arm-
> kernel@lists.infradead.org; Wei Chen <Wei.Chen@arm.com>
> Subject: Re: [boot-wrapper PATCH 2/5] aarch64: Rename labels and prepare
> for lower EL booting
> 
> On Tue, 20 Apr 2021 15:24:35 +0800
> Jaxson Han <jaxson.han@arm.com> wrote:
> 
> > Prepare for booting from lower EL. Rename *_el3 relavant labels with
> > *_el_max and *_no_el3 with *_keep_el. Since the original _no_el3 means
> > "We neither do init sequence at this highest EL nor drop to lower EL
> > when entering to kernel", we rename it with _keep_el to make it more
> > clear for lower EL initialisation.
> 
> So this cleanup and rename is fine, however the patch is hard to read since
> various other changes are mixed in.
> Can you try to isolate this more? If this patch would just rename the labels,
> and wouldn't carry any functional change, it might be easier to reason about.
> At least the SPSR value change should be separate.

Yes, I will.

> 
> Some more below:
> 
> > Also in jump_kernel, skip sctlr_el2 initialisation when CurrentEL < EL2.
> >
> > Signed-off-by: Jaxson Han <jaxson.han@arm.com>
> > ---
> >  arch/aarch64/boot.S            | 54 +++++++++++++++++++++++++---------
> >  arch/aarch64/include/asm/cpu.h |  3 ++
> >  arch/aarch64/psci.S            | 13 ++++----
> >  arch/aarch64/spin.S            |  8 ++---
> >  4 files changed, 54 insertions(+), 24 deletions(-)
> >
> > diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index
> > e47cf59..f7dbf3f 100644
> > --- a/arch/aarch64/boot.S
> > +++ b/arch/aarch64/boot.S
> > @@ -12,7 +12,7 @@
> >  	.section .init
> >
> >  	.globl	_start
> > -	.globl jump_kernel
> > +	.globl	jump_kernel
> >
> >  _start:
> >  	cpuid	x0, x1
> > @@ -22,20 +22,30 @@ _start:
> >  	bl	setup_stack
> >
> >  	/*
> > -	 * EL3 initialisation
> > +	 * Boot sequence
> > +	 * If CurrentEL == EL3, then goto EL3 initialisation and drop to
> > +	 *   lower EL before entering the kernel.
> > +	 * Else, no initialisation and keep the current EL before
> > +	 *   entering the kernel.
> >  	 */
> >  	mrs	x0, CurrentEL
> >  	cmp	x0, #CURRENTEL_EL3
> > -	b.eq	1f
> > +	beq	el3_init
> >
> > +	/*
> > +	 * We stay in the current EL for entering the kernel
> > +	 */
> >  	mov	w0, #1
> > -	ldr	x1, =flag_no_el3
> > +	ldr	x1, =flag_keep_el
> >  	str	w0, [x1]
> >
> > -	bl	setup_stack
> 
> I think this is indeed redundant, but can you either make this a separate
> patch or at least mention it in the commit message?

Yes, I will make this separate.

> 
> > -	b	start_no_el3
> > +	b	start_keep_el
> >
> > -1:	mov	x0, #0x30			// RES1
> > +	/*
> > +	 * EL3 initialisation
> > +	 */
> > +el3_init:
> > +	mov	x0, #0x30			// RES1
> >  	orr	x0, x0, #(1 << 0)		// Non-secure EL1
> >  	orr	x0, x0, #(1 << 8)		// HVC enable
> >
> > @@ -93,13 +103,23 @@ _start:
> >  	mov	x0, #ZCR_EL3_LEN_MASK		// SVE: Enable full
> vector len
> >  	msr	ZCR_EL3, x0			// for EL2.
> >
> > -1:
> > +	/*
> > +	 * Save SPSR_KERNEL into spsr_to_elx.
> > +	 * The jump_kernel will load spsr_to_elx into spsr_el3
> > +	 */
> > +1:	mov	w0, #SPSR_KERNEL
> > +	ldr	x1, =spsr_to_elx
> > +	str	w0, [x1]
> > +	b	el_max_init
> 
> This (and the other SPSR related changes below) should be in a separate
> patch.

Yes, I will

> 
> > +
> > +el_max_init:
> >  	ldr	x0, =CNTFRQ
> >  	msr	cntfrq_el0, x0
> > +	isb
> 
> Why this isb here? I don't see that we would require this?

No need here. I'll remove it.

> 
> >  	bl	gic_secure_init
> >
> > -	b	start_el3
> > +	b	start_el_max
> >
> >  err_invalid_id:
> >  	b	.
> > @@ -119,14 +139,18 @@ jump_kernel:
> >  	ldr	x0, =SCTLR_EL1_RESET
> >  	msr	sctlr_el1, x0
> >
> > +	mrs	x0, CurrentEL
> > +	cmp	x0, #CURRENTEL_EL2
> > +	b.lt	1f
> > +
> 
> This is also a change which might be separate.

Yes

Thanks,
Jaxson

> 
> Cheers,
> Andre
> 
> 
> >  	ldr	x0, =SCTLR_EL2_RESET
> >  	msr	sctlr_el2, x0
> >
> > -	cpuid	x0, x1
> > +1:	cpuid	x0, x1
> >  	bl	find_logical_id
> >  	bl	setup_stack		// Reset stack pointer
> >
> > -	ldr	w0, flag_no_el3
> > +	ldr	w0, flag_keep_el
> >  	cmp	w0, #0			// Prepare Z flag
> >
> >  	mov	x0, x20
> > @@ -135,9 +159,9 @@ jump_kernel:
> >  	mov	x3, x23
> >
> >  	b.eq	1f
> > -	br	x19			// No EL3
> > +	br	x19			// Keep current EL
> >
> > -1:	mov	x4, #SPSR_KERNEL
> > +1:	ldr	w4, spsr_to_elx
> >
> >  	/*
> >  	 * If bit 0 of the kernel address is set, we're entering in AArch32
> > @@ -153,5 +177,7 @@ jump_kernel:
> >
> >  	.data
> >  	.align 3
> > -flag_no_el3:
> > +flag_keep_el:
> > +	.long 0
> > +spsr_to_elx:
> >  	.long 0
> > diff --git a/arch/aarch64/include/asm/cpu.h
> > b/arch/aarch64/include/asm/cpu.h index ccb5397..2b3a0a4 100644
> > --- a/arch/aarch64/include/asm/cpu.h
> > +++ b/arch/aarch64/include/asm/cpu.h
> > @@ -11,6 +11,7 @@
> >
> >  #define MPIDR_ID_BITS		0xff00ffffff
> >
> > +#define CURRENTEL_EL2		(2 << 2)
> >  #define CURRENTEL_EL3		(3 << 2)
> >
> >  /*
> > @@ -24,6 +25,7 @@
> >  #define SPSR_I			(1 << 7)	/* IRQ masked */
> >  #define SPSR_F			(1 << 6)	/* FIQ masked */
> >  #define SPSR_T			(1 << 5)	/* Thumb */
> > +#define SPSR_EL1H		(5 << 0)	/* EL1 Handler mode */
> >  #define SPSR_EL2H		(9 << 0)	/* EL2 Handler mode */
> >  #define SPSR_HYP		(0x1a << 0)	/* M[3:0] = hyp, M[4] =
> AArch32 */
> >
> > @@ -42,6 +44,7 @@
> >  #else
> >  #define SCTLR_EL1_RESET		SCTLR_EL1_RES1
> >  #define SPSR_KERNEL		(SPSR_A | SPSR_D | SPSR_I | SPSR_F |
> SPSR_EL2H)
> > +#define SPSR_KERNEL_EL1		(SPSR_A | SPSR_D | SPSR_I | SPSR_F |
> SPSR_EL1H)
> >  #endif
> >
> >  #ifndef __ASSEMBLY__
> > diff --git a/arch/aarch64/psci.S b/arch/aarch64/psci.S index
> > 01ebe7d..ae02fd6 100644
> > --- a/arch/aarch64/psci.S
> > +++ b/arch/aarch64/psci.S
> > @@ -45,8 +45,8 @@ vector:
> >
> >  	.text
> >
> > -	.globl start_no_el3
> > -	.globl start_el3
> > +	.globl start_keep_el
> > +	.globl start_el_max
> >
> >  err_exception:
> >  	b err_exception
> > @@ -101,7 +101,7 @@ smc_exit:
> >  	eret
> >
> >
> > -start_el3:
> > +start_el_max:
> >  	ldr	x0, =vector
> >  	bl	setup_vector
> >
> > @@ -111,10 +111,11 @@ start_el3:
> >  	b	psci_first_spin
> >
> >  /*
> > - * This PSCI implementation requires EL3. Without EL3 we'll only boot
> > the
> > - * primary cpu, all others will be trapped in an infinite loop.
> > + * This PSCI implementation requires the highest EL(EL3 or Armv8-R EL2).
> > + * Without the highest EL, we'll only boot the primary cpu, all
> > + others
> > + * will be trapped in an infinite loop.
> >   */
> > -start_no_el3:
> > +start_keep_el:
> >  	cpuid	x0, x1
> >  	bl	find_logical_id
> >  	cbz	x0, psci_first_spin
> > diff --git a/arch/aarch64/spin.S b/arch/aarch64/spin.S index
> > 72603cf..533177c 100644
> > --- a/arch/aarch64/spin.S
> > +++ b/arch/aarch64/spin.S
> > @@ -11,11 +11,11 @@
> >
> >  	.text
> >
> > -	.globl start_no_el3
> > -	.globl start_el3
> > +	.globl start_keep_el
> > +	.globl start_el_max
> >
> > -start_el3:
> > -start_no_el3:
> > +start_el_max:
> > +start_keep_el:
> >  	cpuid	x0, x1
> >  	bl	find_logical_id
> >


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[boot-wrapper PATCH 3/5] gic-v3: Prepare for gicv3 with EL2

[Jaxson Han]

This is a preparation for allowing boot-wrapper configuring the gicv3
with EL2.

Signed-off-by: Jaxson Han <jaxson.han@arm.com>
---
 arch/aarch32/include/asm/gic-v3.h |  7 ++++++
 arch/aarch64/include/asm/gic-v3.h | 38 ++++++++++++++++++++++++++++---
 gic-v3.c                          |  2 +-
 3 files changed, 43 insertions(+), 4 deletions(-)

diff --git a/arch/aarch32/include/asm/gic-v3.h b/arch/aarch32/include/asm/gic-v3.h
index ec9a327..86abe09 100644
--- a/arch/aarch32/include/asm/gic-v3.h
+++ b/arch/aarch32/include/asm/gic-v3.h
@@ -9,6 +9,8 @@
 #ifndef __ASM_AARCH32_GICV3_H
 #define __ASM_AARCH32_GICV3_H
 
+#define ICC_CTLR_RESET	(0UL)
+
 static inline uint32_t gic_read_icc_sre(void)
 {
 	uint32_t val;
@@ -26,4 +28,9 @@ static inline void gic_write_icc_ctlr(uint32_t val)
 	asm volatile ("mcr p15, 6, %0, c12, c12, 4" : : "r" (val));
 }
 
+static inline void gic_init_icc_ctlr()
+{
+	gic_write_icc_ctlr(ICC_CTLR_RESET);
+}
+
 #endif
diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic-v3.h
index e743c02..b3dfbd3 100644
--- a/arch/aarch64/include/asm/gic-v3.h
+++ b/arch/aarch64/include/asm/gic-v3.h
@@ -15,21 +15,53 @@
 #define ICC_CTLR_EL3	"S3_6_C12_C12_4"
 #define ICC_PMR_EL1	"S3_0_C4_C6_0"
 
+#define ICC_CTLR_EL3_RESET	(0UL)
+#define ICC_CTLR_EL1_RESET	(0UL)
+
+static inline uint32_t current_el(void)
+{
+	uint32_t val;
+
+	asm volatile ("mrs %0, CurrentEL" : "=r" (val));
+	return val;
+}
+
 static inline uint32_t gic_read_icc_sre(void)
 {
 	uint32_t val;
-	asm volatile ("mrs %0, " ICC_SRE_EL3 : "=r" (val));
+
+	if(current_el() == CURRENTEL_EL3)
+		asm volatile ("mrs %0, " ICC_SRE_EL3 : "=r" (val));
+	else
+		asm volatile ("mrs %0, " ICC_SRE_EL2 : "=r" (val));
+
 	return val;
 }
 
 static inline void gic_write_icc_sre(uint32_t val)
 {
-	asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val));
+	if(current_el() == CURRENTEL_EL3)
+		asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val));
+	else
+		asm volatile ("msr " ICC_SRE_EL2 ", %0" : : "r" (val));
 }
 
-static inline void gic_write_icc_ctlr(uint32_t val)
+static inline void gic_write_icc_ctlr_el3(uint32_t val)
 {
 	asm volatile ("msr " ICC_CTLR_EL3 ", %0" : : "r" (val));
 }
 
+static inline void gic_write_icc_ctlr_el1(uint32_t val)
+{
+	asm volatile ("msr " ICC_CTLR_EL1 ", %0" : : "r" (val));
+}
+
+static inline void gic_init_icc_ctlr()
+{
+	if(current_el() == CURRENTEL_EL3)
+		gic_write_icc_ctlr_el3(ICC_CTLR_EL3_RESET);
+	else
+		gic_write_icc_ctlr_el1(ICC_CTLR_EL1_RESET);
+}
+
 #endif
diff --git a/gic-v3.c b/gic-v3.c
index ae2d2bc..4850572 100644
--- a/gic-v3.c
+++ b/gic-v3.c
@@ -121,6 +121,6 @@ void gic_secure_init(void)
 	gic_write_icc_sre(sre);
 	isb();
 
-	gic_write_icc_ctlr(0);
+	gic_init_icc_ctlr();
 	isb();
 }
-- 
2.25.1


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Re: [boot-wrapper PATCH 3/5] gic-v3: Prepare for gicv3 with EL2

[Andre Przywara]

On Tue, 20 Apr 2021 15:24:36 +0800
Jaxson Han <jaxson.han@arm.com> wrote:

> This is a preparation for allowing boot-wrapper configuring the gicv3
> with EL2.

The GIC is always confusing, so can you please give some more
background here? The introduction of ICC_SRE_EL2 looks straight-forward
enough, but the change to the ICC_CTLR_RESET register deserves some
comments, I guess.

Cheers,
Andre

> Signed-off-by: Jaxson Han <jaxson.han@arm.com>
> ---
>  arch/aarch32/include/asm/gic-v3.h |  7 ++++++
>  arch/aarch64/include/asm/gic-v3.h | 38 ++++++++++++++++++++++++++++---
>  gic-v3.c                          |  2 +-
>  3 files changed, 43 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/aarch32/include/asm/gic-v3.h b/arch/aarch32/include/asm/gic-v3.h
> index ec9a327..86abe09 100644
> --- a/arch/aarch32/include/asm/gic-v3.h
> +++ b/arch/aarch32/include/asm/gic-v3.h
> @@ -9,6 +9,8 @@
>  #ifndef __ASM_AARCH32_GICV3_H
>  #define __ASM_AARCH32_GICV3_H
>  
> +#define ICC_CTLR_RESET	(0UL)
> +
>  static inline uint32_t gic_read_icc_sre(void)
>  {
>  	uint32_t val;
> @@ -26,4 +28,9 @@ static inline void gic_write_icc_ctlr(uint32_t val)
>  	asm volatile ("mcr p15, 6, %0, c12, c12, 4" : : "r" (val));
>  }
>  
> +static inline void gic_init_icc_ctlr()
> +{
> +	gic_write_icc_ctlr(ICC_CTLR_RESET);
> +}
> +
>  #endif
> diff --git a/arch/aarch64/include/asm/gic-v3.h b/arch/aarch64/include/asm/gic-v3.h
> index e743c02..b3dfbd3 100644
> --- a/arch/aarch64/include/asm/gic-v3.h
> +++ b/arch/aarch64/include/asm/gic-v3.h
> @@ -15,21 +15,53 @@
>  #define ICC_CTLR_EL3	"S3_6_C12_C12_4"
>  #define ICC_PMR_EL1	"S3_0_C4_C6_0"
>  
> +#define ICC_CTLR_EL3_RESET	(0UL)
> +#define ICC_CTLR_EL1_RESET	(0UL)
> +
> +static inline uint32_t current_el(void)
> +{
> +	uint32_t val;
> +
> +	asm volatile ("mrs %0, CurrentEL" : "=r" (val));
> +	return val;
> +}
> +
>  static inline uint32_t gic_read_icc_sre(void)
>  {
>  	uint32_t val;
> -	asm volatile ("mrs %0, " ICC_SRE_EL3 : "=r" (val));
> +
> +	if(current_el() == CURRENTEL_EL3)
> +		asm volatile ("mrs %0, " ICC_SRE_EL3 : "=r" (val));
> +	else
> +		asm volatile ("mrs %0, " ICC_SRE_EL2 : "=r" (val));
> +
>  	return val;
>  }
>  
>  static inline void gic_write_icc_sre(uint32_t val)
>  {
> -	asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val));
> +	if(current_el() == CURRENTEL_EL3)
> +		asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val));
> +	else
> +		asm volatile ("msr " ICC_SRE_EL2 ", %0" : : "r" (val));
>  }
>  
> -static inline void gic_write_icc_ctlr(uint32_t val)
> +static inline void gic_write_icc_ctlr_el3(uint32_t val)
>  {
>  	asm volatile ("msr " ICC_CTLR_EL3 ", %0" : : "r" (val));
>  }
>  
> +static inline void gic_write_icc_ctlr_el1(uint32_t val)
> +{
> +	asm volatile ("msr " ICC_CTLR_EL1 ", %0" : : "r" (val));
> +}
> +
> +static inline void gic_init_icc_ctlr()
> +{
> +	if(current_el() == CURRENTEL_EL3)
> +		gic_write_icc_ctlr_el3(ICC_CTLR_EL3_RESET);
> +	else
> +		gic_write_icc_ctlr_el1(ICC_CTLR_EL1_RESET);
> +}
> +
>  #endif
> diff --git a/gic-v3.c b/gic-v3.c
> index ae2d2bc..4850572 100644
> --- a/gic-v3.c
> +++ b/gic-v3.c
> @@ -121,6 +121,6 @@ void gic_secure_init(void)
>  	gic_write_icc_sre(sre);
>  	isb();
>  
> -	gic_write_icc_ctlr(0);
> +	gic_init_icc_ctlr();
>  	isb();
>  }


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RE: [boot-wrapper PATCH 3/5] gic-v3: Prepare for gicv3 with EL2

[Jaxson Han]

Hi Andre,

> -----Original Message-----
> From: Andre Przywara <andre.przywara@arm.com>
> Sent: Monday, April 26, 2021 7:48 PM
> To: Jaxson Han <Jaxson.Han@arm.com>
> Cc: Mark Rutland <Mark.Rutland@arm.com>; linux-arm-
> kernel@lists.infradead.org; Wei Chen <Wei.Chen@arm.com>
> Subject: Re: [boot-wrapper PATCH 3/5] gic-v3: Prepare for gicv3 with EL2
> 
> On Tue, 20 Apr 2021 15:24:36 +0800
> Jaxson Han <jaxson.han@arm.com> wrote:
> 
> > This is a preparation for allowing boot-wrapper configuring the gicv3
> > with EL2.
> 
> The GIC is always confusing, so can you please give some more background
> here? The introduction of ICC_SRE_EL2 looks straight-forward enough, but
> the change to the ICC_CTLR_RESET register deserves some comments, I guess.

Right, I will put more details here.

Thanks,
Jaxson

> 
> Cheers,
> Andre
> 
> > Signed-off-by: Jaxson Han <jaxson.han@arm.com>
> > ---
> >  arch/aarch32/include/asm/gic-v3.h |  7 ++++++
> > arch/aarch64/include/asm/gic-v3.h | 38 ++++++++++++++++++++++++++++-
> --
> >  gic-v3.c                          |  2 +-
> >  3 files changed, 43 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/aarch32/include/asm/gic-v3.h
> > b/arch/aarch32/include/asm/gic-v3.h
> > index ec9a327..86abe09 100644
> > --- a/arch/aarch32/include/asm/gic-v3.h
> > +++ b/arch/aarch32/include/asm/gic-v3.h
> > @@ -9,6 +9,8 @@
> >  #ifndef __ASM_AARCH32_GICV3_H
> >  #define __ASM_AARCH32_GICV3_H
> >
> > +#define ICC_CTLR_RESET	(0UL)
> > +
> >  static inline uint32_t gic_read_icc_sre(void)  {
> >  	uint32_t val;
> > @@ -26,4 +28,9 @@ static inline void gic_write_icc_ctlr(uint32_t val)
> >  	asm volatile ("mcr p15, 6, %0, c12, c12, 4" : : "r" (val));  }
> >
> > +static inline void gic_init_icc_ctlr() {
> > +	gic_write_icc_ctlr(ICC_CTLR_RESET);
> > +}
> > +
> >  #endif
> > diff --git a/arch/aarch64/include/asm/gic-v3.h
> > b/arch/aarch64/include/asm/gic-v3.h
> > index e743c02..b3dfbd3 100644
> > --- a/arch/aarch64/include/asm/gic-v3.h
> > +++ b/arch/aarch64/include/asm/gic-v3.h
> > @@ -15,21 +15,53 @@
> >  #define ICC_CTLR_EL3	"S3_6_C12_C12_4"
> >  #define ICC_PMR_EL1	"S3_0_C4_C6_0"
> >
> > +#define ICC_CTLR_EL3_RESET	(0UL)
> > +#define ICC_CTLR_EL1_RESET	(0UL)
> > +
> > +static inline uint32_t current_el(void) {
> > +	uint32_t val;
> > +
> > +	asm volatile ("mrs %0, CurrentEL" : "=r" (val));
> > +	return val;
> > +}
> > +
> >  static inline uint32_t gic_read_icc_sre(void)  {
> >  	uint32_t val;
> > -	asm volatile ("mrs %0, " ICC_SRE_EL3 : "=r" (val));
> > +
> > +	if(current_el() == CURRENTEL_EL3)
> > +		asm volatile ("mrs %0, " ICC_SRE_EL3 : "=r" (val));
> > +	else
> > +		asm volatile ("mrs %0, " ICC_SRE_EL2 : "=r" (val));
> > +
> >  	return val;
> >  }
> >
> >  static inline void gic_write_icc_sre(uint32_t val)  {
> > -	asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val));
> > +	if(current_el() == CURRENTEL_EL3)
> > +		asm volatile ("msr " ICC_SRE_EL3 ", %0" : : "r" (val));
> > +	else
> > +		asm volatile ("msr " ICC_SRE_EL2 ", %0" : : "r" (val));
> >  }
> >
> > -static inline void gic_write_icc_ctlr(uint32_t val)
> > +static inline void gic_write_icc_ctlr_el3(uint32_t val)
> >  {
> >  	asm volatile ("msr " ICC_CTLR_EL3 ", %0" : : "r" (val));  }
> >
> > +static inline void gic_write_icc_ctlr_el1(uint32_t val) {
> > +	asm volatile ("msr " ICC_CTLR_EL1 ", %0" : : "r" (val)); }
> > +
> > +static inline void gic_init_icc_ctlr() {
> > +	if(current_el() == CURRENTEL_EL3)
> > +		gic_write_icc_ctlr_el3(ICC_CTLR_EL3_RESET);
> > +	else
> > +		gic_write_icc_ctlr_el1(ICC_CTLR_EL1_RESET);
> > +}
> > +
> >  #endif
> > diff --git a/gic-v3.c b/gic-v3.c
> > index ae2d2bc..4850572 100644
> > --- a/gic-v3.c
> > +++ b/gic-v3.c
> > @@ -121,6 +121,6 @@ void gic_secure_init(void)
> >  	gic_write_icc_sre(sre);
> >  	isb();
> >
> > -	gic_write_icc_ctlr(0);
> > +	gic_init_icc_ctlr();
> >  	isb();
> >  }


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[boot-wrapper PATCH 4/5] aarch64: Prepare for booting with EL2

[Jaxson Han]

Prepare for allowing boot-wrapper to be entered in EL2.

Signed-off-by: Jaxson Han <jaxson.han@arm.com>
---
 arch/aarch64/utils.S | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/aarch64/utils.S b/arch/aarch64/utils.S
index ae22ea7..94e9931 100644
--- a/arch/aarch64/utils.S
+++ b/arch/aarch64/utils.S
@@ -37,10 +37,18 @@ find_logical_id:
 	ret
 
 /*
- * Setup EL3 vectors
+ * Setup EL3/EL2 vectors
  * x0: vector address
  */
 setup_vector:
+	mrs	x1, CurrentEL
+	cmp	x1, #CURRENTEL_EL2
+	b.eq	1f
+
 	msr	VBAR_EL3, x0
 	isb
 	ret
+
+1:	msr	VBAR_EL2, x0
+	isb
+	ret
-- 
2.25.1


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Re: [boot-wrapper PATCH 4/5] aarch64: Prepare for booting with EL2

[Andre Przywara]

On Tue, 20 Apr 2021 15:24:37 +0800
Jaxson Han <jaxson.han@arm.com> wrote:

> Prepare for allowing boot-wrapper to be entered in EL2.
> 
> Signed-off-by: Jaxson Han <jaxson.han@arm.com>

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Thanks,
Andre

> ---
>  arch/aarch64/utils.S | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/aarch64/utils.S b/arch/aarch64/utils.S
> index ae22ea7..94e9931 100644
> --- a/arch/aarch64/utils.S
> +++ b/arch/aarch64/utils.S
> @@ -37,10 +37,18 @@ find_logical_id:
>  	ret
>  
>  /*
> - * Setup EL3 vectors
> + * Setup EL3/EL2 vectors
>   * x0: vector address
>   */
>  setup_vector:
> +	mrs	x1, CurrentEL
> +	cmp	x1, #CURRENTEL_EL2
> +	b.eq	1f
> +
>  	msr	VBAR_EL3, x0
>  	isb
>  	ret
> +
> +1:	msr	VBAR_EL2, x0
> +	isb
> +	ret


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[boot-wrapper PATCH 5/5] aarch64: Introduce EL2 boot code for Armv8-R AArch64

[Jaxson Han]

The Armv8-R AArch64 profile does not support the EL3 exception level.
The Armv8-R AArch64 profile allows for an (optional) VMSAv8-64 MMU
at EL1, which allows to run off-the-shelf Linux. However EL2 only
supports a PMSA, which is not supported by Linux, so we need to drop
into EL1 before entering the kernel.

The boot sequence is:
If CurrentEL == EL3, then goto EL3 initialisation and drop to lower EL
  before entering the kernel.
If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf (Armv8-R aarch64),
  then goto Armv8-R AArch64 initialisation and drop to EL1 before
  entering the kernel.
Else, no initialisation and keep the current EL before entering the
  kernel.

Signed-off-by: Jaxson Han <jaxson.han@arm.com>
---
 arch/aarch64/boot.S | 51 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
index f7dbf3f..6961a2a 100644
--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
@@ -25,16 +25,22 @@ _start:
 	 * Boot sequence
 	 * If CurrentEL == EL3, then goto EL3 initialisation and drop to
 	 *   lower EL before entering the kernel.
+	 * If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf, then goto
+	 *   Armv8-R AArch64 initialisation and drop to EL1 before
+	 *   entering the kernel.
 	 * Else, no initialisation and keep the current EL before
 	 *   entering the kernel.
 	 */
 	mrs	x0, CurrentEL
 	cmp	x0, #CURRENTEL_EL3
 	beq	el3_init
+	cmp	x0, #CURRENTEL_EL2
+	beq	el2_init
 
 	/*
 	 * We stay in the current EL for entering the kernel
 	 */
+keep_el:
 	mov	w0, #1
 	ldr	x1, =flag_keep_el
 	str	w0, [x1]
@@ -112,6 +118,43 @@ el3_init:
 	str	w0, [x1]
 	b	el_max_init
 
+	/*
+	 * EL2 Armv8-R AArch64 initialisation
+	 */
+el2_init:
+	/* Detect Armv8-R AArch64 */
+	mrs	x1, id_aa64mmfr0_el1
+	ubfx	x1, x1, #48, #4			// MSA
+	/* 0xf means Armv8-R AArch64 */
+	cmp	x1, 0xf
+	bne	keep_el
+
+	mrs	x0, midr_el1
+	msr	vpidr_el2, x0
+
+	mrs	x0, mpidr_el1
+	msr	vmpidr_el2, x0
+
+	mov	x0, #(1 << 31)			// VTCR_MSA: VMSAv8-64 support
+	msr	vtcr_el2, x0
+
+	/* Enable pointer authentication if present */
+	mrs	x1, id_aa64isar1_el1
+	ldr	x2, =(((0xff) << 24) | (0xff << 4))
+	and	x1, x1, x2
+	cbz	x1, 1f
+
+	mrs	x0, hcr_el2
+	orr	x0, x0, #(1 << 40)		// AP key enable
+	orr	x0, x0, #(1 << 41)		// AP insn enable
+	msr	hcr_el2, x0
+
+1:	isb
+	mov	w0, #SPSR_KERNEL_EL1
+	ldr	x1, =spsr_to_elx
+	str	w0, [x1]
+	b	el_max_init
+
 el_max_init:
 	ldr	x0, =CNTFRQ
 	msr	cntfrq_el0, x0
@@ -169,10 +212,18 @@ jump_kernel:
 	 */
 	bfi	x4, x19, #5, #1
 
+	mrs	x5, CurrentEL
+	cmp	x5, #CURRENTEL_EL2
+	b.eq	1f
+
 	msr	elr_el3, x19
 	msr	spsr_el3, x4
 	eret
 
+1:	msr	elr_el2, x19
+	msr	spsr_el2, x4
+	eret
+
 	.ltorg
 
 	.data
-- 
2.25.1


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Re: [boot-wrapper PATCH 5/5] aarch64: Introduce EL2 boot code for Armv8-R AArch64

[Andre Przywara]

On Tue, 20 Apr 2021 15:24:38 +0800
Jaxson Han <jaxson.han@arm.com> wrote:

Hi,

> The Armv8-R AArch64 profile does not support the EL3 exception level.
> The Armv8-R AArch64 profile allows for an (optional) VMSAv8-64 MMU
> at EL1, which allows to run off-the-shelf Linux. However EL2 only
> supports a PMSA, which is not supported by Linux, so we need to drop
> into EL1 before entering the kernel.
> 
> The boot sequence is:
> If CurrentEL == EL3, then goto EL3 initialisation and drop to lower EL
>   before entering the kernel.
> If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf (Armv8-R aarch64),
>   then goto Armv8-R AArch64 initialisation and drop to EL1 before
>   entering the kernel.
> Else, no initialisation and keep the current EL before entering the
>   kernel.
> 
> Signed-off-by: Jaxson Han <jaxson.han@arm.com>
> ---
>  arch/aarch64/boot.S | 51 +++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 51 insertions(+)
> 
> diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
> index f7dbf3f..6961a2a 100644
> --- a/arch/aarch64/boot.S
> +++ b/arch/aarch64/boot.S
> @@ -25,16 +25,22 @@ _start:
>  	 * Boot sequence
>  	 * If CurrentEL == EL3, then goto EL3 initialisation and drop to
>  	 *   lower EL before entering the kernel.
> +	 * If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf, then goto
> +	 *   Armv8-R AArch64 initialisation and drop to EL1 before
> +	 *   entering the kernel.
>  	 * Else, no initialisation and keep the current EL before
>  	 *   entering the kernel.
>  	 */
>  	mrs	x0, CurrentEL
>  	cmp	x0, #CURRENTEL_EL3
>  	beq	el3_init
> +	cmp	x0, #CURRENTEL_EL2
> +	beq	el2_init

nitpick: I tend to compare against EL2, then use b.gt for EL3, b.lt for
EL1 and b.eq for EL2 code. Saves you an extra cmp here.

>  	/*
>  	 * We stay in the current EL for entering the kernel
>  	 */
> +keep_el:
>  	mov	w0, #1
>  	ldr	x1, =flag_keep_el
>  	str	w0, [x1]
> @@ -112,6 +118,43 @@ el3_init:
>  	str	w0, [x1]
>  	b	el_max_init
>  
> +	/*
> +	 * EL2 Armv8-R AArch64 initialisation
> +	 */
> +el2_init:
> +	/* Detect Armv8-R AArch64 */
> +	mrs	x1, id_aa64mmfr0_el1
> +	ubfx	x1, x1, #48, #4			// MSA
> +	/* 0xf means Armv8-R AArch64 */
> +	cmp	x1, 0xf
> +	bne	keep_el

Don't we need to also check bits[55:52], to have at least 0b0010?
IIUC the support for VMSA in EL1&0 is optional, and should be checked
before we proceed? VTCR_EL2[31] can only be set in the 0b0010 case.

> +
> +	mrs	x0, midr_el1
> +	msr	vpidr_el2, x0
> +
> +	mrs	x0, mpidr_el1
> +	msr	vmpidr_el2, x0
> +
> +	mov	x0, #(1 << 31)			// VTCR_MSA: VMSAv8-64 support
> +	msr	vtcr_el2, x0
> +
> +	/* Enable pointer authentication if present */
> +	mrs	x1, id_aa64isar1_el1
> +	ldr	x2, =(((0xff) << 24) | (0xff << 4))

Each feature only holds four bits, so the mask you shift should be 0xf.

> +	and	x1, x1, x2
> +	cbz	x1, 1f
> +
> +	mrs	x0, hcr_el2

Shouldn't we force HCR_EL2, instead of modifying it? Just to make sure
nothing unexpected traps into EL2, which we don't handle very well?
So basically just set bit 31 (RES1), plus those two bits on top, if
needed. But I also wonder about FIEN[47] and EnSCXT[53] ...


Rest looks alright.

Cheers,
Andre

> +	orr	x0, x0, #(1 << 40)		// AP key enable
> +	orr	x0, x0, #(1 << 41)		// AP insn enable
> +	msr	hcr_el2, x0
> +
> +1:	isb
> +	mov	w0, #SPSR_KERNEL_EL1
> +	ldr	x1, =spsr_to_elx
> +	str	w0, [x1]
> +	b	el_max_init
> +
>  el_max_init:
>  	ldr	x0, =CNTFRQ
>  	msr	cntfrq_el0, x0
> @@ -169,10 +212,18 @@ jump_kernel:
>  	 */
>  	bfi	x4, x19, #5, #1
>  
> +	mrs	x5, CurrentEL
> +	cmp	x5, #CURRENTEL_EL2
> +	b.eq	1f
> +
>  	msr	elr_el3, x19
>  	msr	spsr_el3, x4
>  	eret
>  
> +1:	msr	elr_el2, x19
> +	msr	spsr_el2, x4
> +	eret
> +
>  	.ltorg
>  
>  	.data


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RE: [boot-wrapper PATCH 5/5] aarch64: Introduce EL2 boot code for Armv8-R AArch64

[Jaxson Han]

Hi Andre,

> -----Original Message-----
> From: Andre Przywara <andre.przywara@arm.com>
> Sent: Monday, April 26, 2021 8:36 PM
> To: Jaxson Han <Jaxson.Han@arm.com>
> Cc: Mark Rutland <Mark.Rutland@arm.com>; linux-arm-
> kernel@lists.infradead.org; Wei Chen <Wei.Chen@arm.com>
> Subject: Re: [boot-wrapper PATCH 5/5] aarch64: Introduce EL2 boot code for
> Armv8-R AArch64
> 
> On Tue, 20 Apr 2021 15:24:38 +0800
> Jaxson Han <jaxson.han@arm.com> wrote:
> 
> Hi,
> 
> > The Armv8-R AArch64 profile does not support the EL3 exception level.
> > The Armv8-R AArch64 profile allows for an (optional) VMSAv8-64 MMU at
> > EL1, which allows to run off-the-shelf Linux. However EL2 only
> > supports a PMSA, which is not supported by Linux, so we need to drop
> > into EL1 before entering the kernel.
> >
> > The boot sequence is:
> > If CurrentEL == EL3, then goto EL3 initialisation and drop to lower EL
> >   before entering the kernel.
> > If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf (Armv8-R aarch64),
> >   then goto Armv8-R AArch64 initialisation and drop to EL1 before
> >   entering the kernel.
> > Else, no initialisation and keep the current EL before entering the
> >   kernel.
> >
> > Signed-off-by: Jaxson Han <jaxson.han@arm.com>
> > ---
> >  arch/aarch64/boot.S | 51
> > +++++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 51 insertions(+)
> >
> > diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index
> > f7dbf3f..6961a2a 100644
> > --- a/arch/aarch64/boot.S
> > +++ b/arch/aarch64/boot.S
> > @@ -25,16 +25,22 @@ _start:
> >  	 * Boot sequence
> >  	 * If CurrentEL == EL3, then goto EL3 initialisation and drop to
> >  	 *   lower EL before entering the kernel.
> > +	 * If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf, then goto
> > +	 *   Armv8-R AArch64 initialisation and drop to EL1 before
> > +	 *   entering the kernel.
> >  	 * Else, no initialisation and keep the current EL before
> >  	 *   entering the kernel.
> >  	 */
> >  	mrs	x0, CurrentEL
> >  	cmp	x0, #CURRENTEL_EL3
> >  	beq	el3_init
> > +	cmp	x0, #CURRENTEL_EL2
> > +	beq	el2_init
> 
> nitpick: I tend to compare against EL2, then use b.gt for EL3, b.lt for
> EL1 and b.eq for EL2 code. Saves you an extra cmp here.

Exactly, I will. Thanks!

> 
> >  	/*
> >  	 * We stay in the current EL for entering the kernel
> >  	 */
> > +keep_el:
> >  	mov	w0, #1
> >  	ldr	x1, =flag_keep_el
> >  	str	w0, [x1]
> > @@ -112,6 +118,43 @@ el3_init:
> >  	str	w0, [x1]
> >  	b	el_max_init
> >
> > +	/*
> > +	 * EL2 Armv8-R AArch64 initialisation
> > +	 */
> > +el2_init:
> > +	/* Detect Armv8-R AArch64 */
> > +	mrs	x1, id_aa64mmfr0_el1
> > +	ubfx	x1, x1, #48, #4			// MSA
> > +	/* 0xf means Armv8-R AArch64 */
> > +	cmp	x1, 0xf
> > +	bne	keep_el
> 
> Don't we need to also check bits[55:52], to have at least 0b0010?
> IIUC the support for VMSA in EL1&0 is optional, and should be checked
> before we proceed? VTCR_EL2[31] can only be set in the 0b0010 case.

Yes, it should be checked, I will add it.

> 
> > +
> > +	mrs	x0, midr_el1
> > +	msr	vpidr_el2, x0
> > +
> > +	mrs	x0, mpidr_el1
> > +	msr	vmpidr_el2, x0
> > +
> > +	mov	x0, #(1 << 31)			// VTCR_MSA: VMSAv8-64
> support
> > +	msr	vtcr_el2, x0
> > +
> > +	/* Enable pointer authentication if present */
> > +	mrs	x1, id_aa64isar1_el1
> > +	ldr	x2, =(((0xff) << 24) | (0xff << 4))
> 
> Each feature only holds four bits, so the mask you shift should be 0xf.

Yes, I will fix.

> 
> > +	and	x1, x1, x2
> > +	cbz	x1, 1f
> > +
> > +	mrs	x0, hcr_el2
> 
> Shouldn't we force HCR_EL2, instead of modifying it? Just to make sure
> nothing unexpected traps into EL2, which we don't handle very well?
> So basically just set bit 31 (RES1), plus those two bits on top, if needed. But I
> also wonder about FIEN[47] and EnSCXT[53] ...

Right, we should force to set HCR_EL2. The API and APK is needed.
And I will also check if we need the FIEN[47] and EnSCXT[53].

Thanks,
Jaxson

> 
> 
> Rest looks alright.
> 
> Cheers,
> Andre
> 
> > +	orr	x0, x0, #(1 << 40)		// AP key enable
> > +	orr	x0, x0, #(1 << 41)		// AP insn enable
> > +	msr	hcr_el2, x0
> > +
> > +1:	isb
> > +	mov	w0, #SPSR_KERNEL_EL1
> > +	ldr	x1, =spsr_to_elx
> > +	str	w0, [x1]
> > +	b	el_max_init
> > +
> >  el_max_init:
> >  	ldr	x0, =CNTFRQ
> >  	msr	cntfrq_el0, x0
> > @@ -169,10 +212,18 @@ jump_kernel:
> >  	 */
> >  	bfi	x4, x19, #5, #1
> >
> > +	mrs	x5, CurrentEL
> > +	cmp	x5, #CURRENTEL_EL2
> > +	b.eq	1f
> > +
> >  	msr	elr_el3, x19
> >  	msr	spsr_el3, x4
> >  	eret
> >
> > +1:	msr	elr_el2, x19
> > +	msr	spsr_el2, x4
> > +	eret
> > +
> >  	.ltorg
> >
> >  	.data


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RE: [boot-wrapper PATCH 5/5] aarch64: Introduce EL2 boot code for Armv8-R AArch64

[Jaxson Han]

Hi Andre,

Since GCC 11 has been released and GCC 11 supports the ' -march=armv8-r',
we got a problem when compile the boot-wrapper with ' -march=armv8-r':
| ../git/arch/aarch64/boot.S:71: Error: selected processor does not support system register name 'scr_el3'
| ../git/arch/aarch64/boot.S:73: Error: selected processor does not support system register name 'cptr_el3'
| ../git/arch/aarch64/boot.S:84: Error: selected processor does not support system register name 'mdcr_el3'
| ../git/arch/aarch64/boot.S:90: Error: selected processor does not support system register name 'cptr_el3'
| ../git/arch/aarch64/boot.S:92: Error: selected processor does not support system register name 'cptr_el3'
| ../git/arch/aarch64/boot.S:194: Error: selected processor does not support system register name 'elr_el3'
| ../git/arch/aarch64/boot.S:195: Error: selected processor does not support system register name 'spsr_el3'

It seems we may need some #if macro to disable all _el3 registers, but it will
break our auto-detection (users should add more compile/build parameter).
So, may I ask your suggestions? :)

Cheers,
Jaxson 

> -----Original Message-----
> From: Jaxson Han
> Sent: Wednesday, April 28, 2021 11:44 AM
> To: Andre Przywara <andre.przywara@arm.com>
> Cc: Mark Rutland <Mark.Rutland@arm.com>; linux-arm-
> kernel@lists.infradead.org; Wei Chen <Wei.Chen@arm.com>
> Subject: RE: [boot-wrapper PATCH 5/5] aarch64: Introduce EL2 boot code for
> Armv8-R AArch64
> 
> Hi Andre,
> 
> > -----Original Message-----
> > From: Andre Przywara <andre.przywara@arm.com>
> > Sent: Monday, April 26, 2021 8:36 PM
> > To: Jaxson Han <Jaxson.Han@arm.com>
> > Cc: Mark Rutland <Mark.Rutland@arm.com>; linux-arm-
> > kernel@lists.infradead.org; Wei Chen <Wei.Chen@arm.com>
> > Subject: Re: [boot-wrapper PATCH 5/5] aarch64: Introduce EL2 boot code
> > for Armv8-R AArch64
> >
> > On Tue, 20 Apr 2021 15:24:38 +0800
> > Jaxson Han <jaxson.han@arm.com> wrote:
> >
> > Hi,
> >
> > > The Armv8-R AArch64 profile does not support the EL3 exception level.
> > > The Armv8-R AArch64 profile allows for an (optional) VMSAv8-64 MMU
> > > at EL1, which allows to run off-the-shelf Linux. However EL2 only
> > > supports a PMSA, which is not supported by Linux, so we need to drop
> > > into EL1 before entering the kernel.
> > >
> > > The boot sequence is:
> > > If CurrentEL == EL3, then goto EL3 initialisation and drop to lower EL
> > >   before entering the kernel.
> > > If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf (Armv8-R aarch64),
> > >   then goto Armv8-R AArch64 initialisation and drop to EL1 before
> > >   entering the kernel.
> > > Else, no initialisation and keep the current EL before entering the
> > >   kernel.
> > >
> > > Signed-off-by: Jaxson Han <jaxson.han@arm.com>
> > > ---
> > >  arch/aarch64/boot.S | 51
> > > +++++++++++++++++++++++++++++++++++++++++++++
> > >  1 file changed, 51 insertions(+)
> > >
> > > diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index
> > > f7dbf3f..6961a2a 100644
> > > --- a/arch/aarch64/boot.S
> > > +++ b/arch/aarch64/boot.S
> > > @@ -25,16 +25,22 @@ _start:
> > >  	 * Boot sequence
> > >  	 * If CurrentEL == EL3, then goto EL3 initialisation and drop to
> > >  	 *   lower EL before entering the kernel.
> > > +	 * If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf, then goto
> > > +	 *   Armv8-R AArch64 initialisation and drop to EL1 before
> > > +	 *   entering the kernel.
> > >  	 * Else, no initialisation and keep the current EL before
> > >  	 *   entering the kernel.
> > >  	 */
> > >  	mrs	x0, CurrentEL
> > >  	cmp	x0, #CURRENTEL_EL3
> > >  	beq	el3_init
> > > +	cmp	x0, #CURRENTEL_EL2
> > > +	beq	el2_init
> >
> > nitpick: I tend to compare against EL2, then use b.gt for EL3, b.lt
> > for
> > EL1 and b.eq for EL2 code. Saves you an extra cmp here.
> 
> Exactly, I will. Thanks!
> 
> >
> > >  	/*
> > >  	 * We stay in the current EL for entering the kernel
> > >  	 */
> > > +keep_el:
> > >  	mov	w0, #1
> > >  	ldr	x1, =flag_keep_el
> > >  	str	w0, [x1]
> > > @@ -112,6 +118,43 @@ el3_init:
> > >  	str	w0, [x1]
> > >  	b	el_max_init
> > >
> > > +	/*
> > > +	 * EL2 Armv8-R AArch64 initialisation
> > > +	 */
> > > +el2_init:
> > > +	/* Detect Armv8-R AArch64 */
> > > +	mrs	x1, id_aa64mmfr0_el1
> > > +	ubfx	x1, x1, #48, #4			// MSA
> > > +	/* 0xf means Armv8-R AArch64 */
> > > +	cmp	x1, 0xf
> > > +	bne	keep_el
> >
> > Don't we need to also check bits[55:52], to have at least 0b0010?
> > IIUC the support for VMSA in EL1&0 is optional, and should be checked
> > before we proceed? VTCR_EL2[31] can only be set in the 0b0010 case.
> 
> Yes, it should be checked, I will add it.
> 
> >
> > > +
> > > +	mrs	x0, midr_el1
> > > +	msr	vpidr_el2, x0
> > > +
> > > +	mrs	x0, mpidr_el1
> > > +	msr	vmpidr_el2, x0
> > > +
> > > +	mov	x0, #(1 << 31)			// VTCR_MSA: VMSAv8-64
> > support
> > > +	msr	vtcr_el2, x0
> > > +
> > > +	/* Enable pointer authentication if present */
> > > +	mrs	x1, id_aa64isar1_el1
> > > +	ldr	x2, =(((0xff) << 24) | (0xff << 4))
> >
> > Each feature only holds four bits, so the mask you shift should be 0xf.
> 
> Yes, I will fix.
> 
> >
> > > +	and	x1, x1, x2
> > > +	cbz	x1, 1f
> > > +
> > > +	mrs	x0, hcr_el2
> >
> > Shouldn't we force HCR_EL2, instead of modifying it? Just to make sure
> > nothing unexpected traps into EL2, which we don't handle very well?
> > So basically just set bit 31 (RES1), plus those two bits on top, if
> > needed. But I also wonder about FIEN[47] and EnSCXT[53] ...
> 
> Right, we should force to set HCR_EL2. The API and APK is needed.
> And I will also check if we need the FIEN[47] and EnSCXT[53].
> 
> Thanks,
> Jaxson
> 
> >
> >
> > Rest looks alright.
> >
> > Cheers,
> > Andre
> >
> > > +	orr	x0, x0, #(1 << 40)		// AP key enable
> > > +	orr	x0, x0, #(1 << 41)		// AP insn enable
> > > +	msr	hcr_el2, x0
> > > +
> > > +1:	isb
> > > +	mov	w0, #SPSR_KERNEL_EL1
> > > +	ldr	x1, =spsr_to_elx
> > > +	str	w0, [x1]
> > > +	b	el_max_init
> > > +
> > >  el_max_init:
> > >  	ldr	x0, =CNTFRQ
> > >  	msr	cntfrq_el0, x0
> > > @@ -169,10 +212,18 @@ jump_kernel:
> > >  	 */
> > >  	bfi	x4, x19, #5, #1
> > >
> > > +	mrs	x5, CurrentEL
> > > +	cmp	x5, #CURRENTEL_EL2
> > > +	b.eq	1f
> > > +
> > >  	msr	elr_el3, x19
> > >  	msr	spsr_el3, x4
> > >  	eret
> > >
> > > +1:	msr	elr_el2, x19
> > > +	msr	spsr_el2, x4
> > > +	eret
> > > +
> > >  	.ltorg
> > >
> > >  	.data


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Re: [boot-wrapper PATCH 5/5] aarch64: Introduce EL2 boot code for Armv8-R AArch64

[Andre Przywara]

On Mon, 10 May 2021 02:13:45 +0000
Jaxson Han <Jaxson.Han@arm.com> wrote:

> Hi Andre,
> 
> Since GCC 11 has been released and GCC 11 supports the ' -march=armv8-r',
> we got a problem when compile the boot-wrapper with ' -march=armv8-r':
> | ../git/arch/aarch64/boot.S:71: Error: selected processor does not support system register name 'scr_el3'
> | ../git/arch/aarch64/boot.S:73: Error: selected processor does not support system register name 'cptr_el3'
> | ../git/arch/aarch64/boot.S:84: Error: selected processor does not support system register name 'mdcr_el3'
> | ../git/arch/aarch64/boot.S:90: Error: selected processor does not support system register name 'cptr_el3'
> | ../git/arch/aarch64/boot.S:92: Error: selected processor does not support system register name 'cptr_el3'
> | ../git/arch/aarch64/boot.S:194: Error: selected processor does not support system register name 'elr_el3'
> | ../git/arch/aarch64/boot.S:195: Error: selected processor does not support system register name 'spsr_el3'
> 
> It seems we may need some #if macro to disable all _el3 registers, but it will
> break our auto-detection (users should add more compile/build parameter).
> So, may I ask your suggestions? :)

Why do you need that in the first place? I think your version worked
without it? At least Ubuntu's 9.3.0 compiled it just fine.
Or does GCC 11 complain about some v8-r specific registers and you need
to add this armv8-r to let them pass, sacrificing all EL3 registers on
the way?

One solution could be to move all accesses to v8-r registers into a
separate file, and only assemble/compile this with the v8-r switch. But
this sounds like some serious plumbing in the code base.

What you could try as well is to use this "s3_0_c12_c12_5" like system
register encoding style (this example is for ICC_SRE_EL1). The kernel
uses this trick to avoid dependencies on gas knowing about all (new)
system register names. Not sure if that is enough to trick gas into
accepting it?

Hope that helps.

Cheers,
Andre

> 
> Cheers,
> Jaxson 
> 
> > -----Original Message-----
> > From: Jaxson Han
> > Sent: Wednesday, April 28, 2021 11:44 AM
> > To: Andre Przywara <andre.przywara@arm.com>
> > Cc: Mark Rutland <Mark.Rutland@arm.com>; linux-arm-
> > kernel@lists.infradead.org; Wei Chen <Wei.Chen@arm.com>
> > Subject: RE: [boot-wrapper PATCH 5/5] aarch64: Introduce EL2 boot code for
> > Armv8-R AArch64
> > 
> > Hi Andre,
> >   
> > > -----Original Message-----
> > > From: Andre Przywara <andre.przywara@arm.com>
> > > Sent: Monday, April 26, 2021 8:36 PM
> > > To: Jaxson Han <Jaxson.Han@arm.com>
> > > Cc: Mark Rutland <Mark.Rutland@arm.com>; linux-arm-
> > > kernel@lists.infradead.org; Wei Chen <Wei.Chen@arm.com>
> > > Subject: Re: [boot-wrapper PATCH 5/5] aarch64: Introduce EL2 boot code
> > > for Armv8-R AArch64
> > >
> > > On Tue, 20 Apr 2021 15:24:38 +0800
> > > Jaxson Han <jaxson.han@arm.com> wrote:
> > >
> > > Hi,
> > >  
> > > > The Armv8-R AArch64 profile does not support the EL3 exception level.
> > > > The Armv8-R AArch64 profile allows for an (optional) VMSAv8-64 MMU
> > > > at EL1, which allows to run off-the-shelf Linux. However EL2 only
> > > > supports a PMSA, which is not supported by Linux, so we need to drop
> > > > into EL1 before entering the kernel.
> > > >
> > > > The boot sequence is:
> > > > If CurrentEL == EL3, then goto EL3 initialisation and drop to lower EL
> > > >   before entering the kernel.
> > > > If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf (Armv8-R aarch64),
> > > >   then goto Armv8-R AArch64 initialisation and drop to EL1 before
> > > >   entering the kernel.
> > > > Else, no initialisation and keep the current EL before entering the
> > > >   kernel.
> > > >
> > > > Signed-off-by: Jaxson Han <jaxson.han@arm.com>
> > > > ---
> > > >  arch/aarch64/boot.S | 51
> > > > +++++++++++++++++++++++++++++++++++++++++++++
> > > >  1 file changed, 51 insertions(+)
> > > >
> > > > diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index
> > > > f7dbf3f..6961a2a 100644
> > > > --- a/arch/aarch64/boot.S
> > > > +++ b/arch/aarch64/boot.S
> > > > @@ -25,16 +25,22 @@ _start:
> > > >  	 * Boot sequence
> > > >  	 * If CurrentEL == EL3, then goto EL3 initialisation and drop to
> > > >  	 *   lower EL before entering the kernel.
> > > > +	 * If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf, then goto
> > > > +	 *   Armv8-R AArch64 initialisation and drop to EL1 before
> > > > +	 *   entering the kernel.
> > > >  	 * Else, no initialisation and keep the current EL before
> > > >  	 *   entering the kernel.
> > > >  	 */
> > > >  	mrs	x0, CurrentEL
> > > >  	cmp	x0, #CURRENTEL_EL3
> > > >  	beq	el3_init
> > > > +	cmp	x0, #CURRENTEL_EL2
> > > > +	beq	el2_init  
> > >
> > > nitpick: I tend to compare against EL2, then use b.gt for EL3, b.lt
> > > for
> > > EL1 and b.eq for EL2 code. Saves you an extra cmp here.  
> > 
> > Exactly, I will. Thanks!
> >   
> > >  
> > > >  	/*
> > > >  	 * We stay in the current EL for entering the kernel
> > > >  	 */
> > > > +keep_el:
> > > >  	mov	w0, #1
> > > >  	ldr	x1, =flag_keep_el
> > > >  	str	w0, [x1]
> > > > @@ -112,6 +118,43 @@ el3_init:
> > > >  	str	w0, [x1]
> > > >  	b	el_max_init
> > > >
> > > > +	/*
> > > > +	 * EL2 Armv8-R AArch64 initialisation
> > > > +	 */
> > > > +el2_init:
> > > > +	/* Detect Armv8-R AArch64 */
> > > > +	mrs	x1, id_aa64mmfr0_el1
> > > > +	ubfx	x1, x1, #48, #4			// MSA
> > > > +	/* 0xf means Armv8-R AArch64 */
> > > > +	cmp	x1, 0xf
> > > > +	bne	keep_el  
> > >
> > > Don't we need to also check bits[55:52], to have at least 0b0010?
> > > IIUC the support for VMSA in EL1&0 is optional, and should be checked
> > > before we proceed? VTCR_EL2[31] can only be set in the 0b0010 case.  
> > 
> > Yes, it should be checked, I will add it.
> >   
> > >  
> > > > +
> > > > +	mrs	x0, midr_el1
> > > > +	msr	vpidr_el2, x0
> > > > +
> > > > +	mrs	x0, mpidr_el1
> > > > +	msr	vmpidr_el2, x0
> > > > +
> > > > +	mov	x0, #(1 << 31)			// VTCR_MSA: VMSAv8-64  
> > > support  
> > > > +	msr	vtcr_el2, x0
> > > > +
> > > > +	/* Enable pointer authentication if present */
> > > > +	mrs	x1, id_aa64isar1_el1
> > > > +	ldr	x2, =(((0xff) << 24) | (0xff << 4))  
> > >
> > > Each feature only holds four bits, so the mask you shift should be 0xf.  
> > 
> > Yes, I will fix.
> >   
> > >  
> > > > +	and	x1, x1, x2
> > > > +	cbz	x1, 1f
> > > > +
> > > > +	mrs	x0, hcr_el2  
> > >
> > > Shouldn't we force HCR_EL2, instead of modifying it? Just to make sure
> > > nothing unexpected traps into EL2, which we don't handle very well?
> > > So basically just set bit 31 (RES1), plus those two bits on top, if
> > > needed. But I also wonder about FIEN[47] and EnSCXT[53] ...  
> > 
> > Right, we should force to set HCR_EL2. The API and APK is needed.
> > And I will also check if we need the FIEN[47] and EnSCXT[53].
> > 
> > Thanks,
> > Jaxson
> >   
> > >
> > >
> > > Rest looks alright.
> > >
> > > Cheers,
> > > Andre
> > >  
> > > > +	orr	x0, x0, #(1 << 40)		// AP key enable
> > > > +	orr	x0, x0, #(1 << 41)		// AP insn enable
> > > > +	msr	hcr_el2, x0
> > > > +
> > > > +1:	isb
> > > > +	mov	w0, #SPSR_KERNEL_EL1
> > > > +	ldr	x1, =spsr_to_elx
> > > > +	str	w0, [x1]
> > > > +	b	el_max_init
> > > > +
> > > >  el_max_init:
> > > >  	ldr	x0, =CNTFRQ
> > > >  	msr	cntfrq_el0, x0
> > > > @@ -169,10 +212,18 @@ jump_kernel:
> > > >  	 */
> > > >  	bfi	x4, x19, #5, #1
> > > >
> > > > +	mrs	x5, CurrentEL
> > > > +	cmp	x5, #CURRENTEL_EL2
> > > > +	b.eq	1f
> > > > +
> > > >  	msr	elr_el3, x19
> > > >  	msr	spsr_el3, x4
> > > >  	eret
> > > >
> > > > +1:	msr	elr_el2, x19
> > > > +	msr	spsr_el2, x4
> > > > +	eret
> > > > +
> > > >  	.ltorg
> > > >
> > > >  	.data  
> 


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RE: [boot-wrapper PATCH 5/5] aarch64: Introduce EL2 boot code for Armv8-R AArch64

[Jaxson Han]

Hi Andre,

> -----Original Message-----
> From: Andre Przywara <andre.przywara@arm.com>
> Sent: Monday, May 10, 2021 4:55 PM
> To: Jaxson Han <Jaxson.Han@arm.com>
> Cc: Mark Rutland <Mark.Rutland@arm.com>; linux-arm-
> kernel@lists.infradead.org; Wei Chen <Wei.Chen@arm.com>
> Subject: Re: [boot-wrapper PATCH 5/5] aarch64: Introduce EL2 boot code for
> Armv8-R AArch64
> 
> On Mon, 10 May 2021 02:13:45 +0000
> Jaxson Han <Jaxson.Han@arm.com> wrote:
> 
> > Hi Andre,
> >
> > Since GCC 11 has been released and GCC 11 supports the '
> > -march=armv8-r', we got a problem when compile the boot-wrapper with '
> -march=armv8-r':
> > | ../git/arch/aarch64/boot.S:71: Error: selected processor does not support
> system register name 'scr_el3'
> > | ../git/arch/aarch64/boot.S:73: Error: selected processor does not support
> system register name 'cptr_el3'
> > | ../git/arch/aarch64/boot.S:84: Error: selected processor does not support
> system register name 'mdcr_el3'
> > | ../git/arch/aarch64/boot.S:90: Error: selected processor does not support
> system register name 'cptr_el3'
> > | ../git/arch/aarch64/boot.S:92: Error: selected processor does not support
> system register name 'cptr_el3'
> > | ../git/arch/aarch64/boot.S:194: Error: selected processor does not
> support system register name 'elr_el3'
> > | ../git/arch/aarch64/boot.S:195: Error: selected processor does not
> support system register name 'spsr_el3'
> >
> > It seems we may need some #if macro to disable all _el3 registers, but
> > it will break our auto-detection (users should add more compile/build
> parameter).
> > So, may I ask your suggestions? :)
> 
> Why do you need that in the first place? I think your version worked without
> it? At least Ubuntu's 9.3.0 compiled it just fine.
> Or does GCC 11 complain about some v8-r specific registers and you need to
> add this armv8-r to let them pass, sacrificing all EL3 registers on the way?

The problem comes from AIS yocto-bsp team. The reason they need this, I think,
may be that they want to test this new option for v8-r since GCC 11 supports
v8-r. Anyway, the current version works well. And I agree it's neither
necessary nor first priority to solve this problem for boot-wrapper. But I think
it's worth to discuss with you and see your suggestions :)

> 
> One solution could be to move all accesses to v8-r registers into a separate
> file, and only assemble/compile this with the v8-r switch. But this sounds like
> some serious plumbing in the code base.
> 
> What you could try as well is to use this "s3_0_c12_c12_5" like system
> register encoding style (this example is for ICC_SRE_EL1). The kernel uses this
> trick to avoid dependencies on gas knowing about all (new) system register
> names. Not sure if that is enough to trick gas into accepting it?
> 
> Hope that helps.

Yes, it helps! Based on this, we could easily evaluate the efforts:)

Thanks,
Jaxson

> 
> Cheers,
> Andre
> 
> >
> > Cheers,
> > Jaxson
> >
> > > -----Original Message-----
> > > From: Jaxson Han
> > > Sent: Wednesday, April 28, 2021 11:44 AM
> > > To: Andre Przywara <andre.przywara@arm.com>
> > > Cc: Mark Rutland <Mark.Rutland@arm.com>; linux-arm-
> > > kernel@lists.infradead.org; Wei Chen <Wei.Chen@arm.com>
> > > Subject: RE: [boot-wrapper PATCH 5/5] aarch64: Introduce EL2 boot
> > > code for Armv8-R AArch64
> > >
> > > Hi Andre,
> > >
> > > > -----Original Message-----
> > > > From: Andre Przywara <andre.przywara@arm.com>
> > > > Sent: Monday, April 26, 2021 8:36 PM
> > > > To: Jaxson Han <Jaxson.Han@arm.com>
> > > > Cc: Mark Rutland <Mark.Rutland@arm.com>; linux-arm-
> > > > kernel@lists.infradead.org; Wei Chen <Wei.Chen@arm.com>
> > > > Subject: Re: [boot-wrapper PATCH 5/5] aarch64: Introduce EL2 boot
> > > > code for Armv8-R AArch64
> > > >
> > > > On Tue, 20 Apr 2021 15:24:38 +0800 Jaxson Han <jaxson.han@arm.com>
> > > > wrote:
> > > >
> > > > Hi,
> > > >
> > > > > The Armv8-R AArch64 profile does not support the EL3 exception level.
> > > > > The Armv8-R AArch64 profile allows for an (optional) VMSAv8-64
> > > > > MMU at EL1, which allows to run off-the-shelf Linux. However EL2
> > > > > only supports a PMSA, which is not supported by Linux, so we
> > > > > need to drop into EL1 before entering the kernel.
> > > > >
> > > > > The boot sequence is:
> > > > > If CurrentEL == EL3, then goto EL3 initialisation and drop to lower EL
> > > > >   before entering the kernel.
> > > > > If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf (Armv8-R
> aarch64),
> > > > >   then goto Armv8-R AArch64 initialisation and drop to EL1 before
> > > > >   entering the kernel.
> > > > > Else, no initialisation and keep the current EL before entering the
> > > > >   kernel.
> > > > >
> > > > > Signed-off-by: Jaxson Han <jaxson.han@arm.com>
> > > > > ---
> > > > >  arch/aarch64/boot.S | 51
> > > > > +++++++++++++++++++++++++++++++++++++++++++++
> > > > >  1 file changed, 51 insertions(+)
> > > > >
> > > > > diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index
> > > > > f7dbf3f..6961a2a 100644
> > > > > --- a/arch/aarch64/boot.S
> > > > > +++ b/arch/aarch64/boot.S
> > > > > @@ -25,16 +25,22 @@ _start:
> > > > >  	 * Boot sequence
> > > > >  	 * If CurrentEL == EL3, then goto EL3 initialisation and drop to
> > > > >  	 *   lower EL before entering the kernel.
> > > > > +	 * If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf,
> then goto
> > > > > +	 *   Armv8-R AArch64 initialisation and drop to EL1 before
> > > > > +	 *   entering the kernel.
> > > > >  	 * Else, no initialisation and keep the current EL before
> > > > >  	 *   entering the kernel.
> > > > >  	 */
> > > > >  	mrs	x0, CurrentEL
> > > > >  	cmp	x0, #CURRENTEL_EL3
> > > > >  	beq	el3_init
> > > > > +	cmp	x0, #CURRENTEL_EL2
> > > > > +	beq	el2_init
> > > >
> > > > nitpick: I tend to compare against EL2, then use b.gt for EL3,
> > > > b.lt for
> > > > EL1 and b.eq for EL2 code. Saves you an extra cmp here.
> > >
> > > Exactly, I will. Thanks!
> > >
> > > >
> > > > >  	/*
> > > > >  	 * We stay in the current EL for entering the kernel
> > > > >  	 */
> > > > > +keep_el:
> > > > >  	mov	w0, #1
> > > > >  	ldr	x1, =flag_keep_el
> > > > >  	str	w0, [x1]
> > > > > @@ -112,6 +118,43 @@ el3_init:
> > > > >  	str	w0, [x1]
> > > > >  	b	el_max_init
> > > > >
> > > > > +	/*
> > > > > +	 * EL2 Armv8-R AArch64 initialisation
> > > > > +	 */
> > > > > +el2_init:
> > > > > +	/* Detect Armv8-R AArch64 */
> > > > > +	mrs	x1, id_aa64mmfr0_el1
> > > > > +	ubfx	x1, x1, #48, #4			// MSA
> > > > > +	/* 0xf means Armv8-R AArch64 */
> > > > > +	cmp	x1, 0xf
> > > > > +	bne	keep_el
> > > >
> > > > Don't we need to also check bits[55:52], to have at least 0b0010?
> > > > IIUC the support for VMSA in EL1&0 is optional, and should be
> > > > checked before we proceed? VTCR_EL2[31] can only be set in the
> 0b0010 case.
> > >
> > > Yes, it should be checked, I will add it.
> > >
> > > >
> > > > > +
> > > > > +	mrs	x0, midr_el1
> > > > > +	msr	vpidr_el2, x0
> > > > > +
> > > > > +	mrs	x0, mpidr_el1
> > > > > +	msr	vmpidr_el2, x0
> > > > > +
> > > > > +	mov	x0, #(1 << 31)			// VTCR_MSA:
> VMSAv8-64
> > > > support
> > > > > +	msr	vtcr_el2, x0
> > > > > +
> > > > > +	/* Enable pointer authentication if present */
> > > > > +	mrs	x1, id_aa64isar1_el1
> > > > > +	ldr	x2, =(((0xff) << 24) | (0xff << 4))
> > > >
> > > > Each feature only holds four bits, so the mask you shift should be 0xf.
> > >
> > > Yes, I will fix.
> > >
> > > >
> > > > > +	and	x1, x1, x2
> > > > > +	cbz	x1, 1f
> > > > > +
> > > > > +	mrs	x0, hcr_el2
> > > >
> > > > Shouldn't we force HCR_EL2, instead of modifying it? Just to make
> > > > sure nothing unexpected traps into EL2, which we don't handle very
> well?
> > > > So basically just set bit 31 (RES1), plus those two bits on top,
> > > > if needed. But I also wonder about FIEN[47] and EnSCXT[53] ...
> > >
> > > Right, we should force to set HCR_EL2. The API and APK is needed.
> > > And I will also check if we need the FIEN[47] and EnSCXT[53].
> > >
> > > Thanks,
> > > Jaxson
> > >
> > > >
> > > >
> > > > Rest looks alright.
> > > >
> > > > Cheers,
> > > > Andre
> > > >
> > > > > +	orr	x0, x0, #(1 << 40)		// AP key enable
> > > > > +	orr	x0, x0, #(1 << 41)		// AP insn enable
> > > > > +	msr	hcr_el2, x0
> > > > > +
> > > > > +1:	isb
> > > > > +	mov	w0, #SPSR_KERNEL_EL1
> > > > > +	ldr	x1, =spsr_to_elx
> > > > > +	str	w0, [x1]
> > > > > +	b	el_max_init
> > > > > +
> > > > >  el_max_init:
> > > > >  	ldr	x0, =CNTFRQ
> > > > >  	msr	cntfrq_el0, x0
> > > > > @@ -169,10 +212,18 @@ jump_kernel:
> > > > >  	 */
> > > > >  	bfi	x4, x19, #5, #1
> > > > >
> > > > > +	mrs	x5, CurrentEL
> > > > > +	cmp	x5, #CURRENTEL_EL2
> > > > > +	b.eq	1f
> > > > > +
> > > > >  	msr	elr_el3, x19
> > > > >  	msr	spsr_el3, x4
> > > > >  	eret
> > > > >
> > > > > +1:	msr	elr_el2, x19
> > > > > +	msr	spsr_el2, x4
> > > > > +	eret
> > > > > +
> > > > >  	.ltorg
> > > > >
> > > > >  	.data
> >


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Re: [boot-wrapper PATCH 5/5] aarch64: Introduce EL2 boot code for Armv8-R AArch64

[Andre Przywara]

On Tue, 11 May 2021 02:03:32 +0000
Jaxson Han <Jaxson.Han@arm.com> wrote:

Hi,

> > -----Original Message-----
> > From: Andre Przywara <andre.przywara@arm.com>
> > Sent: Monday, May 10, 2021 4:55 PM
> > To: Jaxson Han <Jaxson.Han@arm.com>
> > Cc: Mark Rutland <Mark.Rutland@arm.com>; linux-arm-
> > kernel@lists.infradead.org; Wei Chen <Wei.Chen@arm.com>
> > Subject: Re: [boot-wrapper PATCH 5/5] aarch64: Introduce EL2 boot code for
> > Armv8-R AArch64
> > 
> > On Mon, 10 May 2021 02:13:45 +0000
> > Jaxson Han <Jaxson.Han@arm.com> wrote:
> >   
> > > Hi Andre,
> > >
> > > Since GCC 11 has been released and GCC 11 supports the '
> > > -march=armv8-r', we got a problem when compile the boot-wrapper with '  
> > -march=armv8-r':  
> > > | ../git/arch/aarch64/boot.S:71: Error: selected processor does not support  
> > system register name 'scr_el3'  
> > > | ../git/arch/aarch64/boot.S:73: Error: selected processor does not support  
> > system register name 'cptr_el3'  
> > > | ../git/arch/aarch64/boot.S:84: Error: selected processor does not support  
> > system register name 'mdcr_el3'  
> > > | ../git/arch/aarch64/boot.S:90: Error: selected processor does not support  
> > system register name 'cptr_el3'  
> > > | ../git/arch/aarch64/boot.S:92: Error: selected processor does not support  
> > system register name 'cptr_el3'  
> > > | ../git/arch/aarch64/boot.S:194: Error: selected processor does not  
> > support system register name 'elr_el3'  
> > > | ../git/arch/aarch64/boot.S:195: Error: selected processor does not  
> > support system register name 'spsr_el3'  
> > >
> > > It seems we may need some #if macro to disable all _el3 registers, but
> > > it will break our auto-detection (users should add more compile/build  
> > parameter).  
> > > So, may I ask your suggestions? :)  
> > 
> > Why do you need that in the first place? I think your version worked without
> > it? At least Ubuntu's 9.3.0 compiled it just fine.
> > Or does GCC 11 complain about some v8-r specific registers and you need to
> > add this armv8-r to let them pass, sacrificing all EL3 registers on the way?  
> 
> The problem comes from AIS yocto-bsp team. The reason they need this, I think,
> may be that they want to test this new option for v8-r since GCC 11 supports
> v8-r. Anyway, the current version works well. And I agree it's neither
> necessary nor first priority to solve this problem for boot-wrapper. But I think
> it's worth to discuss with you and see your suggestions :)

Well, but each software package sets the stage for the compiler options
it can or cannot accept. And since the boot-wrapper is still foremost a
v8-A software, just compiling it with v8-r (or any other random switch)
won't work. So it's just not valid to use that switch there - it's the
task of the Makefile to set compiler options, any user choices have no
guarantee of working anyway.

And out of curiosity: what did you expect from using that option?

> > One solution could be to move all accesses to v8-r registers into a separate
> > file, and only assemble/compile this with the v8-r switch. But this sounds like
> > some serious plumbing in the code base.
> > 
> > What you could try as well is to use this "s3_0_c12_c12_5" like system
> > register encoding style (this example is for ICC_SRE_EL1). The kernel uses this
> > trick to avoid dependencies on gas knowing about all (new) system register
> > names. Not sure if that is enough to trick gas into accepting it?
> > 
> > Hope that helps.  
> 
> Yes, it helps! Based on this, we could easily evaluate the efforts:)

Did you change the EL3 registers this way? Was there any effect on the
code?

Cheers,
Andre

> > 
> > Cheers,
> > Andre
> >   
> > >
> > > Cheers,
> > > Jaxson
> > >  
> > > > -----Original Message-----
> > > > From: Jaxson Han
> > > > Sent: Wednesday, April 28, 2021 11:44 AM
> > > > To: Andre Przywara <andre.przywara@arm.com>
> > > > Cc: Mark Rutland <Mark.Rutland@arm.com>; linux-arm-
> > > > kernel@lists.infradead.org; Wei Chen <Wei.Chen@arm.com>
> > > > Subject: RE: [boot-wrapper PATCH 5/5] aarch64: Introduce EL2 boot
> > > > code for Armv8-R AArch64
> > > >
> > > > Hi Andre,
> > > >  
> > > > > -----Original Message-----
> > > > > From: Andre Przywara <andre.przywara@arm.com>
> > > > > Sent: Monday, April 26, 2021 8:36 PM
> > > > > To: Jaxson Han <Jaxson.Han@arm.com>
> > > > > Cc: Mark Rutland <Mark.Rutland@arm.com>; linux-arm-
> > > > > kernel@lists.infradead.org; Wei Chen <Wei.Chen@arm.com>
> > > > > Subject: Re: [boot-wrapper PATCH 5/5] aarch64: Introduce EL2 boot
> > > > > code for Armv8-R AArch64
> > > > >
> > > > > On Tue, 20 Apr 2021 15:24:38 +0800 Jaxson Han <jaxson.han@arm.com>
> > > > > wrote:
> > > > >
> > > > > Hi,
> > > > >  
> > > > > > The Armv8-R AArch64 profile does not support the EL3 exception level.
> > > > > > The Armv8-R AArch64 profile allows for an (optional) VMSAv8-64
> > > > > > MMU at EL1, which allows to run off-the-shelf Linux. However EL2
> > > > > > only supports a PMSA, which is not supported by Linux, so we
> > > > > > need to drop into EL1 before entering the kernel.
> > > > > >
> > > > > > The boot sequence is:
> > > > > > If CurrentEL == EL3, then goto EL3 initialisation and drop to lower EL
> > > > > >   before entering the kernel.
> > > > > > If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf (Armv8-R  
> > aarch64),  
> > > > > >   then goto Armv8-R AArch64 initialisation and drop to EL1 before
> > > > > >   entering the kernel.
> > > > > > Else, no initialisation and keep the current EL before entering the
> > > > > >   kernel.
> > > > > >
> > > > > > Signed-off-by: Jaxson Han <jaxson.han@arm.com>
> > > > > > ---
> > > > > >  arch/aarch64/boot.S | 51
> > > > > > +++++++++++++++++++++++++++++++++++++++++++++
> > > > > >  1 file changed, 51 insertions(+)
> > > > > >
> > > > > > diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index
> > > > > > f7dbf3f..6961a2a 100644
> > > > > > --- a/arch/aarch64/boot.S
> > > > > > +++ b/arch/aarch64/boot.S
> > > > > > @@ -25,16 +25,22 @@ _start:
> > > > > >  	 * Boot sequence
> > > > > >  	 * If CurrentEL == EL3, then goto EL3 initialisation and drop to
> > > > > >  	 *   lower EL before entering the kernel.
> > > > > > +	 * If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf,  
> > then goto  
> > > > > > +	 *   Armv8-R AArch64 initialisation and drop to EL1 before
> > > > > > +	 *   entering the kernel.
> > > > > >  	 * Else, no initialisation and keep the current EL before
> > > > > >  	 *   entering the kernel.
> > > > > >  	 */
> > > > > >  	mrs	x0, CurrentEL
> > > > > >  	cmp	x0, #CURRENTEL_EL3
> > > > > >  	beq	el3_init
> > > > > > +	cmp	x0, #CURRENTEL_EL2
> > > > > > +	beq	el2_init  
> > > > >
> > > > > nitpick: I tend to compare against EL2, then use b.gt for EL3,
> > > > > b.lt for
> > > > > EL1 and b.eq for EL2 code. Saves you an extra cmp here.  
> > > >
> > > > Exactly, I will. Thanks!
> > > >  
> > > > >  
> > > > > >  	/*
> > > > > >  	 * We stay in the current EL for entering the kernel
> > > > > >  	 */
> > > > > > +keep_el:
> > > > > >  	mov	w0, #1
> > > > > >  	ldr	x1, =flag_keep_el
> > > > > >  	str	w0, [x1]
> > > > > > @@ -112,6 +118,43 @@ el3_init:
> > > > > >  	str	w0, [x1]
> > > > > >  	b	el_max_init
> > > > > >
> > > > > > +	/*
> > > > > > +	 * EL2 Armv8-R AArch64 initialisation
> > > > > > +	 */
> > > > > > +el2_init:
> > > > > > +	/* Detect Armv8-R AArch64 */
> > > > > > +	mrs	x1, id_aa64mmfr0_el1
> > > > > > +	ubfx	x1, x1, #48, #4			// MSA
> > > > > > +	/* 0xf means Armv8-R AArch64 */
> > > > > > +	cmp	x1, 0xf
> > > > > > +	bne	keep_el  
> > > > >
> > > > > Don't we need to also check bits[55:52], to have at least 0b0010?
> > > > > IIUC the support for VMSA in EL1&0 is optional, and should be
> > > > > checked before we proceed? VTCR_EL2[31] can only be set in the  
> > 0b0010 case.  
> > > >
> > > > Yes, it should be checked, I will add it.
> > > >  
> > > > >  
> > > > > > +
> > > > > > +	mrs	x0, midr_el1
> > > > > > +	msr	vpidr_el2, x0
> > > > > > +
> > > > > > +	mrs	x0, mpidr_el1
> > > > > > +	msr	vmpidr_el2, x0
> > > > > > +
> > > > > > +	mov	x0, #(1 << 31)			// VTCR_MSA:  
> > VMSAv8-64  
> > > > > support  
> > > > > > +	msr	vtcr_el2, x0
> > > > > > +
> > > > > > +	/* Enable pointer authentication if present */
> > > > > > +	mrs	x1, id_aa64isar1_el1
> > > > > > +	ldr	x2, =(((0xff) << 24) | (0xff << 4))  
> > > > >
> > > > > Each feature only holds four bits, so the mask you shift should be 0xf.  
> > > >
> > > > Yes, I will fix.
> > > >  
> > > > >  
> > > > > > +	and	x1, x1, x2
> > > > > > +	cbz	x1, 1f
> > > > > > +
> > > > > > +	mrs	x0, hcr_el2  
> > > > >
> > > > > Shouldn't we force HCR_EL2, instead of modifying it? Just to make
> > > > > sure nothing unexpected traps into EL2, which we don't handle very  
> > well?  
> > > > > So basically just set bit 31 (RES1), plus those two bits on top,
> > > > > if needed. But I also wonder about FIEN[47] and EnSCXT[53] ...  
> > > >
> > > > Right, we should force to set HCR_EL2. The API and APK is needed.
> > > > And I will also check if we need the FIEN[47] and EnSCXT[53].
> > > >
> > > > Thanks,
> > > > Jaxson
> > > >  
> > > > >
> > > > >
> > > > > Rest looks alright.
> > > > >
> > > > > Cheers,
> > > > > Andre
> > > > >  
> > > > > > +	orr	x0, x0, #(1 << 40)		// AP key enable
> > > > > > +	orr	x0, x0, #(1 << 41)		// AP insn enable
> > > > > > +	msr	hcr_el2, x0
> > > > > > +
> > > > > > +1:	isb
> > > > > > +	mov	w0, #SPSR_KERNEL_EL1
> > > > > > +	ldr	x1, =spsr_to_elx
> > > > > > +	str	w0, [x1]
> > > > > > +	b	el_max_init
> > > > > > +
> > > > > >  el_max_init:
> > > > > >  	ldr	x0, =CNTFRQ
> > > > > >  	msr	cntfrq_el0, x0
> > > > > > @@ -169,10 +212,18 @@ jump_kernel:
> > > > > >  	 */
> > > > > >  	bfi	x4, x19, #5, #1
> > > > > >
> > > > > > +	mrs	x5, CurrentEL
> > > > > > +	cmp	x5, #CURRENTEL_EL2
> > > > > > +	b.eq	1f
> > > > > > +
> > > > > >  	msr	elr_el3, x19
> > > > > >  	msr	spsr_el3, x4
> > > > > >  	eret
> > > > > >
> > > > > > +1:	msr	elr_el2, x19
> > > > > > +	msr	spsr_el2, x4
> > > > > > +	eret
> > > > > > +
> > > > > >  	.ltorg
> > > > > >
> > > > > >  	.data  
> > >  
> 


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RE: [boot-wrapper PATCH 5/5] aarch64: Introduce EL2 boot code for Armv8-R AArch64

[Jaxson Han]

Hi Andre,

> -----Original Message-----
> From: Andre Przywara <andre.przywara@arm.com>
> Sent: Tuesday, May 11, 2021 4:00 PM
> To: Jaxson Han <Jaxson.Han@arm.com>
> Cc: Mark Rutland <Mark.Rutland@arm.com>; linux-arm-
> kernel@lists.infradead.org; Wei Chen <Wei.Chen@arm.com>
> Subject: Re: [boot-wrapper PATCH 5/5] aarch64: Introduce EL2 boot code for
> Armv8-R AArch64
> 
> On Tue, 11 May 2021 02:03:32 +0000
> Jaxson Han <Jaxson.Han@arm.com> wrote:
> 
> Hi,
> 
> > > -----Original Message-----
> > > From: Andre Przywara <andre.przywara@arm.com>
> > > Sent: Monday, May 10, 2021 4:55 PM
> > > To: Jaxson Han <Jaxson.Han@arm.com>
> > > Cc: Mark Rutland <Mark.Rutland@arm.com>; linux-arm-
> > > kernel@lists.infradead.org; Wei Chen <Wei.Chen@arm.com>
> > > Subject: Re: [boot-wrapper PATCH 5/5] aarch64: Introduce EL2 boot
> > > code for Armv8-R AArch64
> > >
> > > On Mon, 10 May 2021 02:13:45 +0000
> > > Jaxson Han <Jaxson.Han@arm.com> wrote:
> > >
> > > > Hi Andre,
> > > >
> > > > Since GCC 11 has been released and GCC 11 supports the '
> > > > -march=armv8-r', we got a problem when compile the boot-wrapper
> with '
> > > -march=armv8-r':
> > > > | ../git/arch/aarch64/boot.S:71: Error: selected processor does
> > > > | not support
> > > system register name 'scr_el3'
> > > > | ../git/arch/aarch64/boot.S:73: Error: selected processor does
> > > > | not support
> > > system register name 'cptr_el3'
> > > > | ../git/arch/aarch64/boot.S:84: Error: selected processor does
> > > > | not support
> > > system register name 'mdcr_el3'
> > > > | ../git/arch/aarch64/boot.S:90: Error: selected processor does
> > > > | not support
> > > system register name 'cptr_el3'
> > > > | ../git/arch/aarch64/boot.S:92: Error: selected processor does
> > > > | not support
> > > system register name 'cptr_el3'
> > > > | ../git/arch/aarch64/boot.S:194: Error: selected processor does
> > > > | not
> > > support system register name 'elr_el3'
> > > > | ../git/arch/aarch64/boot.S:195: Error: selected processor does
> > > > | not
> > > support system register name 'spsr_el3'
> > > >
> > > > It seems we may need some #if macro to disable all _el3 registers,
> > > > but it will break our auto-detection (users should add more
> > > > compile/build
> > > parameter).
> > > > So, may I ask your suggestions? :)
> > >
> > > Why do you need that in the first place? I think your version worked
> > > without it? At least Ubuntu's 9.3.0 compiled it just fine.
> > > Or does GCC 11 complain about some v8-r specific registers and you
> > > need to add this armv8-r to let them pass, sacrificing all EL3 registers on
> the way?
> >
> > The problem comes from AIS yocto-bsp team. The reason they need this,
> > I think, may be that they want to test this new option for v8-r since
> > GCC 11 supports v8-r. Anyway, the current version works well. And I
> > agree it's neither necessary nor first priority to solve this problem
> > for boot-wrapper. But I think it's worth to discuss with you and see
> > your suggestions :)
> 
> Well, but each software package sets the stage for the compiler options it can
> or cannot accept. And since the boot-wrapper is still foremost a v8-A
> software, just compiling it with v8-r (or any other random switch) won't work.
> So it's just not valid to use that switch there - it's the task of the Makefile to
> set compiler options, any user choices have no guarantee of working anyway.

I got it. And we decided remove this option, because it's almost no gain.

> 
> And out of curiosity: what did you expect from using that option?

At the very beginning, maybe, expecting reorganization of v8-r registers,
or some optimizations?
But, since boot-wrapper does nothing but some inits, this option seems
useless totally.
So, we remove it.

> 
> > > One solution could be to move all accesses to v8-r registers into a
> > > separate file, and only assemble/compile this with the v8-r switch.
> > > But this sounds like some serious plumbing in the code base.
> > >
> > > What you could try as well is to use this "s3_0_c12_c12_5" like
> > > system register encoding style (this example is for ICC_SRE_EL1).
> > > The kernel uses this trick to avoid dependencies on gas knowing
> > > about all (new) system register names. Not sure if that is enough to trick
> gas into accepting it?
> > >
> > > Hope that helps.
> >
> > Yes, it helps! Based on this, we could easily evaluate the efforts:)
> 
> Did you change the EL3 registers this way? Was there any effect on the code?

No, I didn't. There's no need to try, I think, with so many efforts and no gain. :)

Thanks,
Andre

> 
> Cheers,
> Andre
> 
> > >
> > > Cheers,
> > > Andre
> > >
> > > >
> > > > Cheers,
> > > > Jaxson
> > > >
> > > > > -----Original Message-----
> > > > > From: Jaxson Han
> > > > > Sent: Wednesday, April 28, 2021 11:44 AM
> > > > > To: Andre Przywara <andre.przywara@arm.com>
> > > > > Cc: Mark Rutland <Mark.Rutland@arm.com>; linux-arm-
> > > > > kernel@lists.infradead.org; Wei Chen <Wei.Chen@arm.com>
> > > > > Subject: RE: [boot-wrapper PATCH 5/5] aarch64: Introduce EL2
> > > > > boot code for Armv8-R AArch64
> > > > >
> > > > > Hi Andre,
> > > > >
> > > > > > -----Original Message-----
> > > > > > From: Andre Przywara <andre.przywara@arm.com>
> > > > > > Sent: Monday, April 26, 2021 8:36 PM
> > > > > > To: Jaxson Han <Jaxson.Han@arm.com>
> > > > > > Cc: Mark Rutland <Mark.Rutland@arm.com>; linux-arm-
> > > > > > kernel@lists.infradead.org; Wei Chen <Wei.Chen@arm.com>
> > > > > > Subject: Re: [boot-wrapper PATCH 5/5] aarch64: Introduce EL2
> > > > > > boot code for Armv8-R AArch64
> > > > > >
> > > > > > On Tue, 20 Apr 2021 15:24:38 +0800 Jaxson Han
> > > > > > <jaxson.han@arm.com>
> > > > > > wrote:
> > > > > >
> > > > > > Hi,
> > > > > >
> > > > > > > The Armv8-R AArch64 profile does not support the EL3 exception
> level.
> > > > > > > The Armv8-R AArch64 profile allows for an (optional)
> > > > > > > VMSAv8-64 MMU at EL1, which allows to run off-the-shelf
> > > > > > > Linux. However EL2 only supports a PMSA, which is not
> > > > > > > supported by Linux, so we need to drop into EL1 before entering
> the kernel.
> > > > > > >
> > > > > > > The boot sequence is:
> > > > > > > If CurrentEL == EL3, then goto EL3 initialisation and drop to lower
> EL
> > > > > > >   before entering the kernel.
> > > > > > > If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf (Armv8-R
> > > aarch64),
> > > > > > >   then goto Armv8-R AArch64 initialisation and drop to EL1 before
> > > > > > >   entering the kernel.
> > > > > > > Else, no initialisation and keep the current EL before entering the
> > > > > > >   kernel.
> > > > > > >
> > > > > > > Signed-off-by: Jaxson Han <jaxson.han@arm.com>
> > > > > > > ---
> > > > > > >  arch/aarch64/boot.S | 51
> > > > > > > +++++++++++++++++++++++++++++++++++++++++++++
> > > > > > >  1 file changed, 51 insertions(+)
> > > > > > >
> > > > > > > diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index
> > > > > > > f7dbf3f..6961a2a 100644
> > > > > > > --- a/arch/aarch64/boot.S
> > > > > > > +++ b/arch/aarch64/boot.S
> > > > > > > @@ -25,16 +25,22 @@ _start:
> > > > > > >  	 * Boot sequence
> > > > > > >  	 * If CurrentEL == EL3, then goto EL3 initialisation and drop to
> > > > > > >  	 *   lower EL before entering the kernel.
> > > > > > > +	 * If CurrentEL == EL2 && id_aa64mmfr0_el1.MSA == 0xf,
> > > then goto
> > > > > > > +	 *   Armv8-R AArch64 initialisation and drop to EL1 before
> > > > > > > +	 *   entering the kernel.
> > > > > > >  	 * Else, no initialisation and keep the current EL before
> > > > > > >  	 *   entering the kernel.
> > > > > > >  	 */
> > > > > > >  	mrs	x0, CurrentEL
> > > > > > >  	cmp	x0, #CURRENTEL_EL3
> > > > > > >  	beq	el3_init
> > > > > > > +	cmp	x0, #CURRENTEL_EL2
> > > > > > > +	beq	el2_init
> > > > > >
> > > > > > nitpick: I tend to compare against EL2, then use b.gt for EL3,
> > > > > > b.lt for
> > > > > > EL1 and b.eq for EL2 code. Saves you an extra cmp here.
> > > > >
> > > > > Exactly, I will. Thanks!
> > > > >
> > > > > >
> > > > > > >  	/*
> > > > > > >  	 * We stay in the current EL for entering the kernel
> > > > > > >  	 */
> > > > > > > +keep_el:
> > > > > > >  	mov	w0, #1
> > > > > > >  	ldr	x1, =flag_keep_el
> > > > > > >  	str	w0, [x1]
> > > > > > > @@ -112,6 +118,43 @@ el3_init:
> > > > > > >  	str	w0, [x1]
> > > > > > >  	b	el_max_init
> > > > > > >
> > > > > > > +	/*
> > > > > > > +	 * EL2 Armv8-R AArch64 initialisation
> > > > > > > +	 */
> > > > > > > +el2_init:
> > > > > > > +	/* Detect Armv8-R AArch64 */
> > > > > > > +	mrs	x1, id_aa64mmfr0_el1
> > > > > > > +	ubfx	x1, x1, #48, #4			// MSA
> > > > > > > +	/* 0xf means Armv8-R AArch64 */
> > > > > > > +	cmp	x1, 0xf
> > > > > > > +	bne	keep_el
> > > > > >
> > > > > > Don't we need to also check bits[55:52], to have at least 0b0010?
> > > > > > IIUC the support for VMSA in EL1&0 is optional, and should be
> > > > > > checked before we proceed? VTCR_EL2[31] can only be set in the
> > > 0b0010 case.
> > > > >
> > > > > Yes, it should be checked, I will add it.
> > > > >
> > > > > >
> > > > > > > +
> > > > > > > +	mrs	x0, midr_el1
> > > > > > > +	msr	vpidr_el2, x0
> > > > > > > +
> > > > > > > +	mrs	x0, mpidr_el1
> > > > > > > +	msr	vmpidr_el2, x0
> > > > > > > +
> > > > > > > +	mov	x0, #(1 << 31)			// VTCR_MSA:
> > > VMSAv8-64
> > > > > > support
> > > > > > > +	msr	vtcr_el2, x0
> > > > > > > +
> > > > > > > +	/* Enable pointer authentication if present */
> > > > > > > +	mrs	x1, id_aa64isar1_el1
> > > > > > > +	ldr	x2, =(((0xff) << 24) | (0xff << 4))
> > > > > >
> > > > > > Each feature only holds four bits, so the mask you shift should be
> 0xf.
> > > > >
> > > > > Yes, I will fix.
> > > > >
> > > > > >
> > > > > > > +	and	x1, x1, x2
> > > > > > > +	cbz	x1, 1f
> > > > > > > +
> > > > > > > +	mrs	x0, hcr_el2
> > > > > >
> > > > > > Shouldn't we force HCR_EL2, instead of modifying it? Just to
> > > > > > make sure nothing unexpected traps into EL2, which we don't
> > > > > > handle very
> > > well?
> > > > > > So basically just set bit 31 (RES1), plus those two bits on
> > > > > > top, if needed. But I also wonder about FIEN[47] and EnSCXT[53] ...
> > > > >
> > > > > Right, we should force to set HCR_EL2. The API and APK is needed.
> > > > > And I will also check if we need the FIEN[47] and EnSCXT[53].
> > > > >
> > > > > Thanks,
> > > > > Jaxson
> > > > >
> > > > > >
> > > > > >
> > > > > > Rest looks alright.
> > > > > >
> > > > > > Cheers,
> > > > > > Andre
> > > > > >
> > > > > > > +	orr	x0, x0, #(1 << 40)		// AP key enable
> > > > > > > +	orr	x0, x0, #(1 << 41)		// AP insn enable
> > > > > > > +	msr	hcr_el2, x0
> > > > > > > +
> > > > > > > +1:	isb
> > > > > > > +	mov	w0, #SPSR_KERNEL_EL1
> > > > > > > +	ldr	x1, =spsr_to_elx
> > > > > > > +	str	w0, [x1]
> > > > > > > +	b	el_max_init
> > > > > > > +
> > > > > > >  el_max_init:
> > > > > > >  	ldr	x0, =CNTFRQ
> > > > > > >  	msr	cntfrq_el0, x0
> > > > > > > @@ -169,10 +212,18 @@ jump_kernel:
> > > > > > >  	 */
> > > > > > >  	bfi	x4, x19, #5, #1
> > > > > > >
> > > > > > > +	mrs	x5, CurrentEL
> > > > > > > +	cmp	x5, #CURRENTEL_EL2
> > > > > > > +	b.eq	1f
> > > > > > > +
> > > > > > >  	msr	elr_el3, x19
> > > > > > >  	msr	spsr_el3, x4
> > > > > > >  	eret
> > > > > > >
> > > > > > > +1:	msr	elr_el2, x19
> > > > > > > +	msr	spsr_el2, x4
> > > > > > > +	eret
> > > > > > > +
> > > > > > >  	.ltorg
> > > > > > >
> > > > > > >  	.data
> > > >
> >


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