* [PATCH v4] arm64: smccc: Support SMCCC v1.3 SVE register saving hint
@ 2021-05-24 10:42 Mark Brown
2021-05-26 21:31 ` Will Deacon
0 siblings, 1 reply; 7+ messages in thread
From: Mark Brown @ 2021-05-24 10:42 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon
Cc: Lorenzo Pieralisi, Sudeep Holla, Marc Zyngier, linux-arm-kernel,
Mark Brown, Ard Biesheuvel
SMCCC v1.2 requires that all SVE state be preserved over SMC calls which
introduces substantial overhead in the common case where there is no SVE
state in the registers. To avoid this SMCCC v1.3 introduces a flag which
allows the caller to say that there is no state that needs to be preserved
in the registers. Make use of this flag, setting it if the SMCCC version
indicates support for it and the TIF_ flags indicate that there is no live
SVE state in the registers, this avoids placing any constraints on when
SMCCC calls can be done or triggering extra saving and reloading of SVE
register state in the kernel.
This would be straightforward enough except for the rather entertaining
inline assembly we use to do SMCCC v1.1 calls to allow us to take advantage
of the limited number of registers it clobbers. Deal with this by having a
function which we call immediately before issuing the SMCCC call to make
our checks and set the flag. Using alternatives the overhead if SVE is
supported but not detected at runtime can be reduced to a single NOP.
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
---
v4:
- Also clobber cc as per suggestion from Ard.
- Rebase onto v5.13-rc3.
arch/arm64/kernel/smccc-call.S | 26 ++++++++++++++++++++++++++
drivers/firmware/smccc/smccc.c | 4 ++++
include/linux/arm-smccc.h | 24 ++++++++++++++++++++++--
3 files changed, 52 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kernel/smccc-call.S b/arch/arm64/kernel/smccc-call.S
index d62447964ed9..dbc96dbe2be2 100644
--- a/arch/arm64/kernel/smccc-call.S
+++ b/arch/arm64/kernel/smccc-call.S
@@ -7,8 +7,34 @@
#include <asm/asm-offsets.h>
#include <asm/assembler.h>
+#include <asm/thread_info.h>
+
+/*
+ * If we have SMCCC v1.3 and (as is likely) no SVE state in
+ * the registers then set the SMCCC hint bit to say there's no
+ * need to preserve it. Do this by directly adjusting the SMCCC
+ * function value which is already stored in x0 ready to be called.
+ */
+SYM_FUNC_START(__smccc_sve_check)
+
+ ldr_l x16, smccc_has_sve_hint
+ cbz x16, 2f
+
+ get_current_task x16
+ ldr x16, [x16, #TSK_TI_FLAGS]
+ tbnz x16, #TIF_FOREIGN_FPSTATE, 1f // Any live FP state?
+ tbnz x16, #TIF_SVE, 2f // Does that state include SVE?
+
+1: orr x0, x0, ARM_SMCCC_1_3_SVE_HINT
+
+2: ret
+SYM_FUNC_END(__smccc_sve_check)
+EXPORT_SYMBOL(__smccc_sve_check)
.macro SMCCC instr
+alternative_if ARM64_SVE
+ bl __smccc_sve_check
+alternative_else_nop_endif
\instr #0
ldr x4, [sp]
stp x0, x1, [x4, #ARM_SMCCC_RES_X0_OFFS]
diff --git a/drivers/firmware/smccc/smccc.c b/drivers/firmware/smccc/smccc.c
index 028f81d702cc..9f937b125ab0 100644
--- a/drivers/firmware/smccc/smccc.c
+++ b/drivers/firmware/smccc/smccc.c
@@ -15,6 +15,7 @@ static u32 smccc_version = ARM_SMCCC_VERSION_1_0;
static enum arm_smccc_conduit smccc_conduit = SMCCC_CONDUIT_NONE;
bool __ro_after_init smccc_trng_available = false;
+u64 __ro_after_init smccc_has_sve_hint = false;
void __init arm_smccc_version_init(u32 version, enum arm_smccc_conduit conduit)
{
@@ -22,6 +23,9 @@ void __init arm_smccc_version_init(u32 version, enum arm_smccc_conduit conduit)
smccc_conduit = conduit;
smccc_trng_available = smccc_probe_trng();
+ if (IS_ENABLED(CONFIG_ARM64_SVE) &&
+ smccc_version >= ARM_SMCCC_VERSION_1_3)
+ smccc_has_sve_hint = true;
}
enum arm_smccc_conduit arm_smccc_1_1_get_conduit(void)
diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h
index 6861489a1890..407610021a56 100644
--- a/include/linux/arm-smccc.h
+++ b/include/linux/arm-smccc.h
@@ -63,6 +63,9 @@
#define ARM_SMCCC_VERSION_1_0 0x10000
#define ARM_SMCCC_VERSION_1_1 0x10001
#define ARM_SMCCC_VERSION_1_2 0x10002
+#define ARM_SMCCC_VERSION_1_3 0x10003
+
+#define ARM_SMCCC_1_3_SVE_HINT 0x10000
#define ARM_SMCCC_VERSION_FUNC_ID \
ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \
@@ -216,6 +219,8 @@ u32 arm_smccc_get_version(void);
void __init arm_smccc_version_init(u32 version, enum arm_smccc_conduit conduit);
+extern u64 smccc_has_sve_hint;
+
/**
* struct arm_smccc_res - Result from SMC/HVC call
* @a0-a3 result values from registers 0 to 3
@@ -297,6 +302,20 @@ asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1,
#endif
+/* nVHE hypervisor doesn't have a current thread so needs separate checks */
+#if defined(CONFIG_ARM64_SVE) && !defined(__KVM_NVHE_HYPERVISOR__)
+
+#define SMCCC_SVE_CHECK ALTERNATIVE("nop \n", "bl __smccc_sve_check \n", \
+ ARM64_SVE)
+#define smccc_sve_clobbers "x16", "lr", "cc",
+
+#else
+
+#define SMCCC_SVE_CHECK
+#define smccc_sve_clobbers
+
+#endif
+
#define ___count_args(_0, _1, _2, _3, _4, _5, _6, _7, _8, x, ...) x
#define __count_args(...) \
@@ -364,7 +383,7 @@ asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1,
#define ___constraints(count) \
: __constraint_read_ ## count \
- : "memory"
+ : smccc_sve_clobbers "memory"
#define __constraints(count) ___constraints(count)
/*
@@ -379,7 +398,8 @@ asmlinkage void __arm_smccc_hvc(unsigned long a0, unsigned long a1,
register unsigned long r2 asm("r2"); \
register unsigned long r3 asm("r3"); \
__declare_args(__count_args(__VA_ARGS__), __VA_ARGS__); \
- asm volatile(inst "\n" : \
+ asm volatile(SMCCC_SVE_CHECK \
+ inst "\n" : \
"=r" (r0), "=r" (r1), "=r" (r2), "=r" (r3) \
__constraints(__count_args(__VA_ARGS__))); \
if (___res) \
--
2.20.1
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* Re: [PATCH v4] arm64: smccc: Support SMCCC v1.3 SVE register saving hint
2021-05-24 10:42 [PATCH v4] arm64: smccc: Support SMCCC v1.3 SVE register saving hint Mark Brown
@ 2021-05-26 21:31 ` Will Deacon
2021-05-26 23:02 ` Mark Brown
0 siblings, 1 reply; 7+ messages in thread
From: Will Deacon @ 2021-05-26 21:31 UTC (permalink / raw)
To: Mark Brown
Cc: Catalin Marinas, Lorenzo Pieralisi, Sudeep Holla, Marc Zyngier,
linux-arm-kernel, Ard Biesheuvel
On Mon, May 24, 2021 at 11:42:53AM +0100, Mark Brown wrote:
> SMCCC v1.2 requires that all SVE state be preserved over SMC calls which
> introduces substantial overhead in the common case where there is no SVE
> state in the registers. To avoid this SMCCC v1.3 introduces a flag which
> allows the caller to say that there is no state that needs to be preserved
> in the registers. Make use of this flag, setting it if the SMCCC version
> indicates support for it and the TIF_ flags indicate that there is no live
> SVE state in the registers, this avoids placing any constraints on when
> SMCCC calls can be done or triggering extra saving and reloading of SVE
> register state in the kernel.
>
> This would be straightforward enough except for the rather entertaining
> inline assembly we use to do SMCCC v1.1 calls to allow us to take advantage
> of the limited number of registers it clobbers. Deal with this by having a
> function which we call immediately before issuing the SMCCC call to make
> our checks and set the flag. Using alternatives the overhead if SVE is
> supported but not detected at runtime can be reduced to a single NOP.
>
> Signed-off-by: Mark Brown <broonie@kernel.org>
> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
> ---
>
> v4:
> - Also clobber cc as per suggestion from Ard.
> - Rebase onto v5.13-rc3.
>
> arch/arm64/kernel/smccc-call.S | 26 ++++++++++++++++++++++++++
> drivers/firmware/smccc/smccc.c | 4 ++++
> include/linux/arm-smccc.h | 24 ++++++++++++++++++++++--
> 3 files changed, 52 insertions(+), 2 deletions(-)
This fails to build for me:
Failed to build : cfc21861dca9 arm64: smccc: Support SMCCC v1.3 SVE register saving hint
Configuration: "defconfig-arm64-aarch64-linux-gnu-".
592 | arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_WORKAROUND_2, true, NULL);
| ^~~~~~~~~~~~~~~~~~~~
include/linux/arm-smccc.h:456:3: error: unknown register name ‘lr’ in ‘asm’
456 | asm volatile(SMCCC_SVE_CHECK \
| ^~~
include/linux/arm-smccc.h:478:32: note: in expansion of macro ‘__arm_smccc_1_1’
478 | #define arm_smccc_1_1_smc(...) __arm_smccc_1_1(SMCCC_SMC_INST, __VA_ARGS__)
| ^~~~~~~~~~~~~~~
include/linux/arm-smccc.h:531:4: note: in expansion of macro ‘arm_smccc_1_1_smc’
531 | arm_smccc_1_1_smc(__VA_ARGS__); \
| ^~~~~~~~~~~~~~~~~
arch/arm64/kernel/proton-pack.c:592:2: note: in expansion of macro ‘arm_smccc_1_1_invoke’
592 | arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_WORKAROUND_2, true, NULL);
| ^~~~~~~~~~~~~~~~~~~~
include/linux/arm-smccc.h:504:3: error: unknown register name ‘lr’ in ‘asm’
504 | asm ("" : __constraints(__count_args(__VA_ARGS__))); \
| ^~~
include/linux/arm-smccc.h:534:4: note: in expansion of macro ‘__fail_smccc_1_1’
534 | __fail_smccc_1_1(__VA_ARGS__); \
| ^~~~~~~~~~~~~~~~
arch/arm64/kernel/proton-pack.c:592:2: note: in expansion of macro ‘arm_smccc_1_1_invoke’
592 | arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_WORKAROUND_2, true, NULL);
| ^~~~~~~~~~~~~~~~~~~~
make[3]: *** [scripts/Makefile.build:272: arch/arm64/kernel/proton-pack.o] Error 1
Maybe need an x30 instead of lr?
Will
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v4] arm64: smccc: Support SMCCC v1.3 SVE register saving hint
2021-05-26 21:31 ` Will Deacon
@ 2021-05-26 23:02 ` Mark Brown
2021-05-27 8:09 ` Will Deacon
0 siblings, 1 reply; 7+ messages in thread
From: Mark Brown @ 2021-05-26 23:02 UTC (permalink / raw)
To: Will Deacon
Cc: Catalin Marinas, Lorenzo Pieralisi, Sudeep Holla, Marc Zyngier,
linux-arm-kernel, Ard Biesheuvel
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On Wed, May 26, 2021 at 10:31:29PM +0100, Will Deacon wrote:
> On Mon, May 24, 2021 at 11:42:53AM +0100, Mark Brown wrote:
> > drivers/firmware/smccc/smccc.c | 4 ++++
> > include/linux/arm-smccc.h | 24 ++++++++++++++++++++++--
> > 3 files changed, 52 insertions(+), 2 deletions(-)
> This fails to build for me:
Interesting... which toolchain are you using here?
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* Re: [PATCH v4] arm64: smccc: Support SMCCC v1.3 SVE register saving hint
2021-05-26 23:02 ` Mark Brown
@ 2021-05-27 8:09 ` Will Deacon
2021-05-27 8:18 ` Will Deacon
0 siblings, 1 reply; 7+ messages in thread
From: Will Deacon @ 2021-05-27 8:09 UTC (permalink / raw)
To: Mark Brown
Cc: Catalin Marinas, Lorenzo Pieralisi, Sudeep Holla, Marc Zyngier,
linux-arm-kernel, Ard Biesheuvel
On Thu, May 27, 2021 at 12:02:48AM +0100, Mark Brown wrote:
> On Wed, May 26, 2021 at 10:31:29PM +0100, Will Deacon wrote:
> > On Mon, May 24, 2021 at 11:42:53AM +0100, Mark Brown wrote:
>
> > > drivers/firmware/smccc/smccc.c | 4 ++++
> > > include/linux/arm-smccc.h | 24 ++++++++++++++++++++++--
> > > 3 files changed, 52 insertions(+), 2 deletions(-)
>
> > This fails to build for me:
>
> Interesting... which toolchain are you using here?
That's a good question.
/me digs into scripts
I think it's:
gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))
But note that we actually have a register alias in asm/assembler.h so
maybe just a missing include?
Will
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* Re: [PATCH v4] arm64: smccc: Support SMCCC v1.3 SVE register saving hint
2021-05-27 8:09 ` Will Deacon
@ 2021-05-27 8:18 ` Will Deacon
2021-05-31 5:52 ` Ard Biesheuvel
0 siblings, 1 reply; 7+ messages in thread
From: Will Deacon @ 2021-05-27 8:18 UTC (permalink / raw)
To: Mark Brown
Cc: Catalin Marinas, Lorenzo Pieralisi, Sudeep Holla, Marc Zyngier,
linux-arm-kernel, Ard Biesheuvel
On Thu, May 27, 2021 at 09:09:53AM +0100, Will Deacon wrote:
> On Thu, May 27, 2021 at 12:02:48AM +0100, Mark Brown wrote:
> > On Wed, May 26, 2021 at 10:31:29PM +0100, Will Deacon wrote:
> > > On Mon, May 24, 2021 at 11:42:53AM +0100, Mark Brown wrote:
> >
> > > > drivers/firmware/smccc/smccc.c | 4 ++++
> > > > include/linux/arm-smccc.h | 24 ++++++++++++++++++++++--
> > > > 3 files changed, 52 insertions(+), 2 deletions(-)
> >
> > > This fails to build for me:
> >
> > Interesting... which toolchain are you using here?
>
> That's a good question.
>
> /me digs into scripts
>
> I think it's:
>
> gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))
Duh, I suppose you're probably more interested in the assembler:
GNU assembler (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 2.33.1.20191209
Will
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v4] arm64: smccc: Support SMCCC v1.3 SVE register saving hint
2021-05-27 8:18 ` Will Deacon
@ 2021-05-31 5:52 ` Ard Biesheuvel
2021-06-01 12:45 ` Mark Brown
0 siblings, 1 reply; 7+ messages in thread
From: Ard Biesheuvel @ 2021-05-31 5:52 UTC (permalink / raw)
To: Will Deacon
Cc: Mark Brown, Catalin Marinas, Lorenzo Pieralisi, Sudeep Holla,
Marc Zyngier, Linux ARM
On Thu, 27 May 2021 at 10:18, Will Deacon <will@kernel.org> wrote:
>
> On Thu, May 27, 2021 at 09:09:53AM +0100, Will Deacon wrote:
> > On Thu, May 27, 2021 at 12:02:48AM +0100, Mark Brown wrote:
> > > On Wed, May 26, 2021 at 10:31:29PM +0100, Will Deacon wrote:
> > > > On Mon, May 24, 2021 at 11:42:53AM +0100, Mark Brown wrote:
> > >
> > > > > drivers/firmware/smccc/smccc.c | 4 ++++
> > > > > include/linux/arm-smccc.h | 24 ++++++++++++++++++++++--
> > > > > 3 files changed, 52 insertions(+), 2 deletions(-)
> > >
> > > > This fails to build for me:
> > >
> > > Interesting... which toolchain are you using here?
> >
> > That's a good question.
> >
> > /me digs into scripts
> >
> > I think it's:
> >
> > gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))
>
> Duh, I suppose you're probably more interested in the assembler:
>
> GNU assembler (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10)) 2.33.1.20191209
>
Didn't we run into this before?
IIRC, lr was never defined as a register alias for x30, which is why
we have the .req in 8f5c9037a55b. This caused breakage when the GNU
folks tried to add the lr alias, as the .req would be rejected now, so
they removed it again. (I might be misremembering, but something along
those lines did occur)
In summary, let's just use x30 in the clobber list and be done with it.
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* Re: [PATCH v4] arm64: smccc: Support SMCCC v1.3 SVE register saving hint
2021-05-31 5:52 ` Ard Biesheuvel
@ 2021-06-01 12:45 ` Mark Brown
0 siblings, 0 replies; 7+ messages in thread
From: Mark Brown @ 2021-06-01 12:45 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: Will Deacon, Catalin Marinas, Lorenzo Pieralisi, Sudeep Holla,
Marc Zyngier, Linux ARM
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On Mon, May 31, 2021 at 07:52:59AM +0200, Ard Biesheuvel wrote:
> In summary, let's just use x30 in the clobber list and be done with it.
Yeah, that's what I've done - I just wanted to reproduce the failure.
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2021-05-27 8:09 ` Will Deacon
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