[PATCH v2 0/4] imx8mp: Add media block control

[PATCH v2 0/4] imx8mp: Add media block control

[Laurent Pinchart]

Hello,

This patch series adds support for the MEDIA_BLK_CTRL of the i.MX8MP to
the imx8m-blk-ctrl driver, and integrates it in the i.MX8MP device tree.

The patches depend on v2 of the series "soc: imx: gpcv2: add PGC
control register indirection" from Lucas Stach [1]. For testing
convenience, a branch that includes the dependency, based on v5.17, is
available at [2].

The series starts with DT bindings (1/4) and driver support (2/4),
followed by addition of the MEDIAMIX power domains to the GPC DT node
(3/4) and finally the new DT node for the MEDIA_BLK_CTRL.

Changes since v1 are listed in changelogs in the individual patches.

The patches have been tested with with ISI on the i.MX8MP. The ISI
driver is still under development [3], and will be posted in the not too
distant future.

[1] https://lore.kernel.org/all/20220207192547.1997549-1-l.stach@pengutronix.de/
[2] https://git.linuxtv.org/pinchartl/media.git/log/?h=nxp/next/powerdomains
[3] https://gitlab.com/ideasonboard/nxp/linux/-/tree/pinchartl/v5.17/isi

Laurent Pinchart (1):
  arm64: dts: imx8mp: Add MEDIAMIX power domains

Paul Elder (3):
  dt-bindings: soc: Add i.MX8MP media block control DT bindings
  soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl
  arm64: dts: imx8mp: Add MEDIA_BLK_CTRL

 .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml    | 106 ++++++++++++++
 arch/arm64/boot/dts/freescale/imx8mp.dtsi     |  59 ++++++++
 drivers/soc/imx/imx8m-blk-ctrl.c              | 131 +++++++++++++++++-
 include/dt-bindings/power/imx8mp-power.h      |  11 ++
 4 files changed, 305 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml


base-commit: 256819fa3c09600675e31e9cb64a1a24574f02b2
-- 
Regards,

Laurent Pinchart


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[PATCH v2 1/4] dt-bindings: soc: Add i.MX8MP media block control DT bindings

[Laurent Pinchart]

From: Paul Elder <paul.elder@ideasonboard.com>

The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level
peripheral providing access to the NoC and ensuring proper power
sequencing of the peripherals within the MEDIAMIX domain. Add DT
bindings for it.

There is already a driver for block controls of other SoCs in the i.MX8M
family, so these bindings will expand upon that.

Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
Changes since v1:

- Lower reg size to 0x138
- Add ISP2 power domain and rename ISP to ISP1
---
 .../soc/imx/fsl,imx8mp-media-blk-ctrl.yaml    | 106 ++++++++++++++++++
 include/dt-bindings/power/imx8mp-power.h      |  11 ++
 2 files changed, 117 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml

diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
new file mode 100644
index 000000000000..b6808981de2f
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8MP Media Block Control
+
+maintainers:
+  - Paul Elder <paul.elder@ideasonboard.com>
+
+description:
+  The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
+  providing access to the NoC and ensuring proper power sequencing of the
+  peripherals within the MEDIAMIX domain.
+
+properties:
+  compatible:
+    items:
+      - const: fsl,imx8mp-media-blk-ctrl
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#power-domain-cells':
+    const: 1
+
+  power-domains:
+    maxItems: 11
+
+  power-domain-names:
+    items:
+      - const: bus
+      - const: mipi-dsi1
+      - const: mipi-csi1
+      - const: lcdif1
+      - const: isi
+      - const: mipi-csi2
+      - const: lcdif2
+      - const: isp2
+      - const: isp1
+      - const: dwe
+      - const: mipi-dsi2
+
+  clocks:
+    items:
+      - description: The APB clock
+      - description: The AXI clock
+      - description: The pixel clock for the first CSI2 receiver (aclk)
+      - description: The pixel clock for the second CSI2 receiver (aclk)
+      - description: The pixel clock for the first LCDIF (pix_clk)
+      - description: The pixel clock for the second LCDIF (pix_clk)
+      - description: The core clock for the ISP (clk)
+      - description: The MIPI-PHY reference clock used by DSI
+
+  clock-names:
+    items:
+      - const: apb
+      - const: axi
+      - const: cam1
+      - const: cam2
+      - const: disp1
+      - const: disp2
+      - const: isp
+      - const: phy
+
+required:
+  - compatible
+  - reg
+  - '#power-domain-cells'
+  - power-domains
+  - power-domain-names
+  - clocks
+  - clock-names
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/imx8mp-clock.h>
+    #include <dt-bindings/power/imx8mp-power.h>
+
+    media_blk_ctl: blk-ctl@32ec0000 {
+        compatible = "fsl,imx8mp-media-blk-ctrl", "syscon";
+        reg = <0x32ec0000 0x138>;
+        power-domains = <&mediamix_pd>, <&mipi_phy1_pd>, <&mipi_phy1_pd>,
+                        <&mediamix_pd>, <&mediamix_pd>, <&mipi_phy2_pd>,
+                        <&mediamix_pd>, <&ispdwp_pd>, <&ispdwp_pd>,
+                        <&ispdwp_pd>, <&mipi_phy2_pd>;
+        power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", "lcdif1", "isi",
+                             "mipi-csi2", "lcdif2", "isp2", "isp1", "dwe",
+                             "mipi-dsi2";
+        clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
+                 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+                 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
+                 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
+                 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
+                 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
+                 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
+                 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
+        clock-names = "apb", "axi", "cam1", "cam2", "disp1", "disp2",
+                      "isp", "phy";
+        #power-domain-cells = <1>;
+    };
+...
diff --git a/include/dt-bindings/power/imx8mp-power.h b/include/dt-bindings/power/imx8mp-power.h
index 9f90c40a2c6c..3f72bf7818fd 100644
--- a/include/dt-bindings/power/imx8mp-power.h
+++ b/include/dt-bindings/power/imx8mp-power.h
@@ -32,4 +32,15 @@
 #define IMX8MP_HSIOBLK_PD_PCIE				3
 #define IMX8MP_HSIOBLK_PD_PCIE_PHY			4
 
+#define IMX8MP_MEDIABLK_PD_MIPI_DSI_1			0
+#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_1			1
+#define IMX8MP_MEDIABLK_PD_LCDIF_1			2
+#define IMX8MP_MEDIABLK_PD_ISI				3
+#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_2			4
+#define IMX8MP_MEDIABLK_PD_LCDIF_2			5
+#define IMX8MP_MEDIABLK_PD_ISP2				6
+#define IMX8MP_MEDIABLK_PD_ISP1				7
+#define IMX8MP_MEDIABLK_PD_DWE				8
+#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2			9
+
 #endif
-- 
Regards,

Laurent Pinchart


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[PATCH v2 2/4] soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl

[Laurent Pinchart]

From: Paul Elder <paul.elder@ideasonboard.com>

Add the description for the i.MX8MP media blk-ctrl.

Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
Changes since v1:

- Add ISP2 power domain and rename ISP to ISP1
---
 drivers/soc/imx/imx8m-blk-ctrl.c | 131 ++++++++++++++++++++++++++++++-
 1 file changed, 129 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
index 511e74f0db8a..eb53468bf790 100644
--- a/drivers/soc/imx/imx8m-blk-ctrl.c
+++ b/drivers/soc/imx/imx8m-blk-ctrl.c
@@ -15,10 +15,11 @@
 
 #include <dt-bindings/power/imx8mm-power.h>
 #include <dt-bindings/power/imx8mn-power.h>
+#include <dt-bindings/power/imx8mp-power.h>
 
 #define BLK_SFT_RSTN	0x0
 #define BLK_CLK_EN	0x4
-#define BLK_MIPI_RESET_DIV	0x8 /* Mini/Nano DISPLAY_BLK_CTRL only */
+#define BLK_MIPI_RESET_DIV	0x8 /* Mini/Nano/Plus DISPLAY_BLK_CTRL only */
 
 struct imx8m_blk_ctrl_domain;
 
@@ -40,7 +41,7 @@ struct imx8m_blk_ctrl_domain_data {
 	u32 clk_mask;
 
 	/*
-	 * i.MX8M Mini and Nano have a third DISPLAY_BLK_CTRL register
+	 * i.MX8M Mini, Nano and Plus have a third DISPLAY_BLK_CTRL register
 	 * which is used to control the reset for the MIPI Phy.
 	 * Since it's only present in certain circumstances,
 	 * an if-statement should be used before setting and clearing this
@@ -589,6 +590,129 @@ static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = {
 	.num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data),
 };
 
+static int imx8mp_media_power_notifier(struct notifier_block *nb,
+				unsigned long action, void *data)
+{
+	struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
+						 power_nb);
+
+	if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
+		return NOTIFY_OK;
+
+	/* Enable bus clock and deassert bus reset */
+	regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8));
+	regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8));
+
+	/*
+	 * On power up we have no software backchannel to the GPC to
+	 * wait for the ADB handshake to happen, so we just delay for a
+	 * bit. On power down the GPC driver waits for the handshake.
+	 */
+	if (action == GENPD_NOTIFY_ON)
+		udelay(5);
+
+	return NOTIFY_OK;
+}
+
+/*
+ * From i.MX 8M Plus Applications Processor Reference Manual, Rev. 1,
+ * section 13.2.2, 13.2.3
+ * isp-ahb and dwe are not in Figure 13-5. Media BLK_CTRL Clocks
+ */
+static const struct imx8m_blk_ctrl_domain_data imx8mp_media_blk_ctl_domain_data[] = {
+	[IMX8MP_MEDIABLK_PD_MIPI_DSI_1] = {
+		.name = "mediablk-mipi-dsi-1",
+		.clk_names = (const char *[]){ "apb", "phy", },
+		.num_clks = 2,
+		.gpc_name = "mipi-dsi1",
+		.rst_mask = BIT(0) | BIT(1),
+		.clk_mask = BIT(0) | BIT(1),
+		.mipi_phy_rst_mask = BIT(17),
+	},
+	[IMX8MP_MEDIABLK_PD_MIPI_CSI2_1] = {
+		.name = "mediablk-mipi-csi2-1",
+		.clk_names = (const char *[]){ "apb", "cam1" },
+		.num_clks = 2,
+		.gpc_name = "mipi-csi1",
+		.rst_mask = BIT(2) | BIT(3),
+		.clk_mask = BIT(2) | BIT(3),
+		.mipi_phy_rst_mask = BIT(16),
+	},
+	[IMX8MP_MEDIABLK_PD_LCDIF_1] = {
+		.name = "mediablk-lcdif-1",
+		.clk_names = (const char *[]){ "disp1", "apb", "axi", },
+		.num_clks = 3,
+		.gpc_name = "lcdif1",
+		.rst_mask = BIT(4) | BIT(5) | BIT(23),
+		.clk_mask = BIT(4) | BIT(5) | BIT(23),
+	},
+	[IMX8MP_MEDIABLK_PD_ISI] = {
+		.name = "mediablk-isi",
+		.clk_names = (const char *[]){ "axi", "apb" },
+		.num_clks = 2,
+		.gpc_name = "isi",
+		.rst_mask = BIT(6) | BIT(7),
+		.clk_mask = BIT(6) | BIT(7),
+	},
+	[IMX8MP_MEDIABLK_PD_MIPI_CSI2_2] = {
+		.name = "mediablk-mipi-csi2-2",
+		.clk_names = (const char *[]){ "apb", "cam2" },
+		.num_clks = 2,
+		.gpc_name = "mipi-csi2",
+		.rst_mask = BIT(9) | BIT(10),
+		.clk_mask = BIT(9) | BIT(10),
+		.mipi_phy_rst_mask = BIT(30),
+	},
+	[IMX8MP_MEDIABLK_PD_LCDIF_2] = {
+		.name = "mediablk-lcdif-2",
+		.clk_names = (const char *[]){ "disp1", "apb", "axi", },
+		.num_clks = 3,
+		.gpc_name = "lcdif2",
+		.rst_mask = BIT(11) | BIT(12) | BIT(24),
+		.clk_mask = BIT(11) | BIT(12) | BIT(24),
+	},
+	[IMX8MP_MEDIABLK_PD_ISP2] = {
+		.name = "mediablk-isp2",
+		.clk_names = (const char *[]){ "isp", "axi", "apb" },
+		.num_clks = 3,
+		.gpc_name = "isp2",
+		.rst_mask = BIT(13) | BIT(14) | BIT(15),
+		.clk_mask = BIT(13) | BIT(14) | BIT(15),
+	},
+	[IMX8MP_MEDIABLK_PD_ISP1] = {
+		.name = "mediablk-isp1",
+		.clk_names = (const char *[]){ "isp", "axi", "apb" },
+		.num_clks = 3,
+		.gpc_name = "isp1",
+		.rst_mask = BIT(16) | BIT(17) | BIT(18),
+		.clk_mask = BIT(16) | BIT(17) | BIT(18),
+	},
+	[IMX8MP_MEDIABLK_PD_DWE] = {
+		.name = "mediablk-dwe",
+		.clk_names = (const char *[]){ "axi", "apb" },
+		.num_clks = 2,
+		.gpc_name = "dwe",
+		.rst_mask = BIT(19) | BIT(20) | BIT(21),
+		.clk_mask = BIT(19) | BIT(20) | BIT(21),
+	},
+	[IMX8MP_MEDIABLK_PD_MIPI_DSI_2] = {
+		.name = "mediablk-mipi-dsi-2",
+		.clk_names = (const char *[]){ "phy", },
+		.num_clks = 1,
+		.gpc_name = "mipi-dsi2",
+		.rst_mask = BIT(22),
+		.clk_mask = BIT(22),
+		.mipi_phy_rst_mask = BIT(29),
+	},
+};
+
+static const struct imx8m_blk_ctrl_data imx8mp_media_blk_ctl_dev_data = {
+	.max_reg = 0x138,
+	.power_notifier_fn = imx8mp_media_power_notifier,
+	.domains = imx8mp_media_blk_ctl_domain_data,
+	.num_domains = ARRAY_SIZE(imx8mp_media_blk_ctl_domain_data),
+};
+
 static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
 	{
 		.compatible = "fsl,imx8mm-vpu-blk-ctrl",
@@ -599,6 +723,9 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
 	}, {
 		.compatible = "fsl,imx8mn-disp-blk-ctrl",
 		.data = &imx8mn_disp_blk_ctl_dev_data
+	}, {
+		.compatible = "fsl,imx8mp-media-blk-ctrl",
+		.data = &imx8mp_media_blk_ctl_dev_data
 	}, {
 		/* Sentinel */
 	}
-- 
Regards,

Laurent Pinchart


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[PATCH v2 3/4] arm64: dts: imx8mp: Add MEDIAMIX power domains

[Laurent Pinchart]

Add the power domains related to the MEDIAMIX to the GPC.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 26 +++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index b40a5646f205..b440f22e03e5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -488,6 +488,11 @@ pgc {
 					#address-cells = <1>;
 					#size-cells = <0>;
 
+					pgc_mipi_phy1: power-domain@0 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
+					};
+
 					pgc_pcie_phy: power-domain@1 {
 						#power-domain-cells = <0>;
 						reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
@@ -530,6 +535,21 @@ pgc_gpu3d: power-domain@9 {
 						power-domains = <&pgc_gpumix>;
 					};
 
+					pgc_mediamix: power-domain@10 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
+						clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+							 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+						assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+								  <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+						assigned-clock-rates = <500000000>, <200000000>;
+					};
+
+					pgc_mipi_phy2: power-domain@16 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
+					};
+
 					pgc_hsiomix: power-domains@17 {
 						#power-domain-cells = <0>;
 						reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
@@ -539,6 +559,12 @@ pgc_hsiomix: power-domains@17 {
 						assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
 						assigned-clock-rates = <500000000>;
 					};
+
+					pgc_ispdwp: power-domain@18 {
+						#power-domain-cells = <0>;
+						reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
+						clocks = <&clk IMX8MP_CLK_MEDIA_ISP_DIV>;
+					};
 				};
 			};
 		};
-- 
Regards,

Laurent Pinchart


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[PATCH v2 4/4] arm64: dts: imx8mp: Add MEDIA_BLK_CTRL

[Laurent Pinchart]

From: Paul Elder <paul.elder@ideasonboard.com>

Add a DT node for the MEDIA_BLK_CTRL, which provides power domains for
the camera and display devices.

Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 33 +++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index b440f22e03e5..f61ad0a1248a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -991,6 +991,39 @@ aips4: bus@32c00000 {
 			#size-cells = <1>;
 			ranges;
 
+			media_blk_ctrl: blk-ctrl@32ec0000 {
+				compatible = "fsl,imx8mp-media-blk-ctrl",
+					     "syscon";
+				reg = <0x32ec0000 0x10000>;
+				power-domains = <&pgc_mediamix>,
+						<&pgc_mipi_phy1>,
+						<&pgc_mipi_phy1>,
+						<&pgc_mediamix>,
+						<&pgc_mediamix>,
+						<&pgc_mipi_phy2>,
+						<&pgc_mediamix>,
+						<&pgc_ispdwp>,
+						<&pgc_ispdwp>,
+						<&pgc_ispdwp>,
+						<&pgc_mipi_phy2>;
+				power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
+						     "lcdif1", "isi", "mipi-csi2",
+						     "lcdif2", "isp2", "isp1", "dwe",
+						     "mipi-dsi2";
+				clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
+					 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
+				clock-names = "apb", "axi", "cam1", "cam2",
+					      "disp1", "disp2", "isp", "phy";
+
+				#power-domain-cells = <1>;
+			};
+
 			hsio_blk_ctrl: blk-ctrl@32f10000 {
 				compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
 				reg = <0x32f10000 0x24>;
-- 
Regards,

Laurent Pinchart


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Re: [PATCH v2 1/4] dt-bindings: soc: Add i.MX8MP media block control DT bindings

[Marek Vasut]

On 3/22/22 20:03, Laurent Pinchart wrote:
> From: Paul Elder <paul.elder@ideasonboard.com>
> 
> The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level
> peripheral providing access to the NoC and ensuring proper power
> sequencing of the peripherals within the MEDIAMIX domain. Add DT
> bindings for it.
> 
> There is already a driver for block controls of other SoCs in the i.MX8M
> family, so these bindings will expand upon that.
> 
> Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

Reviewed-by: Marek Vasut <marex@denx.de>

[...]

> +        power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", "lcdif1", "isi",
> +                             "mipi-csi2", "lcdif2", "isp2", "isp1", "dwe",
> +                             "mipi-dsi2";

Nit, I cannot say I'm a big fan of calling the power domain "mipi-csi1" 
and "mipi-csi2", they are both MIPI CSI2, except there are two of them 
CSI2 (#1 and #2).

Maybe mipi-csi2-1 and mipi-csi2-2 would be better ? DTTO for the LCDIF, 
where we have lcdifv3 and then mx8mp lcdifv3 and eventually we will have 
power domain for lcdif #3 instance in this SoC in hdmimix, so maybe some 
lcdif-1/lcdif-2 would be a better name ?

[...]

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Re: [PATCH v2 2/4] soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl

[Marek Vasut]

On 3/22/22 20:03, Laurent Pinchart wrote:
> From: Paul Elder <paul.elder@ideasonboard.com>
> 
> Add the description for the i.MX8MP media blk-ctrl.
> 
> Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

Reviewed-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de> # MX8MP LCDIF #1

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Re: [PATCH v2 3/4] arm64: dts: imx8mp: Add MEDIAMIX power domains

[Marek Vasut]

On 3/22/22 20:03, Laurent Pinchart wrote:
> Add the power domains related to the MEDIAMIX to the GPC.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
>   arch/arm64/boot/dts/freescale/imx8mp.dtsi | 26 +++++++++++++++++++++++
>   1 file changed, 26 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index b40a5646f205..b440f22e03e5 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -488,6 +488,11 @@ pgc {
>   					#address-cells = <1>;
>   					#size-cells = <0>;
>   
> +					pgc_mipi_phy1: power-domain@0 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;

Shouldn't there be this here ?

power-domains = <&pgc_mediamix>;

> +					};
> +
>   					pgc_pcie_phy: power-domain@1 {
>   						#power-domain-cells = <0>;
>   						reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
> @@ -530,6 +535,21 @@ pgc_gpu3d: power-domain@9 {
>   						power-domains = <&pgc_gpumix>;
>   					};
>   
> +					pgc_mediamix: power-domain@10 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
> +						clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> +							 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> +						assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> +								  <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> +						assigned-clock-rates = <500000000>, <200000000>;
> +					};
> +
> +					pgc_mipi_phy2: power-domain@16 {
> +						#power-domain-cells = <0>;
> +						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;

Here too ?

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Re: [PATCH v2 1/4] dt-bindings: soc: Add i.MX8MP media block control DT bindings

[Laurent Pinchart]

Hi Marek,

On Tue, Mar 22, 2022 at 10:29:56PM +0100, Marek Vasut wrote:
> On 3/22/22 20:03, Laurent Pinchart wrote:
> > From: Paul Elder <paul.elder@ideasonboard.com>
> > 
> > The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level
> > peripheral providing access to the NoC and ensuring proper power
> > sequencing of the peripherals within the MEDIAMIX domain. Add DT
> > bindings for it.
> > 
> > There is already a driver for block controls of other SoCs in the i.MX8M
> > family, so these bindings will expand upon that.
> > 
> > Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> 
> Reviewed-by: Marek Vasut <marex@denx.de>
> 
> [...]
> 
> > +        power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", "lcdif1", "isi",
> > +                             "mipi-csi2", "lcdif2", "isp2", "isp1", "dwe",
> > +                             "mipi-dsi2";
> 
> Nit, I cannot say I'm a big fan of calling the power domain "mipi-csi1" 
> and "mipi-csi2", they are both MIPI CSI2, except there are two of them 
> CSI2 (#1 and #2).
> 
> Maybe mipi-csi2-1 and mipi-csi2-2 would be better ? DTTO for the LCDIF, 
> where we have lcdifv3 and then mx8mp lcdifv3 and eventually we will have 
> power domain for lcdif #3 instance in this SoC in hdmimix, so maybe some 
> lcdif-1/lcdif-2 would be a better name ?

The names come from the reference manual, at least the ones for the
second instance. We have, for instance, SFT_EN_MIPI_CSI_PCLK_RESETN and
SFT_EN_MIPI_CSI2_PCLK_RESETN. Same for DSI and LCDIF, there's DSI and
DSI2, and LCDIF and LCDIF2. The "1" suffix has been added for clarity.

This is a bit bikeshedding territory as I expect the DT node for the
media-blk-ctrl to be written once and never be touched again, so if
anyone feels strongly about using better names (whatever those better
names would be), I don't mind much.

I can submit a v3 once a consensus emerges.

-- 
Regards,

Laurent Pinchart

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Re: [PATCH v2 2/4] soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl

[Laurent Pinchart]

On Tue, Mar 22, 2022 at 10:30:56PM +0100, Marek Vasut wrote:
> On 3/22/22 20:03, Laurent Pinchart wrote:
> > From: Paul Elder <paul.elder@ideasonboard.com>
> > 
> > Add the description for the i.MX8MP media blk-ctrl.
> > 
> > Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
> > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> 
> Reviewed-by: Marek Vasut <marex@denx.de>
> Tested-by: Marek Vasut <marex@denx.de> # MX8MP LCDIF #1

Thank you for testing, that's appreciated.

-- 
Regards,

Laurent Pinchart

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Re: [PATCH v2 1/4] dt-bindings: soc: Add i.MX8MP media block control DT bindings

[Marek Vasut]

On 3/22/22 22:57, Laurent Pinchart wrote:
> Hi Marek,
> 
> On Tue, Mar 22, 2022 at 10:29:56PM +0100, Marek Vasut wrote:
>> On 3/22/22 20:03, Laurent Pinchart wrote:
>>> From: Paul Elder <paul.elder@ideasonboard.com>
>>>
>>> The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level
>>> peripheral providing access to the NoC and ensuring proper power
>>> sequencing of the peripherals within the MEDIAMIX domain. Add DT
>>> bindings for it.
>>>
>>> There is already a driver for block controls of other SoCs in the i.MX8M
>>> family, so these bindings will expand upon that.
>>>
>>> Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
>>> Reviewed-by: Rob Herring <robh@kernel.org>
>>> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
>>> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
>>
>> Reviewed-by: Marek Vasut <marex@denx.de>
>>
>> [...]
>>
>>> +        power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", "lcdif1", "isi",
>>> +                             "mipi-csi2", "lcdif2", "isp2", "isp1", "dwe",
>>> +                             "mipi-dsi2";
>>
>> Nit, I cannot say I'm a big fan of calling the power domain "mipi-csi1"
>> and "mipi-csi2", they are both MIPI CSI2, except there are two of them
>> CSI2 (#1 and #2).
>>
>> Maybe mipi-csi2-1 and mipi-csi2-2 would be better ? DTTO for the LCDIF,
>> where we have lcdifv3 and then mx8mp lcdifv3 and eventually we will have
>> power domain for lcdif #3 instance in this SoC in hdmimix, so maybe some
>> lcdif-1/lcdif-2 would be a better name ?
> 
> The names come from the reference manual, at least the ones for the
> second instance. We have, for instance, SFT_EN_MIPI_CSI_PCLK_RESETN and
> SFT_EN_MIPI_CSI2_PCLK_RESETN. Same for DSI and LCDIF, there's DSI and
> DSI2, and LCDIF and LCDIF2. The "1" suffix has been added for clarity.
> 
> This is a bit bikeshedding territory as I expect the DT node for the
> media-blk-ctrl to be written once and never be touched again, so if
> anyone feels strongly about using better names (whatever those better
> names would be), I don't mind much.
> 
> I can submit a v3 once a consensus emerges.

I don't feel strongly about it, I just wanted to point it out.
Let's wait for the others' opinions.

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Re: [PATCH v2 3/4] arm64: dts: imx8mp: Add MEDIAMIX power domains

[Laurent Pinchart]

Hi Marek,

On Tue, Mar 22, 2022 at 10:31:59PM +0100, Marek Vasut wrote:
> On 3/22/22 20:03, Laurent Pinchart wrote:
> > Add the power domains related to the MEDIAMIX to the GPC.
> > 
> > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > ---
> >   arch/arm64/boot/dts/freescale/imx8mp.dtsi | 26 +++++++++++++++++++++++
> >   1 file changed, 26 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > index b40a5646f205..b440f22e03e5 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > @@ -488,6 +488,11 @@ pgc {
> >   					#address-cells = <1>;
> >   					#size-cells = <0>;
> >   
> > +					pgc_mipi_phy1: power-domain@0 {
> > +						#power-domain-cells = <0>;
> > +						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
> 
> Shouldn't there be this here ?
> 
> power-domains = <&pgc_mediamix>;

I recall Lucas telling me it wasn't needed, and was instead handled
internally in the gpcv2 driver, due to sequencing requirements, but I
don't recall the details.

> > +					};
> > +
> >   					pgc_pcie_phy: power-domain@1 {
> >   						#power-domain-cells = <0>;
> >   						reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
> > @@ -530,6 +535,21 @@ pgc_gpu3d: power-domain@9 {
> >   						power-domains = <&pgc_gpumix>;
> >   					};
> >   
> > +					pgc_mediamix: power-domain@10 {
> > +						#power-domain-cells = <0>;
> > +						reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
> > +						clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> > +							 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> > +						assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> > +								  <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> > +						assigned-clock-rates = <500000000>, <200000000>;
> > +					};
> > +
> > +					pgc_mipi_phy2: power-domain@16 {
> > +						#power-domain-cells = <0>;
> > +						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
> 
> Here too ?

-- 
Regards,

Laurent Pinchart

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Re: [PATCH v2 3/4] arm64: dts: imx8mp: Add MEDIAMIX power domains

[Lucas Stach]

Am Mittwoch, dem 23.03.2022 um 00:02 +0200 schrieb Laurent Pinchart:
> Hi Marek,
> 
> On Tue, Mar 22, 2022 at 10:31:59PM +0100, Marek Vasut wrote:
> > On 3/22/22 20:03, Laurent Pinchart wrote:
> > > Add the power domains related to the MEDIAMIX to the GPC.
> > > 
> > > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > > ---
> > >   arch/arm64/boot/dts/freescale/imx8mp.dtsi | 26 +++++++++++++++++++++++
> > >   1 file changed, 26 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > index b40a5646f205..b440f22e03e5 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > @@ -488,6 +488,11 @@ pgc {
> > >   					#address-cells = <1>;
> > >   					#size-cells = <0>;
> > >   
> > > +					pgc_mipi_phy1: power-domain@0 {
> > > +						#power-domain-cells = <0>;
> > > +						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
> > 
> > Shouldn't there be this here ?
> > 
> > power-domains = <&pgc_mediamix>;
> 
> I recall Lucas telling me it wasn't needed, and was instead handled
> internally in the gpcv2 driver, due to sequencing requirements, but I
> don't recall the details.

It's not handled by the gpcv2 driver, but the blk-ctrl driver. The blk-
ctrl driver handles the sequencing requirements when powering up/down
the "bus" domain, in that case the mediamix domain. In fact there must
not be any direct connection between the domains in the GPC DT
description as that would cause the requirements for clock and reset
propagation to be violated.

Regards,
Lucas

> 
> > > +					};
> > > +
> > >   					pgc_pcie_phy: power-domain@1 {
> > >   						#power-domain-cells = <0>;
> > >   						reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
> > > @@ -530,6 +535,21 @@ pgc_gpu3d: power-domain@9 {
> > >   						power-domains = <&pgc_gpumix>;
> > >   					};
> > >   
> > > +					pgc_mediamix: power-domain@10 {
> > > +						#power-domain-cells = <0>;
> > > +						reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
> > > +						clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> > > +							 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> > > +						assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
> > > +								  <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
> > > +						assigned-clock-rates = <500000000>, <200000000>;
> > > +					};
> > > +
> > > +					pgc_mipi_phy2: power-domain@16 {
> > > +						#power-domain-cells = <0>;
> > > +						reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
> > 
> > Here too ?
> 



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