[PATCHv4 0/2] soc: qcom: llcc: Support chipsets that can write to llcc regs

[PATCHv4 0/2] soc: qcom: llcc: Support chipsets that can write to llcc regs

[Sai Prakash Ranjan]

Older chipsets may not be allowed to configure certain LLCC registers
as that is handled by the secure side software. However, this is not
the case for newer chipsets and they must configure these registers
according to the contents of the SCT table, while keeping in mind that
older targets may not have these capabilities. So add support to allow
such configuration of registers to enable capacity based allocation
and power collapse retention for capable chipsets.

Reason for choosing capacity based allocation rather than the default
way based allocation is because capacity based allocation allows more
finer grain partition and provides more flexibility in configuration.
As for the retention through power collapse, it has an advantage where
the cache hits are more when we wake up from power collapse although
it does burn more power but the exact power numbers are not known at
the moment.

Patch 1 is a cleanup to separate out llcc attribute configuration to
its own function.
Patch 2 adds support for chipsets capable of writing to llcc registers.

Changes in v4:
 * Separate out llcc attribute config to its own function (Stephen)
 * Pass qcom_llcc_config instead of a new llcc_drvdata property (Doug)

Changes in v3:
 * Drop separate table and use existing qcom_llcc_config (Doug)
 * More descriptive commit msg (Doug)
 * Directly set the config instead of '|=' (Doug)

Changes in v2:
 * Fix build errors reported by kernel test robot.

Isaac J. Manjarres (1):
  soc: qcom: llcc: Support chipsets that can write to llcc

Sai Prakash Ranjan (1):
  soc: qcom: llcc: Move attribute config to its own function

 drivers/soc/qcom/llcc-qcom.c | 100 +++++++++++++++++++++++------------
 1 file changed, 65 insertions(+), 35 deletions(-)


base-commit: 75894849c81ab9a2e9df2e8cf2f9c52035cd22a0
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[PATCHv4 1/2] soc: qcom: llcc: Move attribute config to its own function

[Sai Prakash Ranjan]

Cleanup qcom_llcc_cfg_program() by moving llcc attribute
configuration to a separate function of its own. Also
correct misspelled 'instance' caught by checkpatch.

Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
 drivers/soc/qcom/llcc-qcom.c | 75 ++++++++++++++++++++----------------
 1 file changed, 41 insertions(+), 34 deletions(-)

diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 429b5a60a1ba..60ee31842dea 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -318,14 +318,50 @@ size_t llcc_get_slice_size(struct llcc_slice_desc *desc)
 }
 EXPORT_SYMBOL_GPL(llcc_get_slice_size);
 
-static int qcom_llcc_cfg_program(struct platform_device *pdev)
+static int qcom_llcc_attr_cfg(const struct llcc_slice_config *table)
 {
-	int i;
 	u32 attr1_cfg;
 	u32 attr0_cfg;
 	u32 attr1_val;
 	u32 attr0_val;
 	u32 max_cap_cacheline;
+	int ret;
+
+	attr1_cfg = LLCC_TRP_ATTR1_CFGn(table->slice_id);
+	attr0_cfg = LLCC_TRP_ATTR0_CFGn(table->slice_id);
+
+	attr1_val = table->cache_mode;
+	attr1_val |= table->probe_target_ways << ATTR1_PROBE_TARGET_WAYS_SHIFT;
+	attr1_val |= table->fixed_size << ATTR1_FIXED_SIZE_SHIFT;
+	attr1_val |= table->priority << ATTR1_PRIORITY_SHIFT;
+
+	max_cap_cacheline = MAX_CAP_TO_BYTES(table->max_cap);
+
+	/* LLCC instances can vary for each target.
+	 * The SW writes to broadcast register which gets propagated
+	 * to each llcc instance (llcc0,.. llccN).
+	 * Since the size of the memory is divided equally amongst the
+	 * llcc instances, we need to configure the max cap accordingly.
+	 */
+	max_cap_cacheline = max_cap_cacheline / drv_data->num_banks;
+	max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT;
+	attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT;
+
+	attr0_val = table->res_ways & ATTR0_RES_WAYS_MASK;
+	attr0_val |= table->bonus_ways << ATTR0_BONUS_WAYS_SHIFT;
+
+	ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val);
+	if (ret)
+		return ret;
+
+	ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val);
+
+	return ret;
+}
+
+static int qcom_llcc_cfg_program(struct platform_device *pdev)
+{
+	int i;
 	u32 sz;
 	int ret = 0;
 	const struct llcc_slice_config *llcc_table;
@@ -335,45 +371,16 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev)
 	llcc_table = drv_data->cfg;
 
 	for (i = 0; i < sz; i++) {
-		attr1_cfg = LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id);
-		attr0_cfg = LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id);
-
-		attr1_val = llcc_table[i].cache_mode;
-		attr1_val |= llcc_table[i].probe_target_ways <<
-				ATTR1_PROBE_TARGET_WAYS_SHIFT;
-		attr1_val |= llcc_table[i].fixed_size <<
-				ATTR1_FIXED_SIZE_SHIFT;
-		attr1_val |= llcc_table[i].priority <<
-				ATTR1_PRIORITY_SHIFT;
-
-		max_cap_cacheline = MAX_CAP_TO_BYTES(llcc_table[i].max_cap);
-
-		/* LLCC instances can vary for each target.
-		 * The SW writes to broadcast register which gets propagated
-		 * to each llcc instace (llcc0,.. llccN).
-		 * Since the size of the memory is divided equally amongst the
-		 * llcc instances, we need to configure the max cap accordingly.
-		 */
-		max_cap_cacheline = max_cap_cacheline / drv_data->num_banks;
-		max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT;
-		attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT;
-
-		attr0_val = llcc_table[i].res_ways & ATTR0_RES_WAYS_MASK;
-		attr0_val |= llcc_table[i].bonus_ways << ATTR0_BONUS_WAYS_SHIFT;
-
-		ret = regmap_write(drv_data->bcast_regmap, attr1_cfg,
-					attr1_val);
-		if (ret)
-			return ret;
-		ret = regmap_write(drv_data->bcast_regmap, attr0_cfg,
-					attr0_val);
+		ret = qcom_llcc_attr_cfg(&llcc_table[i]);
 		if (ret)
 			return ret;
+
 		if (llcc_table[i].activate_on_init) {
 			desc.slice_id = llcc_table[i].slice_id;
 			ret = llcc_slice_activate(&desc);
 		}
 	}
+
 	return ret;
 }
 
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Re: [PATCHv4 1/2] soc: qcom: llcc: Move attribute config to its own function

[Stephen Boyd]

Quoting Sai Prakash Ranjan (2020-09-14 04:12:59)
> Cleanup qcom_llcc_cfg_program() by moving llcc attribute
> configuration to a separate function of its own. Also
> correct misspelled 'instance' caught by checkpatch.
> 
> Suggested-by: Stephen Boyd <swboyd@chromium.org>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
>  drivers/soc/qcom/llcc-qcom.c | 75 ++++++++++++++++++++----------------
>  1 file changed, 41 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index 429b5a60a1ba..60ee31842dea 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -318,14 +318,50 @@ size_t llcc_get_slice_size(struct llcc_slice_desc *desc)
>  }
>  EXPORT_SYMBOL_GPL(llcc_get_slice_size);
>  
> -static int qcom_llcc_cfg_program(struct platform_device *pdev)
> +static int qcom_llcc_attr_cfg(const struct llcc_slice_config *table)

Call it config? It's certainly not a table.

>  {
> -       int i;
>         u32 attr1_cfg;
>         u32 attr0_cfg;
>         u32 attr1_val;
>         u32 attr0_val;
>         u32 max_cap_cacheline;
> +       int ret;
> +
> +       attr1_cfg = LLCC_TRP_ATTR1_CFGn(table->slice_id);
> +       attr0_cfg = LLCC_TRP_ATTR0_CFGn(table->slice_id);

Can this move down to near where it is used?

> +
> +       attr1_val = table->cache_mode;
> +       attr1_val |= table->probe_target_ways << ATTR1_PROBE_TARGET_WAYS_SHIFT;
> +       attr1_val |= table->fixed_size << ATTR1_FIXED_SIZE_SHIFT;
> +       attr1_val |= table->priority << ATTR1_PRIORITY_SHIFT;
> +
> +       max_cap_cacheline = MAX_CAP_TO_BYTES(table->max_cap);
> +
> +       /* LLCC instances can vary for each target.

The /* should be on a line by itself.

> +        * The SW writes to broadcast register which gets propagated
> +        * to each llcc instance (llcc0,.. llccN).
> +        * Since the size of the memory is divided equally amongst the
> +        * llcc instances, we need to configure the max cap accordingly.
> +        */
> +       max_cap_cacheline = max_cap_cacheline / drv_data->num_banks;
> +       max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT;
> +       attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT;
> +
> +       attr0_val = table->res_ways & ATTR0_RES_WAYS_MASK;
> +       attr0_val |= table->bonus_ways << ATTR0_BONUS_WAYS_SHIFT;
> +
> +       ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val);
> +       if (ret)
> +               return ret;
> +
> +       ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val);
> +
> +       return ret;

return regmap_write(...)

> +}
> +
> +static int qcom_llcc_cfg_program(struct platform_device *pdev)
> +{
> +       int i;
>         u32 sz;
>         int ret = 0;
>         const struct llcc_slice_config *llcc_table;

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Re: [PATCHv4 1/2] soc: qcom: llcc: Move attribute config to its own function

[Sai Prakash Ranjan]

On 2020-09-15 00:14, Stephen Boyd wrote:
> Quoting Sai Prakash Ranjan (2020-09-14 04:12:59)
>> Cleanup qcom_llcc_cfg_program() by moving llcc attribute
>> configuration to a separate function of its own. Also
>> correct misspelled 'instance' caught by checkpatch.
>> 
>> Suggested-by: Stephen Boyd <swboyd@chromium.org>
>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>> ---
>>  drivers/soc/qcom/llcc-qcom.c | 75 
>> ++++++++++++++++++++----------------
>>  1 file changed, 41 insertions(+), 34 deletions(-)
>> 
>> diff --git a/drivers/soc/qcom/llcc-qcom.c 
>> b/drivers/soc/qcom/llcc-qcom.c
>> index 429b5a60a1ba..60ee31842dea 100644
>> --- a/drivers/soc/qcom/llcc-qcom.c
>> +++ b/drivers/soc/qcom/llcc-qcom.c
>> @@ -318,14 +318,50 @@ size_t llcc_get_slice_size(struct 
>> llcc_slice_desc *desc)
>>  }
>>  EXPORT_SYMBOL_GPL(llcc_get_slice_size);
>> 
>> -static int qcom_llcc_cfg_program(struct platform_device *pdev)
>> +static int qcom_llcc_attr_cfg(const struct llcc_slice_config *table)
> 
> Call it config? It's certainly not a table.
> 

Yes, will do.

>>  {
>> -       int i;
>>         u32 attr1_cfg;
>>         u32 attr0_cfg;
>>         u32 attr1_val;
>>         u32 attr0_val;
>>         u32 max_cap_cacheline;
>> +       int ret;
>> +
>> +       attr1_cfg = LLCC_TRP_ATTR1_CFGn(table->slice_id);
>> +       attr0_cfg = LLCC_TRP_ATTR0_CFGn(table->slice_id);
> 
> Can this move down to near where it is used?
> 

Sure.

>> +
>> +       attr1_val = table->cache_mode;
>> +       attr1_val |= table->probe_target_ways << 
>> ATTR1_PROBE_TARGET_WAYS_SHIFT;
>> +       attr1_val |= table->fixed_size << ATTR1_FIXED_SIZE_SHIFT;
>> +       attr1_val |= table->priority << ATTR1_PRIORITY_SHIFT;
>> +
>> +       max_cap_cacheline = MAX_CAP_TO_BYTES(table->max_cap);
>> +
>> +       /* LLCC instances can vary for each target.
> 
> The /* should be on a line by itself.
> 

This was there before I moved this hunk but I will fix it.

>> +        * The SW writes to broadcast register which gets propagated
>> +        * to each llcc instance (llcc0,.. llccN).
>> +        * Since the size of the memory is divided equally amongst the
>> +        * llcc instances, we need to configure the max cap 
>> accordingly.
>> +        */
>> +       max_cap_cacheline = max_cap_cacheline / drv_data->num_banks;
>> +       max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT;
>> +       attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT;
>> +
>> +       attr0_val = table->res_ways & ATTR0_RES_WAYS_MASK;
>> +       attr0_val |= table->bonus_ways << ATTR0_BONUS_WAYS_SHIFT;
>> +
>> +       ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, 
>> attr1_val);
>> +       if (ret)
>> +               return ret;
>> +
>> +       ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, 
>> attr0_val);
>> +
>> +       return ret;
> 
> return regmap_write(...)
> 

Ok done.

Thanks,
Sai

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[PATCHv4 2/2] soc: qcom: llcc: Support chipsets that can write to llcc regs

[Sai Prakash Ranjan]

From: "Isaac J. Manjarres" <isaacm@codeaurora.org>

Older chipsets may not be allowed to configure certain LLCC registers
as that is handled by the secure side software. However, this is not
the case for newer chipsets and they must configure these registers
according to the contents of the SCT table, while keeping in mind that
older targets may not have these capabilities. So add support to allow
such configuration of registers to enable capacity based allocation
and power collapse retention for capable chipsets.

Reason for choosing capacity based allocation rather than the default
way based allocation is because capacity based allocation allows more
finer grain partition and provides more flexibility in configuration.
As for the retention through power collapse, it has an advantage where
the cache hits are more when we wake up from power collapse although
it does burn more power but the exact power numbers are not known at
the moment.

Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
(saiprakash.ranjan@codeaurora.org: use existing config and reword commit msg)
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
 drivers/soc/qcom/llcc-qcom.c | 27 +++++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 60ee31842dea..6aedccff49bb 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -45,6 +45,9 @@
 #define LLCC_TRP_ATTR0_CFGn(n)        (0x21000 + SZ_8 * n)
 #define LLCC_TRP_ATTR1_CFGn(n)        (0x21004 + SZ_8 * n)
 
+#define LLCC_TRP_SCID_DIS_CAP_ALLOC   0x21f00
+#define LLCC_TRP_PCB_ACT              0x21f04
+
 #define BANK_OFFSET_STRIDE	      0x80000
 
 /**
@@ -89,6 +92,7 @@ struct llcc_slice_config {
 struct qcom_llcc_config {
 	const struct llcc_slice_config *sct_data;
 	int size;
+	bool need_llcc_cfg;
 };
 
 static const struct llcc_slice_config sc7180_data[] =  {
@@ -122,11 +126,13 @@ static const struct llcc_slice_config sdm845_data[] =  {
 static const struct qcom_llcc_config sc7180_cfg = {
 	.sct_data	= sc7180_data,
 	.size		= ARRAY_SIZE(sc7180_data),
+	.need_llcc_cfg	= true,
 };
 
 static const struct qcom_llcc_config sdm845_cfg = {
 	.sct_data	= sdm845_data,
 	.size		= ARRAY_SIZE(sdm845_data),
+	.need_llcc_cfg	= false,
 };
 
 static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
@@ -359,7 +365,8 @@ static int qcom_llcc_attr_cfg(const struct llcc_slice_config *table)
 	return ret;
 }
 
-static int qcom_llcc_cfg_program(struct platform_device *pdev)
+static int qcom_llcc_cfg_program(struct platform_device *pdev,
+				 const struct qcom_llcc_config *cfg)
 {
 	int i;
 	u32 sz;
@@ -375,6 +382,22 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev)
 		if (ret)
 			return ret;
 
+		if (cfg->need_llcc_cfg) {
+			u32 disable_cap_alloc, retain_pc;
+
+			disable_cap_alloc = llcc_table[i].dis_cap_alloc << llcc_table[i].slice_id;
+			ret = regmap_write(drv_data->bcast_regmap,
+					LLCC_TRP_SCID_DIS_CAP_ALLOC, disable_cap_alloc);
+			if (ret)
+				return ret;
+
+			retain_pc = llcc_table[i].retain_on_pc << llcc_table[i].slice_id;
+			ret = regmap_write(drv_data->bcast_regmap,
+					LLCC_TRP_PCB_ACT, retain_pc);
+			if (ret)
+				return ret;
+		}
+
 		if (llcc_table[i].activate_on_init) {
 			desc.slice_id = llcc_table[i].slice_id;
 			ret = llcc_slice_activate(&desc);
@@ -484,7 +507,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
 	mutex_init(&drv_data->lock);
 	platform_set_drvdata(pdev, drv_data);
 
-	ret = qcom_llcc_cfg_program(pdev);
+	ret = qcom_llcc_cfg_program(pdev, cfg);
 	if (ret)
 		goto err;
 
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Re: [PATCHv4 2/2] soc: qcom: llcc: Support chipsets that can write to llcc regs

[Stephen Boyd]

Quoting Sai Prakash Ranjan (2020-09-14 04:13:00)
> From: "Isaac J. Manjarres" <isaacm@codeaurora.org>
> 
> Older chipsets may not be allowed to configure certain LLCC registers
> as that is handled by the secure side software. However, this is not
> the case for newer chipsets and they must configure these registers
> according to the contents of the SCT table, while keeping in mind that
> older targets may not have these capabilities. So add support to allow
> such configuration of registers to enable capacity based allocation
> and power collapse retention for capable chipsets.
> 
> Reason for choosing capacity based allocation rather than the default
> way based allocation is because capacity based allocation allows more
> finer grain partition and provides more flexibility in configuration.
> As for the retention through power collapse, it has an advantage where
> the cache hits are more when we wake up from power collapse although
> it does burn more power but the exact power numbers are not known at
> the moment.
> 
> Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>
> (saiprakash.ranjan@codeaurora.org: use existing config and reword commit msg)

Should be [ not (

> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
>  drivers/soc/qcom/llcc-qcom.c | 27 +++++++++++++++++++++++++--
>  1 file changed, 25 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index 60ee31842dea..6aedccff49bb 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -375,6 +382,22 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev)
>                 if (ret)
>                         return ret;
>  
> +               if (cfg->need_llcc_cfg) {
> +                       u32 disable_cap_alloc, retain_pc;
> +
> +                       disable_cap_alloc = llcc_table[i].dis_cap_alloc << llcc_table[i].slice_id;
> +                       ret = regmap_write(drv_data->bcast_regmap,
> +                                       LLCC_TRP_SCID_DIS_CAP_ALLOC, disable_cap_alloc);
> +                       if (ret)
> +                               return ret;
> +
> +                       retain_pc = llcc_table[i].retain_on_pc << llcc_table[i].slice_id;
> +                       ret = regmap_write(drv_data->bcast_regmap,
> +                                       LLCC_TRP_PCB_ACT, retain_pc);
> +                       if (ret)
> +                               return ret;
> +               }
> +
>                 if (llcc_table[i].activate_on_init) {
>                         desc.slice_id = llcc_table[i].slice_id;
>                         ret = llcc_slice_activate(&desc);

I thought all of this stuff would move into the config function. So the
for loop is simplified to a function call and return if failure.

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Re: [PATCHv4 2/2] soc: qcom: llcc: Support chipsets that can write to llcc regs

[Sai Prakash Ranjan]

On 2020-09-15 00:16, Stephen Boyd wrote:
> Quoting Sai Prakash Ranjan (2020-09-14 04:13:00)
>> From: "Isaac J. Manjarres" <isaacm@codeaurora.org>
>> 
>> Older chipsets may not be allowed to configure certain LLCC registers
>> as that is handled by the secure side software. However, this is not
>> the case for newer chipsets and they must configure these registers
>> according to the contents of the SCT table, while keeping in mind that
>> older targets may not have these capabilities. So add support to allow
>> such configuration of registers to enable capacity based allocation
>> and power collapse retention for capable chipsets.
>> 
>> Reason for choosing capacity based allocation rather than the default
>> way based allocation is because capacity based allocation allows more
>> finer grain partition and provides more flexibility in configuration.
>> As for the retention through power collapse, it has an advantage where
>> the cache hits are more when we wake up from power collapse although
>> it does burn more power but the exact power numbers are not known at
>> the moment.
>> 
>> Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
>> Reviewed-by: Douglas Anderson <dianders@chromium.org>
>> (saiprakash.ranjan@codeaurora.org: use existing config and reword 
>> commit msg)
> 
> Should be [ not (
> 

Ok

>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>> ---
>>  drivers/soc/qcom/llcc-qcom.c | 27 +++++++++++++++++++++++++--
>>  1 file changed, 25 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/soc/qcom/llcc-qcom.c 
>> b/drivers/soc/qcom/llcc-qcom.c
>> index 60ee31842dea..6aedccff49bb 100644
>> --- a/drivers/soc/qcom/llcc-qcom.c
>> +++ b/drivers/soc/qcom/llcc-qcom.c
>> @@ -375,6 +382,22 @@ static int qcom_llcc_cfg_program(struct 
>> platform_device *pdev)
>>                 if (ret)
>>                         return ret;
>> 
>> +               if (cfg->need_llcc_cfg) {
>> +                       u32 disable_cap_alloc, retain_pc;
>> +
>> +                       disable_cap_alloc = 
>> llcc_table[i].dis_cap_alloc << llcc_table[i].slice_id;
>> +                       ret = regmap_write(drv_data->bcast_regmap,
>> +                                       LLCC_TRP_SCID_DIS_CAP_ALLOC, 
>> disable_cap_alloc);
>> +                       if (ret)
>> +                               return ret;
>> +
>> +                       retain_pc = llcc_table[i].retain_on_pc << 
>> llcc_table[i].slice_id;
>> +                       ret = regmap_write(drv_data->bcast_regmap,
>> +                                       LLCC_TRP_PCB_ACT, retain_pc);
>> +                       if (ret)
>> +                               return ret;
>> +               }
>> +
>>                 if (llcc_table[i].activate_on_init) {
>>                         desc.slice_id = llcc_table[i].slice_id;
>>                         ret = llcc_slice_activate(&desc);
> 
> I thought all of this stuff would move into the config function. So the
> for loop is simplified to a function call and return if failure.

The config function was specifically for attribute config
not for other llcc configs like these, so I will rename
qcom_llcc_attr_cfg() to _qcom_llcc_cfg_program() and move
everything there.

As a side note, I have your mails in my inbox but these
messages are not appearing in the list [1]. For Patch 2,
its on the list [2]. I have noticed same thing on your
messages for previous patches, where your reply for one
patch was on the list but the other one was missing, you
might have to check that.

[1] https://lore.kernel.org/patchwork/patch/1305132/
[2] https://lore.kernel.org/patchwork/patch/1305133/

Same with lore.kernel.org/lkml/ links but since url was big, I gave the
above patchwork links.

Thanks,
Sai

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a 
member
of Code Aurora Forum, hosted by The Linux Foundation

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Re: [PATCHv4 2/2] soc: qcom: llcc: Support chipsets that can write to llcc regs

[Stephen Boyd]

Quoting Sai Prakash Ranjan (2020-09-14 22:22:45)
> 
> As a side note, I have your mails in my inbox but these
> messages are not appearing in the list [1]. For Patch 2,
> its on the list [2]. I have noticed same thing on your
> messages for previous patches, where your reply for one
> patch was on the list but the other one was missing, you
> might have to check that.

I think my MUA has a hard time sometimes. I don't know how to fix it
besides switching away from it to something else. Seems that it can't
handle UTF-8 encoding properly and sends the wrong content-type headers.

> 
> [1] https://lore.kernel.org/patchwork/patch/1305132/
> [2] https://lore.kernel.org/patchwork/patch/1305133/
> 
> Same with lore.kernel.org/lkml/ links but since url was big, I gave the
> above patchwork links.
> 

The lore stuff seems slow sometimes. I see it on lore now:

https://lore.kernel.org/r/160010909573.4188128.171199552773965552@swboyd.mtv.corp.google.com
https://lore.kernel.org/r/160010921920.4188128.15524650302574745988@swboyd.mtv.corp.google.com

maybe I'm hitting spam filters and have to be allowed through. Don't
know.

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