From: Guenter Roeck <linux@roeck-us.net>
To: Peter Griffin <peter.griffin@linaro.org>
Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org,
tomasz.figa@gmail.com, s.nawrocki@samsung.com,
linus.walleij@linaro.org, wim@linux-watchdog.org,
catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de,
olof@lixom.net, cw00.choi@samsung.com, tudor.ambarus@linaro.org,
andre.draszik@linaro.org, semen.protsenko@linaro.org,
soc@kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org
Subject: Re: [PATCH 17/21] watchdog: s3c2410_wdt: Add support for Google tensor SoCs
Date: Thu, 5 Oct 2023 11:58:40 -0700 [thread overview]
Message-ID: <734eb901-84cc-4a47-a3f6-2313273f79b2@roeck-us.net> (raw)
In-Reply-To: <20231005155618.700312-18-peter.griffin@linaro.org>
On Thu, Oct 05, 2023 at 04:56:14PM +0100, Peter Griffin wrote:
> This patch adds the compatibles and drvdata for the Google
> gs101 & gs201 SoCs found in Pixel 6 and Pixel 7 phones. Similar
> to Exynos850 it has two watchdog instances, one for each cluster
> and has some control bits in PMU registers.
>
> The watchdog IP found in gs101 SoCs also supports a few
> additional bits/features in the WTCON register which we add
> support for and an additional register detailed below.
>
> dbgack-mask - Enables masking WDT interrupt and reset request
> according to asserted DBGACK input
>
> windowed-mode - Enabled Windowed watchdog mode
>
> Windowed watchdog mode also has an additional register WTMINCNT.
> If windowed watchdog is enabled and you reload WTCNT when the
> value is greater than WTMINCNT, it prompts interrupt or reset
> request as if the watchdog time has expired.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> drivers/watchdog/s3c2410_wdt.c | 116 +++++++++++++++++++++++++++++----
> 1 file changed, 105 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> index 0b4bd883ff28..4c23c7e6a3f1 100644
> --- a/drivers/watchdog/s3c2410_wdt.c
> +++ b/drivers/watchdog/s3c2410_wdt.c
> @@ -31,12 +31,14 @@
> #define S3C2410_WTDAT 0x04
> #define S3C2410_WTCNT 0x08
> #define S3C2410_WTCLRINT 0x0c
> -
> +#define S3C2410_WTMINCNT 0x10
> #define S3C2410_WTCNT_MAXCNT 0xffff
>
> -#define S3C2410_WTCON_RSTEN (1 << 0)
> -#define S3C2410_WTCON_INTEN (1 << 2)
> -#define S3C2410_WTCON_ENABLE (1 << 5)
> +#define S3C2410_WTCON_RSTEN (1 << 0)
> +#define S3C2410_WTCON_INTEN (1 << 2)
> +#define S3C2410_WTCON_ENABLE (1 << 5)
> +#define S3C2410_WTCON_DBGACK_MASK (1 << 16)
> +#define S3C2410_WTCON_WINDOWED_WD (1 << 20)
>
> #define S3C2410_WTCON_DIV16 (0 << 3)
> #define S3C2410_WTCON_DIV32 (1 << 3)
> @@ -61,12 +63,16 @@
> #define EXYNOS850_CLUSTER1_NONCPU_INT_EN 0x1644
> #define EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT 0x1520
> #define EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN 0x1544
> -
> #define EXYNOS850_CLUSTER0_WDTRESET_BIT 24
> #define EXYNOS850_CLUSTER1_WDTRESET_BIT 23
> #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT 25
> #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT 24
> -
> +#define GS_CLUSTER0_NONCPU_OUT 0x1220
> +#define GS_CLUSTER1_NONCPU_OUT 0x1420
> +#define GS_CLUSTER0_NONCPU_INT_EN 0x1244
> +#define GS_CLUSTER1_NONCPU_INT_EN 0x1444
> +#define GS_CLUSTER2_NONCPU_INT_EN 0x1644
> +#define GS_RST_STAT_REG_OFFSET 0x3B44
> /**
> * DOC: Quirk flags for different Samsung watchdog IP-cores
> *
> @@ -106,6 +112,8 @@
> #define QUIRK_HAS_PMU_RST_STAT (1 << 2)
> #define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3)
> #define QUIRK_HAS_PMU_CNT_EN (1 << 4)
> +#define QUIRK_HAS_DBGACK_BIT (1 << 5)
> +#define QUIRK_HAS_WTMINCNT_REG (1 << 6)
>
> /* These quirks require that we have a PMU register map */
> #define QUIRKS_HAVE_PMUREG \
> @@ -263,6 +271,54 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl1 = {
> QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN,
> };
>
> +static const struct s3c2410_wdt_variant drv_data_gs101_cl0 = {
> + .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
> + .mask_bit = 2,
> + .mask_reset_inv = true,
> + .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> + .rst_stat_bit = 0,
> + .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
> + .cnt_en_bit = 8,
> + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> +};
> +
> +static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = {
> + .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
> + .mask_bit = 2,
> + .mask_reset_inv = true,
> + .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> + .rst_stat_bit = 1,
> + .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
> + .cnt_en_bit = 7,
> + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> +};
> +
> +static const struct s3c2410_wdt_variant drv_data_gs201_cl0 = {
> + .mask_reset_reg = GS_CLUSTER0_NONCPU_INT_EN,
> + .mask_bit = 2,
> + .mask_reset_inv = true,
> + .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> + .rst_stat_bit = 0,
> + .cnt_en_reg = GS_CLUSTER0_NONCPU_OUT,
> + .cnt_en_bit = 8,
> + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> +};
> +
> +static const struct s3c2410_wdt_variant drv_data_gs201_cl1 = {
> + .mask_reset_reg = GS_CLUSTER1_NONCPU_INT_EN,
> + .mask_bit = 2,
> + .mask_reset_inv = true,
> + .rst_stat_reg = GS_RST_STAT_REG_OFFSET,
> + .rst_stat_bit = 1,
> + .cnt_en_reg = GS_CLUSTER1_NONCPU_OUT,
> + .cnt_en_bit = 7,
> + .quirks = QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_CNT_EN |
> + QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_DBGACK_BIT | QUIRK_HAS_WTMINCNT_REG,
> +};
> +
> static const struct of_device_id s3c2410_wdt_match[] = {
> { .compatible = "samsung,s3c2410-wdt",
> .data = &drv_data_s3c2410 },
> @@ -278,6 +334,10 @@ static const struct of_device_id s3c2410_wdt_match[] = {
> .data = &drv_data_exynos850_cl0 },
> { .compatible = "samsung,exynosautov9-wdt",
> .data = &drv_data_exynosautov9_cl0 },
> + { .compatible = "google,gs101-wdt",
> + .data = &drv_data_gs101_cl0 },
> + { .compatible = "google,gs201-wdt",
> + .data = &drv_data_gs201_cl0 },
> {},
> };
> MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
> @@ -375,6 +435,21 @@ static int s3c2410wdt_enable(struct s3c2410_wdt *wdt, bool en)
> return 0;
> }
>
> +static void s3c2410wdt_mask_dbgack(struct s3c2410_wdt *wdt, bool mask)
> +{
> + unsigned long wtcon;
> +
> + if (!(wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT))
> + return;
> +
> + wtcon = readl(wdt->reg_base + S3C2410_WTCON);
> + if (mask)
> + wtcon |= S3C2410_WTCON_DBGACK_MASK;
> + else
> + wtcon &= ~S3C2410_WTCON_DBGACK_MASK;
> + writel(wtcon, wdt->reg_base + S3C2410_WTCON);
> +}
> +
> static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
> {
> struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);
> @@ -585,9 +660,11 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
> }
>
> #ifdef CONFIG_OF
> - /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */
> + /* Choose Exynos850/ExynosAutov9/gsx01 driver data w.r.t. cluster index */
> if (variant == &drv_data_exynos850_cl0 ||
> - variant == &drv_data_exynosautov9_cl0) {
> + variant == &drv_data_exynosautov9_cl0 ||
> + variant == &drv_data_gs101_cl0 ||
> + variant == &drv_data_gs201_cl0) {
> u32 index;
> int err;
>
> @@ -600,9 +677,14 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
> case 0:
> break;
> case 1:
> - variant = (variant == &drv_data_exynos850_cl0) ?
> - &drv_data_exynos850_cl1 :
> - &drv_data_exynosautov9_cl1;
> + if (variant == &drv_data_exynos850_cl0)
> + variant = &drv_data_exynos850_cl1;
> + else if (variant == &drv_data_exynosautov9_cl0)
> + variant = &drv_data_exynosautov9_cl1;
> + else if (variant == &drv_data_gs101_cl0)
> + variant = &drv_data_gs101_cl1;
> + else if (variant == &drv_data_gs201_cl0)
> + variant = &drv_data_gs201_cl1;
> break;
> default:
> return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index);
> @@ -700,6 +782,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
> wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt);
> wdt->wdt_device.parent = dev;
>
> + s3c2410wdt_mask_dbgack(wdt, true);
> +
> /*
> * If "tmr_atboot" param is non-zero, start the watchdog right now. Also
> * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog.
> @@ -712,6 +796,7 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
> s3c2410wdt_start(&wdt->wdt_device);
> set_bit(WDOG_HW_RUNNING, &wdt->wdt_device.status);
> } else {
> + dev_info(dev, "stopping watchdog timer\n");
I am not inclined to accept patches adding such noise.
> s3c2410wdt_stop(&wdt->wdt_device);
> }
>
> @@ -738,6 +823,15 @@ static int s3c2410wdt_probe(struct platform_device *pdev)
> (wtcon & S3C2410_WTCON_RSTEN) ? "en" : "dis",
> (wtcon & S3C2410_WTCON_INTEN) ? "en" : "dis");
>
> + if (wdt->drv_data->quirks & QUIRK_HAS_DBGACK_BIT)
> + dev_info(dev, "DBGACK %sabled\n",
> + (wtcon & S3C2410_WTCON_DBGACK_MASK) ? "en" : "dis");
> +
> + if (wdt->drv_data->quirks & QUIRK_HAS_WTMINCNT_REG)
> + dev_info(dev, "windowed watchdog %sabled, wtmincnt=%x\n",
> + (wtcon & S3C2410_WTCON_WINDOWED_WD) ? "en" : "dis",
> + readl(wdt->reg_base + S3C2410_WTMINCNT));
... and I really don't see its value.
> +
> return 0;
> }
>
> --
> 2.42.0.582.g8ccd20d70d-goog
>
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next prev parent reply other threads:[~2023-10-05 18:59 UTC|newest]
Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-05 15:55 [PATCH 00/21] Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board Peter Griffin
2023-10-05 15:55 ` [PATCH 01/21] dt-bindings: interrupt-controller: Add gs101 interrupt controller Peter Griffin
2023-10-05 16:04 ` Krzysztof Kozlowski
2023-10-06 21:52 ` Linus Walleij
2023-10-05 15:55 ` [PATCH 02/21] dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible Peter Griffin
2023-10-05 16:05 ` Krzysztof Kozlowski
2023-10-05 15:56 ` [PATCH 03/21] dt-bindings: clock: Add Google gs101 clock management unit bindings Peter Griffin
2023-10-05 16:06 ` Krzysztof Kozlowski
2023-10-05 15:56 ` [PATCH 04/21] dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101 Peter Griffin
2023-10-05 16:07 ` Krzysztof Kozlowski
2023-10-06 12:41 ` Peter Griffin
2023-10-06 12:43 ` Krzysztof Kozlowski
2023-10-05 15:56 ` [PATCH 05/21] dt-bindings: watchdog: Document Google gs101 & gs201 watchdog bindings Peter Griffin
2023-10-05 16:08 ` Krzysztof Kozlowski
2023-10-05 17:37 ` William McVicker
2023-10-05 15:56 ` [PATCH 06/21] dt-bindings: arm: google: Add bindings for Google ARM platforms Peter Griffin
2023-10-06 20:44 ` Rob Herring
2023-10-05 15:56 ` [PATCH 07/21] dt-bindings: pinctrl: samsung: add google,gs101-pinctrl compatible Peter Griffin
2023-10-05 16:10 ` Krzysztof Kozlowski
2023-10-05 15:56 ` [PATCH 08/21] dt-bindings: pinctrl: samsung: add gs101-wakeup-eint compatible Peter Griffin
2023-10-05 16:10 ` Krzysztof Kozlowski
2023-10-05 15:56 ` [PATCH 09/21] dt-bindings: clock: gs101: Add cmu_top clock indices Peter Griffin
2023-10-05 16:11 ` Krzysztof Kozlowski
2023-10-08 22:48 ` Chanwoo Choi
2023-10-05 15:56 ` [PATCH 10/21] dt-bindings: clock: gs101: Add cmu_apm " Peter Griffin
2023-10-05 16:11 ` Krzysztof Kozlowski
2023-10-05 15:56 ` [PATCH 11/21] dt-bindings: clock: gs101: Add cmu_misc " Peter Griffin
2023-10-05 15:56 ` [PATCH 12/21] clk: samsung: clk-pll: Add support for pll_{0516,0517,518} Peter Griffin
2023-10-05 17:39 ` William McVicker
2023-10-08 22:51 ` Chanwoo Choi
2023-10-05 15:56 ` [PATCH 13/21] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates Peter Griffin
2023-10-05 17:42 ` William McVicker
2023-10-05 17:45 ` Krzysztof Kozlowski
2023-10-06 4:16 ` kernel test robot
2023-10-14 6:37 ` kernel test robot
2023-10-05 15:56 ` [PATCH 14/21] clk: samsung: clk-gs101: add CMU_APM support Peter Griffin
2023-10-05 17:43 ` William McVicker
2023-10-05 17:45 ` William McVicker
2023-10-05 15:56 ` [PATCH 15/21] clk: google: gs101: Add support for CMU_MISC clock unit Peter Griffin
2023-10-06 5:20 ` kernel test robot
2023-10-05 15:56 ` [PATCH 16/21] pinctrl: samsung: Add gs101 SoC pinctrl configuration Peter Griffin
2023-10-06 6:33 ` Krzysztof Kozlowski
2023-10-09 7:49 ` Peter Griffin
2023-10-05 15:56 ` [PATCH 17/21] watchdog: s3c2410_wdt: Add support for Google tensor SoCs Peter Griffin
2023-10-05 18:58 ` Guenter Roeck [this message]
2023-10-09 11:56 ` Peter Griffin
2023-10-05 15:56 ` [PATCH 18/21] arm64: dts: google: Add initial Google gs101 SoC support Peter Griffin
2023-10-05 16:21 ` Krzysztof Kozlowski
2023-10-05 17:59 ` William McVicker
2023-10-05 18:05 ` Greg KH
2023-10-05 19:18 ` Krzysztof Kozlowski
2023-10-05 19:23 ` Greg KH
2023-10-05 19:29 ` Krzysztof Kozlowski
2023-10-05 23:19 ` William McVicker
2023-10-06 6:06 ` Krzysztof Kozlowski
2023-10-06 8:48 ` Arnd Bergmann
2023-10-06 16:33 ` William McVicker
2023-10-07 14:34 ` Krzysztof Kozlowski
2023-10-09 16:10 ` William McVicker
2023-10-05 19:21 ` Krzysztof Kozlowski
2023-10-05 19:22 ` Krzysztof Kozlowski
2023-10-05 19:26 ` William McVicker
2023-10-09 12:01 ` Tudor Ambarus
2023-10-05 15:56 ` [PATCH 19/21] google/gs101: Add dt overlay for oriole board Peter Griffin
2023-10-05 16:33 ` Krzysztof Kozlowski
2023-10-09 20:03 ` William McVicker
2023-10-06 7:08 ` Geert Uytterhoeven
2023-10-06 20:52 ` Rob Herring
2023-10-10 12:09 ` Peter Griffin
2023-10-05 15:56 ` [PATCH 20/21] arm64: defconfig: Enable Google Tensor SoC Peter Griffin
2023-10-05 15:56 ` [PATCH 21/21] MAINTAINERS: add entry for " Peter Griffin
2023-10-05 16:32 ` [PATCH 00/21] Add minimal Tensor/GS101 SoC support and Oriole/Pixel6 board Krzysztof Kozlowski
2023-10-09 11:39 ` Peter Griffin
2023-10-09 11:10 ` Krzysztof Kozlowski
2023-10-09 11:40 ` Peter Griffin
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