* [PATCH 01/18] phy: mediatek: add a new helper to update bitfield
2022-09-20 9:00 [PATCH 00/18] unify register access and macros Chunfeng Yun
@ 2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:15 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 02/18] phy: mediatek: tphy: remove macros to prepare bitfield value Chunfeng Yun
` (17 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: Chunfeng Yun @ 2022-09-20 9:00 UTC (permalink / raw)
To: Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Chunfeng Yun, Kishon Vijay Abraham I,
Matthias Brugger, dri-devel, linux-mediatek, linux-arm-kernel,
linux-phy, linux-kernel, Jitao Shi, Stanley Chu
Due to FIELD_PREP() macro can be used to prepare a bitfield value,
local ones can be remove; add the new helper to make bitfield update
easier.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/phy/mediatek/phy-mtk-io.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/phy/mediatek/phy-mtk-io.h b/drivers/phy/mediatek/phy-mtk-io.h
index 500fcdab165d..a723d4afc9b4 100644
--- a/drivers/phy/mediatek/phy-mtk-io.h
+++ b/drivers/phy/mediatek/phy-mtk-io.h
@@ -8,6 +8,7 @@
#ifndef __PHY_MTK_H__
#define __PHY_MTK_H__
+#include <linux/bitfield.h>
#include <linux/io.h>
static inline void mtk_phy_clear_bits(void __iomem *reg, u32 bits)
@@ -35,4 +36,10 @@ static inline void mtk_phy_update_bits(void __iomem *reg, u32 mask, u32 val)
writel(tmp, reg);
}
+/* field @mask should be constant and continuous */
+static inline void mtk_phy_update_field(void __iomem *reg, u32 mask, u32 val)
+{
+ mtk_phy_update_bits(reg, mask, FIELD_PREP(mask, val));
+}
+
#endif
--
2.18.0
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^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH 01/18] phy: mediatek: add a new helper to update bitfield
2022-09-20 9:00 ` [PATCH 01/18] phy: mediatek: add a new helper to update bitfield Chunfeng Yun
@ 2022-09-21 8:15 ` AngeloGioacchino Del Regno
2022-09-22 2:36 ` Chunfeng Yun
0 siblings, 1 reply; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-09-21 8:15 UTC (permalink / raw)
To: Chunfeng Yun, Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Kishon Vijay Abraham I, Matthias Brugger,
dri-devel, linux-mediatek, linux-arm-kernel, linux-phy,
linux-kernel, Jitao Shi, Stanley Chu
Il 20/09/22 11:00, Chunfeng Yun ha scritto:
> Due to FIELD_PREP() macro can be used to prepare a bitfield value,
> local ones can be remove; add the new helper to make bitfield update
> easier.
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> drivers/phy/mediatek/phy-mtk-io.h | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/phy/mediatek/phy-mtk-io.h b/drivers/phy/mediatek/phy-mtk-io.h
> index 500fcdab165d..a723d4afc9b4 100644
> --- a/drivers/phy/mediatek/phy-mtk-io.h
> +++ b/drivers/phy/mediatek/phy-mtk-io.h
> @@ -8,6 +8,7 @@
> #ifndef __PHY_MTK_H__
> #define __PHY_MTK_H__
>
> +#include <linux/bitfield.h>
> #include <linux/io.h>
>
> static inline void mtk_phy_clear_bits(void __iomem *reg, u32 bits)
> @@ -35,4 +36,10 @@ static inline void mtk_phy_update_bits(void __iomem *reg, u32 mask, u32 val)
> writel(tmp, reg);
> }
>
> +/* field @mask should be constant and continuous */
"Field @mask shall be [...]"
^^^^^
> +static inline void mtk_phy_update_field(void __iomem *reg, u32 mask, u32 val)
...so, (void __iomem *reg, const u32 mask, u32 val)
> +{
> + mtk_phy_update_bits(reg, mask, FIELD_PREP(mask, val));
> +}
> +
> #endif
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 01/18] phy: mediatek: add a new helper to update bitfield
2022-09-21 8:15 ` AngeloGioacchino Del Regno
@ 2022-09-22 2:36 ` Chunfeng Yun
2022-09-22 7:17 ` AngeloGioacchino Del Regno
0 siblings, 1 reply; 39+ messages in thread
From: Chunfeng Yun @ 2022-09-22 2:36 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Kishon Vijay Abraham I, Matthias Brugger,
dri-devel, linux-mediatek, linux-arm-kernel, linux-phy,
linux-kernel, Jitao Shi, Stanley Chu
On Wed, 2022-09-21 at 10:15 +0200, AngeloGioacchino Del Regno wrote:
> Il 20/09/22 11:00, Chunfeng Yun ha scritto:
> > Due to FIELD_PREP() macro can be used to prepare a bitfield value,
> > local ones can be remove; add the new helper to make bitfield
> > update
> > easier.
> >
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> > drivers/phy/mediatek/phy-mtk-io.h | 7 +++++++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/drivers/phy/mediatek/phy-mtk-io.h
> > b/drivers/phy/mediatek/phy-mtk-io.h
> > index 500fcdab165d..a723d4afc9b4 100644
> > --- a/drivers/phy/mediatek/phy-mtk-io.h
> > +++ b/drivers/phy/mediatek/phy-mtk-io.h
> > @@ -8,6 +8,7 @@
> > #ifndef __PHY_MTK_H__
> > #define __PHY_MTK_H__
> >
> > +#include <linux/bitfield.h>
> > #include <linux/io.h>
> >
> > static inline void mtk_phy_clear_bits(void __iomem *reg, u32
> > bits)
> > @@ -35,4 +36,10 @@ static inline void mtk_phy_update_bits(void
> > __iomem *reg, u32 mask, u32 val)
> > writel(tmp, reg);
> > }
> >
> > +/* field @mask should be constant and continuous */
>
> "Field @mask shall be [...]"
> ^^^^^
Ok, will modify it
>
> > +static inline void mtk_phy_update_field(void __iomem *reg, u32
> > mask, u32 val)
>
> ...so, (void __iomem *reg, const u32 mask, u32 val)
Maybe no need const, @mask will be checked it in compile time when
use FIELD_PREP(), means @mask is a constant value, but not a variable.
Thanks
>
> > +{
> > + mtk_phy_update_bits(reg, mask, FIELD_PREP(mask, val));
> > +}
> > +
> > #endif
>
>
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 01/18] phy: mediatek: add a new helper to update bitfield
2022-09-22 2:36 ` Chunfeng Yun
@ 2022-09-22 7:17 ` AngeloGioacchino Del Regno
2022-09-23 6:03 ` Chunfeng Yun
0 siblings, 1 reply; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-09-22 7:17 UTC (permalink / raw)
To: Chunfeng Yun, Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Kishon Vijay Abraham I, Matthias Brugger,
dri-devel, linux-mediatek, linux-arm-kernel, linux-phy,
linux-kernel, Jitao Shi, Stanley Chu
Il 22/09/22 04:36, Chunfeng Yun ha scritto:
> On Wed, 2022-09-21 at 10:15 +0200, AngeloGioacchino Del Regno wrote:
>> Il 20/09/22 11:00, Chunfeng Yun ha scritto:
>>> Due to FIELD_PREP() macro can be used to prepare a bitfield value,
>>> local ones can be remove; add the new helper to make bitfield
>>> update
>>> easier.
>>>
>>> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
>>> ---
>>> drivers/phy/mediatek/phy-mtk-io.h | 7 +++++++
>>> 1 file changed, 7 insertions(+)
>>>
>>> diff --git a/drivers/phy/mediatek/phy-mtk-io.h
>>> b/drivers/phy/mediatek/phy-mtk-io.h
>>> index 500fcdab165d..a723d4afc9b4 100644
>>> --- a/drivers/phy/mediatek/phy-mtk-io.h
>>> +++ b/drivers/phy/mediatek/phy-mtk-io.h
>>> @@ -8,6 +8,7 @@
>>> #ifndef __PHY_MTK_H__
>>> #define __PHY_MTK_H__
>>>
>>> +#include <linux/bitfield.h>
>>> #include <linux/io.h>
>>>
>>> static inline void mtk_phy_clear_bits(void __iomem *reg, u32
>>> bits)
>>> @@ -35,4 +36,10 @@ static inline void mtk_phy_update_bits(void
>>> __iomem *reg, u32 mask, u32 val)
>>> writel(tmp, reg);
>>> }
>>>
>>> +/* field @mask should be constant and continuous */
>>
>> "Field @mask shall be [...]"
>> ^^^^^
> Ok, will modify it
>
>>
>>> +static inline void mtk_phy_update_field(void __iomem *reg, u32
>>> mask, u32 val)
>>
>> ...so, (void __iomem *reg, const u32 mask, u32 val)
> Maybe no need const, @mask will be checked it in compile time when
> use FIELD_PREP(), means @mask is a constant value, but not a variable.
>
Adding const is not *required*, but `mask` is, effectively, a constant, hence
it fully makes sense to add const.
> Thanks
>
>>
>>> +{
>>> + mtk_phy_update_bits(reg, mask, FIELD_PREP(mask, val));
>>> +}
>>> +
>>> #endif
>>
>>
>
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 01/18] phy: mediatek: add a new helper to update bitfield
2022-09-22 7:17 ` AngeloGioacchino Del Regno
@ 2022-09-23 6:03 ` Chunfeng Yun
0 siblings, 0 replies; 39+ messages in thread
From: Chunfeng Yun @ 2022-09-23 6:03 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Kishon Vijay Abraham I, Matthias Brugger,
dri-devel, linux-mediatek, linux-arm-kernel, linux-phy,
linux-kernel, Jitao Shi, Stanley Chu
On Thu, 2022-09-22 at 09:17 +0200, AngeloGioacchino Del Regno wrote:
> Il 22/09/22 04:36, Chunfeng Yun ha scritto:
> > On Wed, 2022-09-21 at 10:15 +0200, AngeloGioacchino Del Regno
> > wrote:
> > > Il 20/09/22 11:00, Chunfeng Yun ha scritto:
> > > > Due to FIELD_PREP() macro can be used to prepare a bitfield
> > > > value,
> > > > local ones can be remove; add the new helper to make bitfield
> > > > update
> > > > easier.
> > > >
> > > > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > > > ---
> > > > drivers/phy/mediatek/phy-mtk-io.h | 7 +++++++
> > > > 1 file changed, 7 insertions(+)
> > > >
> > > > diff --git a/drivers/phy/mediatek/phy-mtk-io.h
> > > > b/drivers/phy/mediatek/phy-mtk-io.h
> > > > index 500fcdab165d..a723d4afc9b4 100644
> > > > --- a/drivers/phy/mediatek/phy-mtk-io.h
> > > > +++ b/drivers/phy/mediatek/phy-mtk-io.h
> > > > @@ -8,6 +8,7 @@
> > > > #ifndef __PHY_MTK_H__
> > > > #define __PHY_MTK_H__
> > > >
> > > > +#include <linux/bitfield.h>
> > > > #include <linux/io.h>
> > > >
> > > > static inline void mtk_phy_clear_bits(void __iomem *reg, u32
> > > > bits)
> > > > @@ -35,4 +36,10 @@ static inline void mtk_phy_update_bits(void
> > > > __iomem *reg, u32 mask, u32 val)
> > > > writel(tmp, reg);
> > > > }
> > > >
> > > > +/* field @mask should be constant and continuous */
> > >
> > > "Field @mask shall be [...]"
> > > ^^^^^
> >
> > Ok, will modify it
> >
> > >
> > > > +static inline void mtk_phy_update_field(void __iomem *reg, u32
> > > > mask, u32 val)
> > >
> > > ...so, (void __iomem *reg, const u32 mask, u32 val)
> >
> > Maybe no need const, @mask will be checked it in compile time when
> > use FIELD_PREP(), means @mask is a constant value, but not a
> > variable.
> >
>
> Adding const is not *required*, but `mask` is, effectively, a
> constant, hence
> it fully makes sense to add const.
Prefer to leave it unchanged, there is no 'const' in
function mtk_phy_update_bits(), if add 'const', will cause build
warning. and FIELD_PREP() already do many checks in compile time.
Thanks
>
> > Thanks
> >
> > >
> > > > +{
> > > > + mtk_phy_update_bits(reg, mask, FIELD_PREP(mask, val));
> > > > +}
> > > > +
> > > > #endif
> > >
> > >
>
>
>
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^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 02/18] phy: mediatek: tphy: remove macros to prepare bitfield value
2022-09-20 9:00 [PATCH 00/18] unify register access and macros Chunfeng Yun
2022-09-20 9:00 ` [PATCH 01/18] phy: mediatek: add a new helper to update bitfield Chunfeng Yun
@ 2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` [PATCH 03/18] phy: mediatek: xsphy: remove macros used " Chunfeng Yun
` (16 subsequent siblings)
18 siblings, 0 replies; 39+ messages in thread
From: Chunfeng Yun @ 2022-09-20 9:00 UTC (permalink / raw)
To: Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Chunfeng Yun, Kishon Vijay Abraham I,
Matthias Brugger, dri-devel, linux-mediatek, linux-arm-kernel,
linux-phy, linux-kernel, Jitao Shi, Stanley Chu
Prefer to make use of FIELD_PREP() macro to prepare bitfield value,
then no need local ones anymore.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/phy/mediatek/phy-mtk-tphy.c | 193 ++++++++++------------------
1 file changed, 67 insertions(+), 126 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
index cc10298bc70d..e906a82791bd 100644
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
@@ -49,37 +49,28 @@
#define U3P_USBPHYACR0 0x000
#define PA0_RG_U2PLL_FORCE_ON BIT(15)
#define PA0_USB20_PLL_PREDIV GENMASK(7, 6)
-#define PA0_USB20_PLL_PREDIV_VAL(x) ((0x3 & (x)) << 6)
#define PA0_RG_USB20_INTR_EN BIT(5)
#define U3P_USBPHYACR1 0x004
#define PA1_RG_INTR_CAL GENMASK(23, 19)
-#define PA1_RG_INTR_CAL_VAL(x) ((0x1f & (x)) << 19)
#define PA1_RG_VRT_SEL GENMASK(14, 12)
-#define PA1_RG_VRT_SEL_VAL(x) ((0x7 & (x)) << 12)
#define PA1_RG_TERM_SEL GENMASK(10, 8)
-#define PA1_RG_TERM_SEL_VAL(x) ((0x7 & (x)) << 8)
#define U3P_USBPHYACR2 0x008
#define PA2_RG_U2PLL_BW GENMASK(21, 19)
-#define PA2_RG_U2PLL_BW_VAL(x) ((0x7 & (x)) << 19)
#define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18)
#define U3P_USBPHYACR5 0x014
#define PA5_RG_U2_HSTX_SRCAL_EN BIT(15)
#define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12)
-#define PA5_RG_U2_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
#define PA5_RG_U2_HS_100U_U3_EN BIT(11)
#define U3P_USBPHYACR6 0x018
#define PA6_RG_U2_PRE_EMP GENMASK(31, 30)
-#define PA6_RG_U2_PRE_EMP_VAL(x) ((0x3 & (x)) << 30)
#define PA6_RG_U2_BC11_SW_EN BIT(23)
#define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20)
#define PA6_RG_U2_DISCTH GENMASK(7, 4)
-#define PA6_RG_U2_DISCTH_VAL(x) ((0xf & (x)) << 4)
#define PA6_RG_U2_SQTH GENMASK(3, 0)
-#define PA6_RG_U2_SQTH_VAL(x) (0xf & (x))
#define U3P_U2PHYACR4 0x020
#define P2C_RG_USB20_GPIO_CTL BIT(9)
@@ -106,11 +97,9 @@
#define P2C_FORCE_SUSPENDM BIT(18)
#define P2C_FORCE_TERMSEL BIT(17)
#define P2C_RG_DATAIN GENMASK(13, 10)
-#define P2C_RG_DATAIN_VAL(x) ((0xf & (x)) << 10)
#define P2C_RG_DMPULLDOWN BIT(7)
#define P2C_RG_DPPULLDOWN BIT(6)
#define P2C_RG_XCVRSEL GENMASK(5, 4)
-#define P2C_RG_XCVRSEL_VAL(x) ((0x3 & (x)) << 4)
#define P2C_RG_SUSPENDM BIT(3)
#define P2C_RG_TERMSEL BIT(2)
#define P2C_DTM0_PART_MASK \
@@ -141,87 +130,65 @@
#define U3P_U3_PHYA_REG0 0x000
#define P3A_RG_IEXT_INTR GENMASK(15, 10)
-#define P3A_RG_IEXT_INTR_VAL(x) ((0x3f & (x)) << 10)
#define P3A_RG_CLKDRV_OFF GENMASK(3, 2)
-#define P3A_RG_CLKDRV_OFF_VAL(x) ((0x3 & (x)) << 2)
#define U3P_U3_PHYA_REG1 0x004
#define P3A_RG_CLKDRV_AMP GENMASK(31, 29)
-#define P3A_RG_CLKDRV_AMP_VAL(x) ((0x7 & (x)) << 29)
#define U3P_U3_PHYA_REG6 0x018
#define P3A_RG_TX_EIDLE_CM GENMASK(31, 28)
-#define P3A_RG_TX_EIDLE_CM_VAL(x) ((0xf & (x)) << 28)
#define U3P_U3_PHYA_REG9 0x024
#define P3A_RG_RX_DAC_MUX GENMASK(5, 1)
-#define P3A_RG_RX_DAC_MUX_VAL(x) ((0x1f & (x)) << 1)
#define U3P_U3_PHYA_DA_REG0 0x100
#define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16)
-#define P3A_RG_XTAL_EXT_PE2H_VAL(x) ((0x3 & (x)) << 16)
#define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12)
-#define P3A_RG_XTAL_EXT_PE1H_VAL(x) ((0x3 & (x)) << 12)
#define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10)
-#define P3A_RG_XTAL_EXT_EN_U3_VAL(x) ((0x3 & (x)) << 10)
#define U3P_U3_PHYA_DA_REG4 0x108
#define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19)
#define P3A_RG_PLL_BC_PE2H GENMASK(7, 6)
-#define P3A_RG_PLL_BC_PE2H_VAL(x) ((0x3 & (x)) << 6)
#define U3P_U3_PHYA_DA_REG5 0x10c
#define P3A_RG_PLL_BR_PE2H GENMASK(29, 28)
-#define P3A_RG_PLL_BR_PE2H_VAL(x) ((0x3 & (x)) << 28)
#define P3A_RG_PLL_IC_PE2H GENMASK(15, 12)
-#define P3A_RG_PLL_IC_PE2H_VAL(x) ((0xf & (x)) << 12)
#define U3P_U3_PHYA_DA_REG6 0x110
#define P3A_RG_PLL_IR_PE2H GENMASK(19, 16)
-#define P3A_RG_PLL_IR_PE2H_VAL(x) ((0xf & (x)) << 16)
#define U3P_U3_PHYA_DA_REG7 0x114
#define P3A_RG_PLL_BP_PE2H GENMASK(19, 16)
-#define P3A_RG_PLL_BP_PE2H_VAL(x) ((0xf & (x)) << 16)
#define U3P_U3_PHYA_DA_REG20 0x13c
#define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16)
-#define P3A_RG_PLL_DELTA1_PE2H_VAL(x) ((0xffff & (x)) << 16)
#define U3P_U3_PHYA_DA_REG25 0x148
#define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0)
-#define P3A_RG_PLL_DELTA_PE2H_VAL(x) (0xffff & (x))
#define U3P_U3_PHYD_LFPS1 0x00c
#define P3D_RG_FWAKE_TH GENMASK(21, 16)
-#define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16)
#define U3P_U3_PHYD_IMPCAL0 0x010
#define P3D_RG_FORCE_TX_IMPEL BIT(31)
#define P3D_RG_TX_IMPEL GENMASK(28, 24)
-#define P3D_RG_TX_IMPEL_VAL(x) ((0x1f & (x)) << 24)
#define U3P_U3_PHYD_IMPCAL1 0x014
#define P3D_RG_FORCE_RX_IMPEL BIT(31)
#define P3D_RG_RX_IMPEL GENMASK(28, 24)
-#define P3D_RG_RX_IMPEL_VAL(x) ((0x1f & (x)) << 24)
#define U3P_U3_PHYD_RSV 0x054
#define P3D_RG_EFUSE_AUTO_LOAD_DIS BIT(12)
#define U3P_U3_PHYD_CDR1 0x05c
#define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24)
-#define P3D_RG_CDR_BIR_LTD1_VAL(x) ((0x1f & (x)) << 24)
#define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8)
-#define P3D_RG_CDR_BIR_LTD0_VAL(x) ((0x1f & (x)) << 8)
#define U3P_U3_PHYD_RXDET1 0x128
#define P3D_RG_RXDET_STB2_SET GENMASK(17, 9)
-#define P3D_RG_RXDET_STB2_SET_VAL(x) ((0x1ff & (x)) << 9)
#define U3P_U3_PHYD_RXDET2 0x12c
#define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0)
-#define P3D_RG_RXDET_STB2_SET_P3_VAL(x) (0x1ff & (x))
#define U3P_SPLLC_XTALCTL3 0x018
#define XC3_RG_U3_XTAL_RX_PWD BIT(9)
@@ -229,10 +196,8 @@
#define U3P_U2FREQ_FMCR0 0x00
#define P2F_RG_MONCLK_SEL GENMASK(27, 26)
-#define P2F_RG_MONCLK_SEL_VAL(x) ((0x3 & (x)) << 26)
#define P2F_RG_FREQDET_EN BIT(24)
#define P2F_RG_CYCLECNT GENMASK(23, 0)
-#define P2F_RG_CYCLECNT_VAL(x) ((P2F_RG_CYCLECNT) & (x))
#define U3P_U2FREQ_VALUE 0x0c
@@ -249,60 +214,45 @@
#define PHYD_CTRL_SIGNAL_MODE4 0x1c
/* CDR Charge Pump P-path current adjustment */
#define RG_CDR_BICLTD1_GEN1_MSK GENMASK(23, 20)
-#define RG_CDR_BICLTD1_GEN1_VAL(x) ((0xf & (x)) << 20)
#define RG_CDR_BICLTD0_GEN1_MSK GENMASK(11, 8)
-#define RG_CDR_BICLTD0_GEN1_VAL(x) ((0xf & (x)) << 8)
#define PHYD_DESIGN_OPTION2 0x24
/* Symbol lock count selection */
#define RG_LOCK_CNT_SEL_MSK GENMASK(5, 4)
-#define RG_LOCK_CNT_SEL_VAL(x) ((0x3 & (x)) << 4)
#define PHYD_DESIGN_OPTION9 0x40
/* COMWAK GAP width window */
#define RG_TG_MAX_MSK GENMASK(20, 16)
-#define RG_TG_MAX_VAL(x) ((0x1f & (x)) << 16)
/* COMINIT GAP width window */
#define RG_T2_MAX_MSK GENMASK(13, 8)
-#define RG_T2_MAX_VAL(x) ((0x3f & (x)) << 8)
/* COMWAK GAP width window */
#define RG_TG_MIN_MSK GENMASK(7, 5)
-#define RG_TG_MIN_VAL(x) ((0x7 & (x)) << 5)
/* COMINIT GAP width window */
#define RG_T2_MIN_MSK GENMASK(4, 0)
-#define RG_T2_MIN_VAL(x) (0x1f & (x))
#define ANA_RG_CTRL_SIGNAL1 0x4c
/* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
#define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8)
-#define RG_IDRV_0DB_GEN1_VAL(x) ((0x3f & (x)) << 8)
#define ANA_RG_CTRL_SIGNAL4 0x58
#define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20)
-#define RG_CDR_BICLTR_GEN1_VAL(x) ((0xf & (x)) << 20)
/* Loop filter R1 resistance adjustment for Gen1 speed */
#define RG_CDR_BR_GEN2_MSK GENMASK(10, 8)
-#define RG_CDR_BR_GEN2_VAL(x) ((0x7 & (x)) << 8)
#define ANA_RG_CTRL_SIGNAL6 0x60
/* I-path capacitance adjustment for Gen1 */
#define RG_CDR_BC_GEN1_MSK GENMASK(28, 24)
-#define RG_CDR_BC_GEN1_VAL(x) ((0x1f & (x)) << 24)
#define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0)
-#define RG_CDR_BIRLTR_GEN1_VAL(x) (0x1f & (x))
#define ANA_EQ_EYE_CTRL_SIGNAL1 0x6c
/* RX Gen1 LEQ tuning step */
#define RG_EQ_DLEQ_LFI_GEN1_MSK GENMASK(11, 8)
-#define RG_EQ_DLEQ_LFI_GEN1_VAL(x) ((0xf & (x)) << 8)
#define ANA_EQ_EYE_CTRL_SIGNAL4 0xd8
#define RG_CDR_BIRLTD0_GEN1_MSK GENMASK(20, 16)
-#define RG_CDR_BIRLTD0_GEN1_VAL(x) ((0x1f & (x)) << 16)
#define ANA_EQ_EYE_CTRL_SIGNAL5 0xdc
#define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0)
-#define RG_CDR_BIRLTD0_GEN3_VAL(x) (0x1f & (x))
/* PHY switch between pcie/usb3/sgmii/sata */
#define USB_PHY_SWITCH_CTRL 0x0
@@ -414,9 +364,9 @@ static void hs_slew_rate_calibrate(struct mtk_tphy *tphy,
/* set cycle count as 1024, and select u2 channel */
tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL);
- tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT);
+ tmp |= FIELD_PREP(P2F_RG_CYCLECNT, U3P_FM_DET_CYCLE_CNT);
if (tphy->pdata->version == MTK_PHY_V1)
- tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1);
+ tmp |= FIELD_PREP(P2F_RG_MONCLK_SEL, instance->index >> 1);
writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
@@ -449,8 +399,8 @@ static void hs_slew_rate_calibrate(struct mtk_tphy *tphy,
tphy->src_ref_clk, tphy->src_coef);
/* set HS slew rate */
- mtk_phy_update_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL,
- PA5_RG_U2_HSTX_SRCTRL_VAL(calibration_val));
+ mtk_phy_update_field(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL,
+ calibration_val);
/* disable USB ring oscillator */
mtk_phy_clear_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCAL_EN);
@@ -460,33 +410,30 @@ static void u3_phy_instance_init(struct mtk_tphy *tphy,
struct mtk_phy_instance *instance)
{
struct u3phy_banks *u3_banks = &instance->u3_banks;
+ void __iomem *phya = u3_banks->phya;
+ void __iomem *phyd = u3_banks->phyd;
/* gating PCIe Analog XTAL clock */
mtk_phy_set_bits(u3_banks->spllc + U3P_SPLLC_XTALCTL3,
XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD);
/* gating XSQ */
- mtk_phy_update_bits(u3_banks->phya + U3P_U3_PHYA_DA_REG0,
- P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2));
+ mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG0, P3A_RG_XTAL_EXT_EN_U3, 2);
- mtk_phy_update_bits(u3_banks->phya + U3P_U3_PHYA_REG9,
- P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4));
+ mtk_phy_update_field(phya + U3P_U3_PHYA_REG9, P3A_RG_RX_DAC_MUX, 4);
- mtk_phy_update_bits(u3_banks->phya + U3P_U3_PHYA_REG6,
- P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe));
+ mtk_phy_update_field(phya + U3P_U3_PHYA_REG6, P3A_RG_TX_EIDLE_CM, 0xe);
mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_CDR1,
P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1,
- P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3));
+ FIELD_PREP(P3D_RG_CDR_BIR_LTD0, 0xc) |
+ FIELD_PREP(P3D_RG_CDR_BIR_LTD1, 0x3));
- mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_LFPS1,
- P3D_RG_FWAKE_TH, P3D_RG_FWAKE_TH_VAL(0x34));
+ mtk_phy_update_field(phyd + U3P_U3_PHYD_LFPS1, P3D_RG_FWAKE_TH, 0x34);
- mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
- P3D_RG_RXDET_STB2_SET, P3D_RG_RXDET_STB2_SET_VAL(0x10));
+ mtk_phy_update_field(phyd + U3P_U3_PHYD_RXDET1, P3D_RG_RXDET_STB2_SET, 0x10);
- mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
- P3D_RG_RXDET_STB2_SET_P3, P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));
+ mtk_phy_update_field(phyd + U3P_U3_PHYD_RXDET2, P3D_RG_RXDET_STB2_SET_P3, 0x10);
dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
}
@@ -500,11 +447,9 @@ static void u2_phy_pll_26m_set(struct mtk_tphy *tphy,
if (!tphy->pdata->sw_pll_48m_to_26m)
return;
- mtk_phy_update_bits(com + U3P_USBPHYACR0, PA0_USB20_PLL_PREDIV,
- PA0_USB20_PLL_PREDIV_VAL(0));
+ mtk_phy_update_field(com + U3P_USBPHYACR0, PA0_USB20_PLL_PREDIV, 0);
- mtk_phy_update_bits(com + U3P_USBPHYACR2, PA2_RG_U2PLL_BW,
- PA2_RG_U2PLL_BW_VAL(3));
+ mtk_phy_update_field(com + U3P_USBPHYACR2, PA2_RG_U2PLL_BW, 3);
writel(P2R_RG_U2PLL_FBDIV_26M, com + U3P_U2PHYA_RESV);
@@ -550,7 +495,7 @@ static void u2_phy_instance_init(struct mtk_tphy *tphy,
/* DP/DM BC1.1 path Disable */
mtk_phy_clear_bits(com + U3P_USBPHYACR6, PA6_RG_U2_BC11_SW_EN);
- mtk_phy_update_bits(com + U3P_USBPHYACR6, PA6_RG_U2_SQTH, PA6_RG_U2_SQTH_VAL(2));
+ mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_SQTH, 2);
/* Workaround only for mt8195, HW fix it for others (V3) */
u2_phy_pll_26m_set(tphy, instance);
@@ -653,43 +598,39 @@ static void pcie_phy_instance_init(struct mtk_tphy *tphy,
mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0,
P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H,
- P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2));
+ FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) |
+ FIELD_PREP(P3A_RG_XTAL_EXT_PE2H, 0x2));
/* ref clk drive */
- mtk_phy_update_bits(phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP,
- P3A_RG_CLKDRV_AMP_VAL(0x4));
+ mtk_phy_update_field(phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP, 0x4);
- mtk_phy_update_bits(phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF,
- P3A_RG_CLKDRV_OFF_VAL(0x1));
+ mtk_phy_update_field(phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF, 0x1);
/* SSC delta -5000ppm */
- mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG20, P3A_RG_PLL_DELTA1_PE2H,
- P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c));
+ mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG20, P3A_RG_PLL_DELTA1_PE2H, 0x3c);
- mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG25, P3A_RG_PLL_DELTA_PE2H,
- P3A_RG_PLL_DELTA_PE2H_VAL(0x36));
+ mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG25, P3A_RG_PLL_DELTA_PE2H, 0x36);
/* change pll BW 0.6M */
mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG5,
P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H,
- P3A_RG_PLL_BR_PE2H_VAL(0x1) | P3A_RG_PLL_IC_PE2H_VAL(0x1));
+ FIELD_PREP(P3A_RG_PLL_BR_PE2H, 0x1) |
+ FIELD_PREP(P3A_RG_PLL_IC_PE2H, 0x1));
mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG4,
P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H,
- P3A_RG_PLL_BC_PE2H_VAL(0x3));
+ FIELD_PREP(P3A_RG_PLL_BC_PE2H, 0x3));
- mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG6, P3A_RG_PLL_IR_PE2H,
- P3A_RG_PLL_IR_PE2H_VAL(0x2));
+ mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG6, P3A_RG_PLL_IR_PE2H, 0x2);
- mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG7, P3A_RG_PLL_BP_PE2H,
- P3A_RG_PLL_BP_PE2H_VAL(0xa));
+ mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG7, P3A_RG_PLL_BP_PE2H, 0xa);
/* Tx Detect Rx Timing: 10us -> 5us */
- mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
- P3D_RG_RXDET_STB2_SET, P3D_RG_RXDET_STB2_SET_VAL(0x10));
+ mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET1,
+ P3D_RG_RXDET_STB2_SET, 0x10);
- mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
- P3D_RG_RXDET_STB2_SET_P3, P3D_RG_RXDET_STB2_SET_P3_VAL(0x10));
+ mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET2,
+ P3D_RG_RXDET_STB2_SET_P3, 0x10);
/* wait for PCIe subsys register to active */
usleep_range(2500, 3000);
@@ -730,38 +671,38 @@ static void sata_phy_instance_init(struct mtk_tphy *tphy,
/* charge current adjustment */
mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL6,
RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK,
- RG_CDR_BIRLTR_GEN1_VAL(0x6) | RG_CDR_BC_GEN1_VAL(0x1a));
+ FIELD_PREP(RG_CDR_BIRLTR_GEN1_MSK, 0x6) |
+ FIELD_PREP(RG_CDR_BC_GEN1_MSK, 0x1a));
- mtk_phy_update_bits(phyd + ANA_EQ_EYE_CTRL_SIGNAL4, RG_CDR_BIRLTD0_GEN1_MSK,
- RG_CDR_BIRLTD0_GEN1_VAL(0x18));
+ mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL4, RG_CDR_BIRLTD0_GEN1_MSK, 0x18);
- mtk_phy_update_bits(phyd + ANA_EQ_EYE_CTRL_SIGNAL5, RG_CDR_BIRLTD0_GEN3_MSK,
- RG_CDR_BIRLTD0_GEN3_VAL(0x06));
+ mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL5, RG_CDR_BIRLTD0_GEN3_MSK, 0x06);
mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL4,
RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK,
- RG_CDR_BICLTR_GEN1_VAL(0x0c) | RG_CDR_BR_GEN2_VAL(0x07));
+ FIELD_PREP(RG_CDR_BICLTR_GEN1_MSK, 0x0c) |
+ FIELD_PREP(RG_CDR_BR_GEN2_MSK, 0x07));
mtk_phy_update_bits(phyd + PHYD_CTRL_SIGNAL_MODE4,
RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK,
- RG_CDR_BICLTD0_GEN1_VAL(0x08) | RG_CDR_BICLTD1_GEN1_VAL(0x02));
+ FIELD_PREP(RG_CDR_BICLTD0_GEN1_MSK, 0x08) |
+ FIELD_PREP(RG_CDR_BICLTD1_GEN1_MSK, 0x02));
- mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION2, RG_LOCK_CNT_SEL_MSK,
- RG_LOCK_CNT_SEL_VAL(0x02));
+ mtk_phy_update_field(phyd + PHYD_DESIGN_OPTION2, RG_LOCK_CNT_SEL_MSK, 0x02);
mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION9,
RG_T2_MIN_MSK | RG_TG_MIN_MSK,
- RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04));
+ FIELD_PREP(RG_T2_MIN_MSK, 0x12) |
+ FIELD_PREP(RG_TG_MIN_MSK, 0x04));
mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION9,
RG_T2_MAX_MSK | RG_TG_MAX_MSK,
- RG_T2_MAX_VAL(0x31) | RG_TG_MAX_VAL(0x0e));
+ FIELD_PREP(RG_T2_MAX_MSK, 0x31) |
+ FIELD_PREP(RG_TG_MAX_MSK, 0x0e));
- mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL1, RG_IDRV_0DB_GEN1_MSK,
- RG_IDRV_0DB_GEN1_VAL(0x20));
+ mtk_phy_update_field(phyd + ANA_RG_CTRL_SIGNAL1, RG_IDRV_0DB_GEN1_MSK, 0x20);
- mtk_phy_update_bits(phyd + ANA_EQ_EYE_CTRL_SIGNAL1, RG_EQ_DLEQ_LFI_GEN1_MSK,
- RG_EQ_DLEQ_LFI_GEN1_VAL(0x03));
+ mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL1, RG_EQ_DLEQ_LFI_GEN1_MSK, 0x03);
dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index);
}
@@ -857,33 +798,33 @@ static void u2_phy_props_set(struct mtk_tphy *tphy,
mtk_phy_set_bits(com + U3P_U2PHYBC12C, P2C_RG_CHGDT_EN);
if (tphy->pdata->version < MTK_PHY_V3 && instance->eye_src)
- mtk_phy_update_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL,
- PA5_RG_U2_HSTX_SRCTRL_VAL(instance->eye_src));
+ mtk_phy_update_field(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL,
+ instance->eye_src);
if (instance->eye_vrt)
- mtk_phy_update_bits(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL,
- PA1_RG_VRT_SEL_VAL(instance->eye_vrt));
+ mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL,
+ instance->eye_vrt);
if (instance->eye_term)
- mtk_phy_update_bits(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL,
- PA1_RG_TERM_SEL_VAL(instance->eye_term));
+ mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL,
+ instance->eye_term);
if (instance->intr) {
if (u2_banks->misc)
mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1,
MR1_EFUSE_AUTO_LOAD_DIS);
- mtk_phy_update_bits(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL,
- PA1_RG_INTR_CAL_VAL(instance->intr));
+ mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL,
+ instance->intr);
}
if (instance->discth)
- mtk_phy_update_bits(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH,
- PA6_RG_U2_DISCTH_VAL(instance->discth));
+ mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH,
+ instance->discth);
if (instance->pre_emphasis)
- mtk_phy_update_bits(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP,
- PA6_RG_U2_PRE_EMP_VAL(instance->pre_emphasis));
+ mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP,
+ instance->pre_emphasis);
}
/* type switch for usb3/pcie/sgmii/sata */
@@ -1032,23 +973,23 @@ static void phy_efuse_set(struct mtk_phy_instance *instance)
case PHY_TYPE_USB2:
mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1, MR1_EFUSE_AUTO_LOAD_DIS);
- mtk_phy_update_bits(u2_banks->com + U3P_USBPHYACR1, PA1_RG_INTR_CAL,
- PA1_RG_INTR_CAL_VAL(instance->efuse_intr));
+ mtk_phy_update_field(u2_banks->com + U3P_USBPHYACR1, PA1_RG_INTR_CAL,
+ instance->efuse_intr);
break;
case PHY_TYPE_USB3:
case PHY_TYPE_PCIE:
mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_RSV, P3D_RG_EFUSE_AUTO_LOAD_DIS);
- mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL,
- P3D_RG_TX_IMPEL_VAL(instance->efuse_tx_imp));
+ mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL,
+ instance->efuse_tx_imp);
mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_FORCE_TX_IMPEL);
- mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL,
- P3D_RG_RX_IMPEL_VAL(instance->efuse_rx_imp));
+ mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL,
+ instance->efuse_rx_imp);
mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_FORCE_RX_IMPEL);
- mtk_phy_update_bits(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_IEXT_INTR,
- P3A_RG_IEXT_INTR_VAL(instance->efuse_intr));
+ mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_IEXT_INTR,
+ instance->efuse_intr);
break;
default:
dev_warn(dev, "no sw efuse for type %d\n", instance->type);
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 03/18] phy: mediatek: xsphy: remove macros used to prepare bitfield value
2022-09-20 9:00 [PATCH 00/18] unify register access and macros Chunfeng Yun
2022-09-20 9:00 ` [PATCH 01/18] phy: mediatek: add a new helper to update bitfield Chunfeng Yun
2022-09-20 9:00 ` [PATCH 02/18] phy: mediatek: tphy: remove macros to prepare bitfield value Chunfeng Yun
@ 2022-09-20 9:00 ` Chunfeng Yun
2022-09-20 9:00 ` [PATCH 04/18] phy: mediatek: ufs: use common register access helpers Chunfeng Yun
` (15 subsequent siblings)
18 siblings, 0 replies; 39+ messages in thread
From: Chunfeng Yun @ 2022-09-20 9:00 UTC (permalink / raw)
To: Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Chunfeng Yun, Kishon Vijay Abraham I,
Matthias Brugger, dri-devel, linux-mediatek, linux-arm-kernel,
linux-phy, linux-kernel, Jitao Shi, Stanley Chu
Prefer to make use of FIELD_PREP() macro to prepare bitfield value,
then no need local ones anymore.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/phy/mediatek/phy-mtk-xsphy.c | 46 ++++++++++------------------
1 file changed, 17 insertions(+), 29 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-xsphy.c b/drivers/phy/mediatek/phy-mtk-xsphy.c
index c0cdb78f77fa..b222fbbd71d1 100644
--- a/drivers/phy/mediatek/phy-mtk-xsphy.c
+++ b/drivers/phy/mediatek/phy-mtk-xsphy.c
@@ -37,7 +37,6 @@
#define XSP_U2FREQ_FMCR0 ((SSUSB_SIFSLV_U2FREQ) + 0x00)
#define P2F_RG_FREQDET_EN BIT(24)
#define P2F_RG_CYCLECNT GENMASK(23, 0)
-#define P2F_RG_CYCLECNT_VAL(x) ((P2F_RG_CYCLECNT) & (x))
#define XSP_U2FREQ_MMONR0 ((SSUSB_SIFSLV_U2FREQ) + 0x0c)
@@ -50,16 +49,12 @@
#define XSP_USBPHYACR1 ((SSUSB_SIFSLV_U2PHY_COM) + 0x04)
#define P2A1_RG_INTR_CAL GENMASK(23, 19)
-#define P2A1_RG_INTR_CAL_VAL(x) ((0x1f & (x)) << 19)
#define P2A1_RG_VRT_SEL GENMASK(14, 12)
-#define P2A1_RG_VRT_SEL_VAL(x) ((0x7 & (x)) << 12)
#define P2A1_RG_TERM_SEL GENMASK(10, 8)
-#define P2A1_RG_TERM_SEL_VAL(x) ((0x7 & (x)) << 8)
#define XSP_USBPHYACR5 ((SSUSB_SIFSLV_U2PHY_COM) + 0x014)
#define P2A5_RG_HSTX_SRCAL_EN BIT(15)
#define P2A5_RG_HSTX_SRCTRL GENMASK(14, 12)
-#define P2A5_RG_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
#define XSP_USBPHYACR6 ((SSUSB_SIFSLV_U2PHY_COM) + 0x018)
#define P2A6_RG_BC11_SW_EN BIT(23)
@@ -74,15 +69,12 @@
#define SSPXTP_PHYA_GLB_00 ((SSPXTP_SIFSLV_PHYA_GLB) + 0x00)
#define RG_XTP_GLB_BIAS_INTR_CTRL GENMASK(21, 16)
-#define RG_XTP_GLB_BIAS_INTR_CTRL_VAL(x) ((0x3f & (x)) << 16)
#define SSPXTP_PHYA_LN_04 ((SSPXTP_SIFSLV_PHYA_LN) + 0x04)
#define RG_XTP_LN0_TX_IMPSEL GENMASK(4, 0)
-#define RG_XTP_LN0_TX_IMPSEL_VAL(x) (0x1f & (x))
#define SSPXTP_PHYA_LN_14 ((SSPXTP_SIFSLV_PHYA_LN) + 0x014)
#define RG_XTP_LN0_RX_IMPSEL GENMASK(4, 0)
-#define RG_XTP_LN0_RX_IMPSEL_VAL(x) (0x1f & (x))
#define XSP_REF_CLK 26 /* MHZ */
#define XSP_SLEW_RATE_COEF 17
@@ -134,8 +126,8 @@ static void u2_phy_slew_rate_calibrate(struct mtk_xsphy *xsphy,
mtk_phy_set_bits(pbase + XSP_U2FREQ_FMMONR1, P2F_RG_FRCK_EN);
/* set cycle count as 1024 */
- mtk_phy_update_bits(pbase + XSP_U2FREQ_FMCR0, P2F_RG_CYCLECNT,
- P2F_RG_CYCLECNT_VAL(XSP_FM_DET_CYCLE_CNT));
+ mtk_phy_update_field(pbase + XSP_U2FREQ_FMCR0, P2F_RG_CYCLECNT,
+ XSP_FM_DET_CYCLE_CNT);
/* enable frequency meter */
mtk_phy_set_bits(pbase + XSP_U2FREQ_FMCR0, P2F_RG_FREQDET_EN);
@@ -166,8 +158,7 @@ static void u2_phy_slew_rate_calibrate(struct mtk_xsphy *xsphy,
xsphy->src_ref_clk, xsphy->src_coef);
/* set HS slew rate */
- mtk_phy_update_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL,
- P2A5_RG_HSTX_SRCTRL_VAL(calib_val));
+ mtk_phy_update_field(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL, calib_val);
/* disable USB ring oscillator */
mtk_phy_clear_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCAL_EN);
@@ -280,20 +271,20 @@ static void u2_phy_props_set(struct mtk_xsphy *xsphy,
void __iomem *pbase = inst->port_base;
if (inst->efuse_intr)
- mtk_phy_update_bits(pbase + XSP_USBPHYACR1, P2A1_RG_INTR_CAL,
- P2A1_RG_INTR_CAL_VAL(inst->efuse_intr));
+ mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_INTR_CAL,
+ inst->efuse_intr);
if (inst->eye_src)
- mtk_phy_update_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL,
- P2A5_RG_HSTX_SRCTRL_VAL(inst->eye_src));
+ mtk_phy_update_field(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL,
+ inst->eye_src);
if (inst->eye_vrt)
- mtk_phy_update_bits(pbase + XSP_USBPHYACR1, P2A1_RG_VRT_SEL,
- P2A1_RG_VRT_SEL_VAL(inst->eye_vrt));
+ mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_VRT_SEL,
+ inst->eye_vrt);
if (inst->eye_term)
- mtk_phy_update_bits(pbase + XSP_USBPHYACR1, P2A1_RG_TERM_SEL,
- P2A1_RG_TERM_SEL_VAL(inst->eye_term));
+ mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_TERM_SEL,
+ inst->eye_term);
}
static void u3_phy_props_set(struct mtk_xsphy *xsphy,
@@ -302,19 +293,16 @@ static void u3_phy_props_set(struct mtk_xsphy *xsphy,
void __iomem *pbase = inst->port_base;
if (inst->efuse_intr)
- mtk_phy_update_bits(xsphy->glb_base + SSPXTP_PHYA_GLB_00,
- RG_XTP_GLB_BIAS_INTR_CTRL,
- RG_XTP_GLB_BIAS_INTR_CTRL_VAL(inst->efuse_intr));
+ mtk_phy_update_field(xsphy->glb_base + SSPXTP_PHYA_GLB_00,
+ RG_XTP_GLB_BIAS_INTR_CTRL, inst->efuse_intr);
if (inst->efuse_tx_imp)
- mtk_phy_update_bits(pbase + SSPXTP_PHYA_LN_04,
- RG_XTP_LN0_TX_IMPSEL,
- RG_XTP_LN0_TX_IMPSEL_VAL(inst->efuse_tx_imp));
+ mtk_phy_update_field(pbase + SSPXTP_PHYA_LN_04,
+ RG_XTP_LN0_TX_IMPSEL, inst->efuse_tx_imp);
if (inst->efuse_rx_imp)
- mtk_phy_update_bits(pbase + SSPXTP_PHYA_LN_14,
- RG_XTP_LN0_RX_IMPSEL,
- RG_XTP_LN0_RX_IMPSEL_VAL(inst->efuse_rx_imp));
+ mtk_phy_update_field(pbase + SSPXTP_PHYA_LN_14,
+ RG_XTP_LN0_RX_IMPSEL, inst->efuse_rx_imp);
}
static int mtk_phy_init(struct phy *phy)
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH 04/18] phy: mediatek: ufs: use common register access helpers
2022-09-20 9:00 [PATCH 00/18] unify register access and macros Chunfeng Yun
` (2 preceding siblings ...)
2022-09-20 9:00 ` [PATCH 03/18] phy: mediatek: xsphy: remove macros used " Chunfeng Yun
@ 2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 05/18] phy: mediatek: pcie: use new helper to update register bits Chunfeng Yun
` (14 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: Chunfeng Yun @ 2022-09-20 9:00 UTC (permalink / raw)
To: Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Chunfeng Yun, Kishon Vijay Abraham I,
Matthias Brugger, dri-devel, linux-mediatek, linux-arm-kernel,
linux-phy, linux-kernel, Jitao Shi, Stanley Chu
No need define private register access helpers, use common ones defined
in phy-mtk-io.h
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/phy/mediatek/phy-mtk-ufs.c | 78 +++++++++++-------------------
1 file changed, 28 insertions(+), 50 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-ufs.c b/drivers/phy/mediatek/phy-mtk-ufs.c
index a6af06941203..fc19e0fa8ed5 100644
--- a/drivers/phy/mediatek/phy-mtk-ufs.c
+++ b/drivers/phy/mediatek/phy-mtk-ufs.c
@@ -11,6 +11,8 @@
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include "phy-mtk-io.h"
+
/* mphy register and offsets */
#define MP_GLB_DIG_8C 0x008C
#define FRC_PLL_ISO_EN BIT(8)
@@ -39,34 +41,6 @@ struct ufs_mtk_phy {
struct clk_bulk_data clks[UFSPHY_CLKS_CNT];
};
-static inline u32 mphy_readl(struct ufs_mtk_phy *phy, u32 reg)
-{
- return readl(phy->mmio + reg);
-}
-
-static inline void mphy_writel(struct ufs_mtk_phy *phy, u32 val, u32 reg)
-{
- writel(val, phy->mmio + reg);
-}
-
-static void mphy_set_bit(struct ufs_mtk_phy *phy, u32 reg, u32 bit)
-{
- u32 val;
-
- val = mphy_readl(phy, reg);
- val |= bit;
- mphy_writel(phy, val, reg);
-}
-
-static void mphy_clr_bit(struct ufs_mtk_phy *phy, u32 reg, u32 bit)
-{
- u32 val;
-
- val = mphy_readl(phy, reg);
- val &= ~bit;
- mphy_writel(phy, val, reg);
-}
-
static struct ufs_mtk_phy *get_ufs_mtk_phy(struct phy *generic_phy)
{
return (struct ufs_mtk_phy *)phy_get_drvdata(generic_phy);
@@ -84,57 +58,61 @@ static int ufs_mtk_phy_clk_init(struct ufs_mtk_phy *phy)
static void ufs_mtk_phy_set_active(struct ufs_mtk_phy *phy)
{
+ void __iomem *mmio = phy->mmio;
+
/* release DA_MP_PLL_PWR_ON */
- mphy_set_bit(phy, MP_GLB_DIG_8C, PLL_PWR_ON);
- mphy_clr_bit(phy, MP_GLB_DIG_8C, FRC_FRC_PWR_ON);
+ mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, PLL_PWR_ON);
+ mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, FRC_FRC_PWR_ON);
/* release DA_MP_PLL_ISO_EN */
- mphy_clr_bit(phy, MP_GLB_DIG_8C, PLL_ISO_EN);
- mphy_clr_bit(phy, MP_GLB_DIG_8C, FRC_PLL_ISO_EN);
+ mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, PLL_ISO_EN);
+ mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN);
/* release DA_MP_CDR_PWR_ON */
- mphy_set_bit(phy, MP_LN_RX_44, CDR_PWR_ON);
- mphy_clr_bit(phy, MP_LN_RX_44, FRC_CDR_PWR_ON);
+ mtk_phy_set_bits(mmio + MP_LN_RX_44, CDR_PWR_ON);
+ mtk_phy_clear_bits(mmio + MP_LN_RX_44, FRC_CDR_PWR_ON);
/* release DA_MP_CDR_ISO_EN */
- mphy_clr_bit(phy, MP_LN_RX_44, CDR_ISO_EN);
- mphy_clr_bit(phy, MP_LN_RX_44, FRC_CDR_ISO_EN);
+ mtk_phy_clear_bits(mmio + MP_LN_RX_44, CDR_ISO_EN);
+ mtk_phy_clear_bits(mmio + MP_LN_RX_44, FRC_CDR_ISO_EN);
/* release DA_MP_RX0_SQ_EN */
- mphy_set_bit(phy, MP_LN_DIG_RX_AC, RX_SQ_EN);
- mphy_clr_bit(phy, MP_LN_DIG_RX_AC, FRC_RX_SQ_EN);
+ mtk_phy_set_bits(mmio + MP_LN_DIG_RX_AC, RX_SQ_EN);
+ mtk_phy_clear_bits(mmio + MP_LN_DIG_RX_AC, FRC_RX_SQ_EN);
/* delay 1us to wait DIFZ stable */
udelay(1);
/* release DIFZ */
- mphy_clr_bit(phy, MP_LN_DIG_RX_9C, FSM_DIFZ_FRC);
+ mtk_phy_clear_bits(mmio + MP_LN_DIG_RX_9C, FSM_DIFZ_FRC);
}
static void ufs_mtk_phy_set_deep_hibern(struct ufs_mtk_phy *phy)
{
+ void __iomem *mmio = phy->mmio;
+
/* force DIFZ */
- mphy_set_bit(phy, MP_LN_DIG_RX_9C, FSM_DIFZ_FRC);
+ mtk_phy_set_bits(mmio + MP_LN_DIG_RX_9C, FSM_DIFZ_FRC);
/* force DA_MP_RX0_SQ_EN */
- mphy_set_bit(phy, MP_LN_DIG_RX_AC, FRC_RX_SQ_EN);
- mphy_clr_bit(phy, MP_LN_DIG_RX_AC, RX_SQ_EN);
+ mtk_phy_set_bits(mmio + MP_LN_DIG_RX_AC, FRC_RX_SQ_EN);
+ mtk_phy_clear_bits(mmio + MP_LN_DIG_RX_AC, RX_SQ_EN);
/* force DA_MP_CDR_ISO_EN */
- mphy_set_bit(phy, MP_LN_RX_44, FRC_CDR_ISO_EN);
- mphy_set_bit(phy, MP_LN_RX_44, CDR_ISO_EN);
+ mtk_phy_set_bits(mmio + MP_LN_RX_44, FRC_CDR_ISO_EN);
+ mtk_phy_set_bits(mmio + MP_LN_RX_44, CDR_ISO_EN);
/* force DA_MP_CDR_PWR_ON */
- mphy_set_bit(phy, MP_LN_RX_44, FRC_CDR_PWR_ON);
- mphy_clr_bit(phy, MP_LN_RX_44, CDR_PWR_ON);
+ mtk_phy_set_bits(mmio + MP_LN_RX_44, FRC_CDR_PWR_ON);
+ mtk_phy_clear_bits(mmio + MP_LN_RX_44, CDR_PWR_ON);
/* force DA_MP_PLL_ISO_EN */
- mphy_set_bit(phy, MP_GLB_DIG_8C, FRC_PLL_ISO_EN);
- mphy_set_bit(phy, MP_GLB_DIG_8C, PLL_ISO_EN);
+ mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, FRC_PLL_ISO_EN);
+ mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, PLL_ISO_EN);
/* force DA_MP_PLL_PWR_ON */
- mphy_set_bit(phy, MP_GLB_DIG_8C, FRC_FRC_PWR_ON);
- mphy_clr_bit(phy, MP_GLB_DIG_8C, PLL_PWR_ON);
+ mtk_phy_set_bits(mmio + MP_GLB_DIG_8C, FRC_FRC_PWR_ON);
+ mtk_phy_clear_bits(mmio + MP_GLB_DIG_8C, PLL_PWR_ON);
}
static int ufs_mtk_phy_power_on(struct phy *generic_phy)
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH 04/18] phy: mediatek: ufs: use common register access helpers
2022-09-20 9:00 ` [PATCH 04/18] phy: mediatek: ufs: use common register access helpers Chunfeng Yun
@ 2022-09-21 8:13 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-09-21 8:13 UTC (permalink / raw)
To: Chunfeng Yun, Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Kishon Vijay Abraham I, Matthias Brugger,
dri-devel, linux-mediatek, linux-arm-kernel, linux-phy,
linux-kernel, Jitao Shi, Stanley Chu
Il 20/09/22 11:00, Chunfeng Yun ha scritto:
> No need define private register access helpers, use common ones defined
> in phy-mtk-io.h
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 05/18] phy: mediatek: pcie: use new helper to update register bits
2022-09-20 9:00 [PATCH 00/18] unify register access and macros Chunfeng Yun
` (3 preceding siblings ...)
2022-09-20 9:00 ` [PATCH 04/18] phy: mediatek: ufs: use common register access helpers Chunfeng Yun
@ 2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 06/18] phy: mediatek: hdmi: mt2701: use GENMASK and BIT to generate mask and bits Chunfeng Yun
` (13 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: Chunfeng Yun @ 2022-09-20 9:00 UTC (permalink / raw)
To: Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Chunfeng Yun, Kishon Vijay Abraham I,
Matthias Brugger, dri-devel, linux-mediatek, linux-arm-kernel,
linux-phy, linux-kernel, Jitao Shi, Stanley Chu
The new helper will use FIELD_PREP() macro to prepare bits value
according to mask, then we no need do it anymore.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/phy/mediatek/phy-mtk-pcie.c | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-pcie.c b/drivers/phy/mediatek/phy-mtk-pcie.c
index 7f29d43442bf..25dbd6e35722 100644
--- a/drivers/phy/mediatek/phy-mtk-pcie.c
+++ b/drivers/phy/mediatek/phy-mtk-pcie.c
@@ -89,14 +89,14 @@ static void mtk_pcie_efuse_set_lane(struct mtk_pcie_phy *pcie_phy,
addr = pcie_phy->sif_base + PEXTP_ANA_LN0_TRX_REG +
lane * PEXTP_ANA_LANE_OFFSET;
- mtk_phy_update_bits(addr + PEXTP_ANA_TX_REG, EFUSE_LN_TX_PMOS_SEL,
- FIELD_PREP(EFUSE_LN_TX_PMOS_SEL, data->tx_pmos));
+ mtk_phy_update_field(addr + PEXTP_ANA_TX_REG, EFUSE_LN_TX_PMOS_SEL,
+ data->tx_pmos);
- mtk_phy_update_bits(addr + PEXTP_ANA_TX_REG, EFUSE_LN_TX_NMOS_SEL,
- FIELD_PREP(EFUSE_LN_TX_NMOS_SEL, data->tx_nmos));
+ mtk_phy_update_field(addr + PEXTP_ANA_TX_REG, EFUSE_LN_TX_NMOS_SEL,
+ data->tx_nmos);
- mtk_phy_update_bits(addr + PEXTP_ANA_RX_REG, EFUSE_LN_RX_SEL,
- FIELD_PREP(EFUSE_LN_RX_SEL, data->rx_data));
+ mtk_phy_update_field(addr + PEXTP_ANA_RX_REG, EFUSE_LN_RX_SEL,
+ data->rx_data);
}
/**
@@ -116,9 +116,8 @@ static int mtk_pcie_phy_init(struct phy *phy)
return 0;
/* Set global data */
- mtk_phy_update_bits(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG,
- EFUSE_GLB_INTR_SEL,
- FIELD_PREP(EFUSE_GLB_INTR_SEL, pcie_phy->efuse_glb_intr));
+ mtk_phy_update_field(pcie_phy->sif_base + PEXTP_ANA_GLB_00_REG,
+ EFUSE_GLB_INTR_SEL, pcie_phy->efuse_glb_intr);
for (i = 0; i < pcie_phy->data->num_lanes; i++)
mtk_pcie_efuse_set_lane(pcie_phy, i);
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH 05/18] phy: mediatek: pcie: use new helper to update register bits
2022-09-20 9:00 ` [PATCH 05/18] phy: mediatek: pcie: use new helper to update register bits Chunfeng Yun
@ 2022-09-21 8:13 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-09-21 8:13 UTC (permalink / raw)
To: Chunfeng Yun, Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Kishon Vijay Abraham I, Matthias Brugger,
dri-devel, linux-mediatek, linux-arm-kernel, linux-phy,
linux-kernel, Jitao Shi, Stanley Chu
Il 20/09/22 11:00, Chunfeng Yun ha scritto:
> The new helper will use FIELD_PREP() macro to prepare bits value
> according to mask, then we no need do it anymore.
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 06/18] phy: mediatek: hdmi: mt2701: use GENMASK and BIT to generate mask and bits
2022-09-20 9:00 [PATCH 00/18] unify register access and macros Chunfeng Yun
` (4 preceding siblings ...)
2022-09-20 9:00 ` [PATCH 05/18] phy: mediatek: pcie: use new helper to update register bits Chunfeng Yun
@ 2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 07/18] phy: mediatek: hdmi: mt2701: use FIELD_PREP to prepare bits field Chunfeng Yun
` (12 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: Chunfeng Yun @ 2022-09-20 9:00 UTC (permalink / raw)
To: Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Chunfeng Yun, Kishon Vijay Abraham I,
Matthias Brugger, dri-devel, linux-mediatek, linux-arm-kernel,
linux-phy, linux-kernel, Jitao Shi, Stanley Chu
Use GENMASK() and BIT() macros to generate mask and bits
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c | 56 +++++++++++-----------
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
index b74c65a1762c..ce36f37c698d 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
@@ -8,62 +8,62 @@
#define HDMI_CON0 0x00
#define RG_HDMITX_DRV_IBIAS 0
-#define RG_HDMITX_DRV_IBIAS_MASK (0x3f << 0)
+#define RG_HDMITX_DRV_IBIAS_MASK GENMASK(5, 0)
#define RG_HDMITX_EN_SER 12
-#define RG_HDMITX_EN_SER_MASK (0x0f << 12)
+#define RG_HDMITX_EN_SER_MASK GENMASK(15, 12)
#define RG_HDMITX_EN_SLDO 16
-#define RG_HDMITX_EN_SLDO_MASK (0x0f << 16)
+#define RG_HDMITX_EN_SLDO_MASK GENMASK(19, 16)
#define RG_HDMITX_EN_PRED 20
-#define RG_HDMITX_EN_PRED_MASK (0x0f << 20)
+#define RG_HDMITX_EN_PRED_MASK GENMASK(23, 20)
#define RG_HDMITX_EN_IMP 24
-#define RG_HDMITX_EN_IMP_MASK (0x0f << 24)
+#define RG_HDMITX_EN_IMP_MASK GENMASK(27, 24)
#define RG_HDMITX_EN_DRV 28
-#define RG_HDMITX_EN_DRV_MASK (0x0f << 28)
+#define RG_HDMITX_EN_DRV_MASK GENMASK(31, 28)
#define HDMI_CON1 0x04
#define RG_HDMITX_PRED_IBIAS 18
-#define RG_HDMITX_PRED_IBIAS_MASK (0x0f << 18)
-#define RG_HDMITX_PRED_IMP (0x01 << 22)
+#define RG_HDMITX_PRED_IBIAS_MASK GENMASK(21, 18)
+#define RG_HDMITX_PRED_IMP BIT(22)
#define RG_HDMITX_DRV_IMP 26
-#define RG_HDMITX_DRV_IMP_MASK (0x3f << 26)
+#define RG_HDMITX_DRV_IMP_MASK GENMASK(31, 26)
#define HDMI_CON2 0x08
-#define RG_HDMITX_EN_TX_CKLDO (0x01 << 0)
-#define RG_HDMITX_EN_TX_POSDIV (0x01 << 1)
+#define RG_HDMITX_EN_TX_CKLDO BIT(0)
+#define RG_HDMITX_EN_TX_POSDIV BIT(1)
#define RG_HDMITX_TX_POSDIV 3
-#define RG_HDMITX_TX_POSDIV_MASK (0x03 << 3)
-#define RG_HDMITX_EN_MBIAS (0x01 << 6)
-#define RG_HDMITX_MBIAS_LPF_EN (0x01 << 7)
+#define RG_HDMITX_TX_POSDIV_MASK GENMASK(4, 3)
+#define RG_HDMITX_EN_MBIAS BIT(6)
+#define RG_HDMITX_MBIAS_LPF_EN BIT(7)
#define HDMI_CON4 0x10
-#define RG_HDMITX_RESERVE_MASK (0xffffffff << 0)
+#define RG_HDMITX_RESERVE_MASK GENMASK(31, 0)
#define HDMI_CON6 0x18
#define RG_HTPLL_BR 0
-#define RG_HTPLL_BR_MASK (0x03 << 0)
+#define RG_HTPLL_BR_MASK GENMASK(1, 0)
#define RG_HTPLL_BC 2
-#define RG_HTPLL_BC_MASK (0x03 << 2)
+#define RG_HTPLL_BC_MASK GENMASK(3, 2)
#define RG_HTPLL_BP 4
-#define RG_HTPLL_BP_MASK (0x0f << 4)
+#define RG_HTPLL_BP_MASK GENMASK(7, 4)
#define RG_HTPLL_IR 8
-#define RG_HTPLL_IR_MASK (0x0f << 8)
+#define RG_HTPLL_IR_MASK GENMASK(11, 8)
#define RG_HTPLL_IC 12
-#define RG_HTPLL_IC_MASK (0x0f << 12)
+#define RG_HTPLL_IC_MASK GENMASK(15, 12)
#define RG_HTPLL_POSDIV 16
-#define RG_HTPLL_POSDIV_MASK (0x03 << 16)
+#define RG_HTPLL_POSDIV_MASK GENMASK(17, 16)
#define RG_HTPLL_PREDIV 18
-#define RG_HTPLL_PREDIV_MASK (0x03 << 18)
+#define RG_HTPLL_PREDIV_MASK GENMASK(19, 18)
#define RG_HTPLL_FBKSEL 20
-#define RG_HTPLL_FBKSEL_MASK (0x03 << 20)
-#define RG_HTPLL_RLH_EN (0x01 << 22)
+#define RG_HTPLL_FBKSEL_MASK GENMASK(21, 20)
+#define RG_HTPLL_RLH_EN BIT(22)
#define RG_HTPLL_FBKDIV 24
-#define RG_HTPLL_FBKDIV_MASK (0x7f << 24)
-#define RG_HTPLL_EN (0x01 << 31)
+#define RG_HTPLL_FBKDIV_MASK GENMASK(30, 24)
+#define RG_HTPLL_EN BIT(31)
#define HDMI_CON7 0x1c
-#define RG_HTPLL_AUTOK_EN (0x01 << 23)
+#define RG_HTPLL_AUTOK_EN BIT(23)
#define RG_HTPLL_DIVEN 28
-#define RG_HTPLL_DIVEN_MASK (0x07 << 28)
+#define RG_HTPLL_DIVEN_MASK GENMASK(30, 28)
static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
{
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH 06/18] phy: mediatek: hdmi: mt2701: use GENMASK and BIT to generate mask and bits
2022-09-20 9:00 ` [PATCH 06/18] phy: mediatek: hdmi: mt2701: use GENMASK and BIT to generate mask and bits Chunfeng Yun
@ 2022-09-21 8:13 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-09-21 8:13 UTC (permalink / raw)
To: Chunfeng Yun, Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Kishon Vijay Abraham I, Matthias Brugger,
dri-devel, linux-mediatek, linux-arm-kernel, linux-phy,
linux-kernel, Jitao Shi, Stanley Chu
Il 20/09/22 11:00, Chunfeng Yun ha scritto:
> Use GENMASK() and BIT() macros to generate mask and bits
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 07/18] phy: mediatek: hdmi: mt2701: use FIELD_PREP to prepare bits field
2022-09-20 9:00 [PATCH 00/18] unify register access and macros Chunfeng Yun
` (5 preceding siblings ...)
2022-09-20 9:00 ` [PATCH 06/18] phy: mediatek: hdmi: mt2701: use GENMASK and BIT to generate mask and bits Chunfeng Yun
@ 2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 08/18] phy: mediatek: hdmi: mt2701: use common helper to access registers Chunfeng Yun
` (11 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: Chunfeng Yun @ 2022-09-20 9:00 UTC (permalink / raw)
To: Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Chunfeng Yun, Kishon Vijay Abraham I,
Matthias Brugger, dri-devel, linux-mediatek, linux-arm-kernel,
linux-phy, linux-kernel, Jitao Shi, Stanley Chu
Use FIELD_PREP() macro to prepare bits field value, then no need define
macros of bits offset.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c | 60 ++++++++--------------
1 file changed, 21 insertions(+), 39 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
index ce36f37c698d..af6e8ed348cb 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
@@ -7,30 +7,21 @@
#include "phy-mtk-hdmi.h"
#define HDMI_CON0 0x00
-#define RG_HDMITX_DRV_IBIAS 0
#define RG_HDMITX_DRV_IBIAS_MASK GENMASK(5, 0)
-#define RG_HDMITX_EN_SER 12
#define RG_HDMITX_EN_SER_MASK GENMASK(15, 12)
-#define RG_HDMITX_EN_SLDO 16
#define RG_HDMITX_EN_SLDO_MASK GENMASK(19, 16)
-#define RG_HDMITX_EN_PRED 20
#define RG_HDMITX_EN_PRED_MASK GENMASK(23, 20)
-#define RG_HDMITX_EN_IMP 24
#define RG_HDMITX_EN_IMP_MASK GENMASK(27, 24)
-#define RG_HDMITX_EN_DRV 28
#define RG_HDMITX_EN_DRV_MASK GENMASK(31, 28)
#define HDMI_CON1 0x04
-#define RG_HDMITX_PRED_IBIAS 18
#define RG_HDMITX_PRED_IBIAS_MASK GENMASK(21, 18)
#define RG_HDMITX_PRED_IMP BIT(22)
-#define RG_HDMITX_DRV_IMP 26
#define RG_HDMITX_DRV_IMP_MASK GENMASK(31, 26)
#define HDMI_CON2 0x08
#define RG_HDMITX_EN_TX_CKLDO BIT(0)
#define RG_HDMITX_EN_TX_POSDIV BIT(1)
-#define RG_HDMITX_TX_POSDIV 3
#define RG_HDMITX_TX_POSDIV_MASK GENMASK(4, 3)
#define RG_HDMITX_EN_MBIAS BIT(6)
#define RG_HDMITX_MBIAS_LPF_EN BIT(7)
@@ -39,30 +30,20 @@
#define RG_HDMITX_RESERVE_MASK GENMASK(31, 0)
#define HDMI_CON6 0x18
-#define RG_HTPLL_BR 0
#define RG_HTPLL_BR_MASK GENMASK(1, 0)
-#define RG_HTPLL_BC 2
#define RG_HTPLL_BC_MASK GENMASK(3, 2)
-#define RG_HTPLL_BP 4
#define RG_HTPLL_BP_MASK GENMASK(7, 4)
-#define RG_HTPLL_IR 8
#define RG_HTPLL_IR_MASK GENMASK(11, 8)
-#define RG_HTPLL_IC 12
#define RG_HTPLL_IC_MASK GENMASK(15, 12)
-#define RG_HTPLL_POSDIV 16
#define RG_HTPLL_POSDIV_MASK GENMASK(17, 16)
-#define RG_HTPLL_PREDIV 18
#define RG_HTPLL_PREDIV_MASK GENMASK(19, 18)
-#define RG_HTPLL_FBKSEL 20
#define RG_HTPLL_FBKSEL_MASK GENMASK(21, 20)
#define RG_HTPLL_RLH_EN BIT(22)
-#define RG_HTPLL_FBKDIV 24
#define RG_HTPLL_FBKDIV_MASK GENMASK(30, 24)
#define RG_HTPLL_EN BIT(31)
#define HDMI_CON7 0x1c
#define RG_HTPLL_AUTOK_EN BIT(23)
-#define RG_HTPLL_DIVEN 28
#define RG_HTPLL_DIVEN_MASK GENMASK(30, 28)
static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
@@ -128,33 +109,33 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_PREDIV_MASK);
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IC),
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_IC_MASK, 0x1),
RG_HTPLL_IC_MASK);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR),
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_IR_MASK, 0x1),
RG_HTPLL_IR_MASK);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON2, (pos_div << RG_HDMITX_TX_POSDIV),
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON2, FIELD_PREP(RG_HDMITX_TX_POSDIV_MASK, pos_div),
RG_HDMITX_TX_POSDIV_MASK);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (1 << RG_HTPLL_FBKSEL),
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_FBKSEL_MASK, 1),
RG_HTPLL_FBKSEL_MASK);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (19 << RG_HTPLL_FBKDIV),
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_FBKDIV_MASK, 19),
RG_HTPLL_FBKDIV_MASK);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON7, (0x2 << RG_HTPLL_DIVEN),
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON7, FIELD_PREP(RG_HTPLL_DIVEN_MASK, 0x2),
RG_HTPLL_DIVEN_MASK);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0xc << RG_HTPLL_BP),
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_BP_MASK, 0xc),
RG_HTPLL_BP_MASK);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x2 << RG_HTPLL_BC),
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_BC_MASK, 0x2),
RG_HTPLL_BC_MASK);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_BR),
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_BR_MASK, 0x1),
RG_HTPLL_BR_MASK);
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PRED_IMP);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x3 << RG_HDMITX_PRED_IBIAS),
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, FIELD_PREP(RG_HDMITX_PRED_IBIAS_MASK, 0x3),
RG_HDMITX_PRED_IBIAS_MASK);
mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_IMP_MASK);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, (0x28 << RG_HDMITX_DRV_IMP),
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, FIELD_PREP(RG_HDMITX_DRV_IMP_MASK, 0x28),
RG_HDMITX_DRV_IMP_MASK);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, 0x28, RG_HDMITX_RESERVE_MASK);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, (0xa << RG_HDMITX_DRV_IBIAS),
+ mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, FIELD_PREP(RG_HDMITX_DRV_IBIAS_MASK, 0xa),
RG_HDMITX_DRV_IBIAS_MASK);
return 0;
}
@@ -164,9 +145,10 @@ static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
{
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
unsigned long out_rate, val;
+ u32 tmp;
- val = (readl(hdmi_phy->regs + HDMI_CON6)
- & RG_HTPLL_PREDIV_MASK) >> RG_HTPLL_PREDIV;
+ tmp = readl(hdmi_phy->regs + HDMI_CON6);
+ val = FIELD_GET(RG_HTPLL_PREDIV_MASK, tmp);
switch (val) {
case 0x00:
out_rate = parent_rate;
@@ -179,14 +161,14 @@ static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
break;
}
- val = (readl(hdmi_phy->regs + HDMI_CON6)
- & RG_HTPLL_FBKDIV_MASK) >> RG_HTPLL_FBKDIV;
+ val = FIELD_GET(RG_HTPLL_FBKDIV_MASK, tmp);
out_rate *= (val + 1) * 2;
- val = (readl(hdmi_phy->regs + HDMI_CON2)
- & RG_HDMITX_TX_POSDIV_MASK);
- out_rate >>= (val >> RG_HDMITX_TX_POSDIV);
- if (readl(hdmi_phy->regs + HDMI_CON2) & RG_HDMITX_EN_TX_POSDIV)
+ tmp = readl(hdmi_phy->regs + HDMI_CON2);
+ val = FIELD_GET(RG_HDMITX_TX_POSDIV_MASK, tmp);
+ out_rate >>= val;
+
+ if (tmp & RG_HDMITX_EN_TX_POSDIV)
out_rate /= 5;
return out_rate;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH 07/18] phy: mediatek: hdmi: mt2701: use FIELD_PREP to prepare bits field
2022-09-20 9:00 ` [PATCH 07/18] phy: mediatek: hdmi: mt2701: use FIELD_PREP to prepare bits field Chunfeng Yun
@ 2022-09-21 8:13 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-09-21 8:13 UTC (permalink / raw)
To: Chunfeng Yun, Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Kishon Vijay Abraham I, Matthias Brugger,
dri-devel, linux-mediatek, linux-arm-kernel, linux-phy,
linux-kernel, Jitao Shi, Stanley Chu
Il 20/09/22 11:00, Chunfeng Yun ha scritto:
> Use FIELD_PREP() macro to prepare bits field value, then no need define
> macros of bits offset.
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 08/18] phy: mediatek: hdmi: mt2701: use common helper to access registers
2022-09-20 9:00 [PATCH 00/18] unify register access and macros Chunfeng Yun
` (6 preceding siblings ...)
2022-09-20 9:00 ` [PATCH 07/18] phy: mediatek: hdmi: mt2701: use FIELD_PREP to prepare bits field Chunfeng Yun
@ 2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 09/18] phy: mediatek: hdmi: mt8173: use GENMASK to generate bits mask Chunfeng Yun
` (10 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: Chunfeng Yun @ 2022-09-20 9:00 UTC (permalink / raw)
To: Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Chunfeng Yun, Kishon Vijay Abraham I,
Matthias Brugger, dri-devel, linux-mediatek, linux-arm-kernel,
linux-phy, linux-kernel, Jitao Shi, Stanley Chu
Use MediaTek phy's common helper to access registers, then we can remove
hdmi's I/O helpers.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c | 146 ++++++++++-----------
1 file changed, 71 insertions(+), 75 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
index af6e8ed348cb..e51b2d13eab4 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c
@@ -5,6 +5,7 @@
*/
#include "phy-mtk-hdmi.h"
+#include "phy-mtk-io.h"
#define HDMI_CON0 0x00
#define RG_HDMITX_DRV_IBIAS_MASK GENMASK(5, 0)
@@ -49,20 +50,21 @@
static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
{
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
+ void __iomem *base = hdmi_phy->regs;
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
+ mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);
+ mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);
+ mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
+ mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);
usleep_range(80, 100);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
+ mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN);
+ mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
+ mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
usleep_range(80, 100);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
+ mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
+ mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);
+ mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
+ mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
usleep_range(80, 100);
return 0;
}
@@ -70,20 +72,21 @@ static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
{
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
+ void __iomem *base = hdmi_phy->regs;
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
+ mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
+ mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
+ mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);
+ mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
usleep_range(80, 100);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
+ mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
+ mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
+ mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN);
usleep_range(80, 100);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
+ mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);
+ mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
+ mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);
+ mtk_phy_clear_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);
usleep_range(80, 100);
}
@@ -97,6 +100,7 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
+ void __iomem *base = hdmi_phy->regs;
u32 pos_div;
if (rate <= 64000000)
@@ -106,37 +110,25 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
else
pos_div = 1;
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_PREDIV_MASK);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_IC_MASK, 0x1),
- RG_HTPLL_IC_MASK);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_IR_MASK, 0x1),
- RG_HTPLL_IR_MASK);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON2, FIELD_PREP(RG_HDMITX_TX_POSDIV_MASK, pos_div),
- RG_HDMITX_TX_POSDIV_MASK);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_FBKSEL_MASK, 1),
- RG_HTPLL_FBKSEL_MASK);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_FBKDIV_MASK, 19),
- RG_HTPLL_FBKDIV_MASK);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON7, FIELD_PREP(RG_HTPLL_DIVEN_MASK, 0x2),
- RG_HTPLL_DIVEN_MASK);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_BP_MASK, 0xc),
- RG_HTPLL_BP_MASK);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_BC_MASK, 0x2),
- RG_HTPLL_BC_MASK);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, FIELD_PREP(RG_HTPLL_BR_MASK, 0x1),
- RG_HTPLL_BR_MASK);
-
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PRED_IMP);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, FIELD_PREP(RG_HDMITX_PRED_IBIAS_MASK, 0x3),
- RG_HDMITX_PRED_IBIAS_MASK);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_IMP_MASK);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1, FIELD_PREP(RG_HDMITX_DRV_IMP_MASK, 0x28),
- RG_HDMITX_DRV_IMP_MASK);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4, 0x28, RG_HDMITX_RESERVE_MASK);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0, FIELD_PREP(RG_HDMITX_DRV_IBIAS_MASK, 0xa),
- RG_HDMITX_DRV_IBIAS_MASK);
+ mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_PREDIV_MASK);
+ mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
+ mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_POSDIV);
+ mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IC_MASK, 0x1);
+ mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_IR_MASK, 0x1);
+ mtk_phy_update_field(base + HDMI_CON2, RG_HDMITX_TX_POSDIV_MASK, pos_div);
+ mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKSEL_MASK, 1);
+ mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_FBKDIV_MASK, 19);
+ mtk_phy_update_field(base + HDMI_CON7, RG_HTPLL_DIVEN_MASK, 0x2);
+ mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BP_MASK, 0xc);
+ mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BC_MASK, 0x2);
+ mtk_phy_update_field(base + HDMI_CON6, RG_HTPLL_BR_MASK, 0x1);
+
+ mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PRED_IMP);
+ mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PRED_IBIAS_MASK, 0x3);
+ mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_IMP_MASK);
+ mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_DRV_IMP_MASK, 0x28);
+ mtk_phy_update_field(base + HDMI_CON4, RG_HDMITX_RESERVE_MASK, 0x28);
+ mtk_phy_update_field(base + HDMI_CON0, RG_HDMITX_DRV_IBIAS_MASK, 0xa);
return 0;
}
@@ -184,37 +176,41 @@ static const struct clk_ops mtk_hdmi_phy_pll_ops = {
static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
{
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
+ void __iomem *base = hdmi_phy->regs;
+
+ mtk_phy_set_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);
+ mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);
+ mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
+ mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);
usleep_range(80, 100);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
+ mtk_phy_set_bits(base + HDMI_CON6, RG_HTPLL_EN);
+ mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
+ mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
usleep_range(80, 100);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
+ mtk_phy_set_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
+ mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);
+ mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
+ mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
usleep_range(80, 100);
}
static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
{
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SER_MASK);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
+ void __iomem *base = hdmi_phy->regs;
+
+ mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_DRV_MASK);
+ mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_PRED_MASK);
+ mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SER_MASK);
+ mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_MBIAS_LPF_EN);
usleep_range(80, 100);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_EN);
+ mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_EN_SLDO_MASK);
+ mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_TX_CKLDO);
+ mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_EN);
usleep_range(80, 100);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON2, RG_HDMITX_EN_MBIAS);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_POSDIV_MASK);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON6, RG_HTPLL_RLH_EN);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON7, RG_HTPLL_AUTOK_EN);
+ mtk_phy_clear_bits(base + HDMI_CON2, RG_HDMITX_EN_MBIAS);
+ mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_POSDIV_MASK);
+ mtk_phy_clear_bits(base + HDMI_CON6, RG_HTPLL_RLH_EN);
+ mtk_phy_clear_bits(base + HDMI_CON7, RG_HTPLL_AUTOK_EN);
usleep_range(80, 100);
}
--
2.18.0
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH 08/18] phy: mediatek: hdmi: mt2701: use common helper to access registers
2022-09-20 9:00 ` [PATCH 08/18] phy: mediatek: hdmi: mt2701: use common helper to access registers Chunfeng Yun
@ 2022-09-21 8:13 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-09-21 8:13 UTC (permalink / raw)
To: Chunfeng Yun, Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Kishon Vijay Abraham I, Matthias Brugger,
dri-devel, linux-mediatek, linux-arm-kernel, linux-phy,
linux-kernel, Jitao Shi, Stanley Chu
Il 20/09/22 11:00, Chunfeng Yun ha scritto:
> Use MediaTek phy's common helper to access registers, then we can remove
> hdmi's I/O helpers.
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 09/18] phy: mediatek: hdmi: mt8173: use GENMASK to generate bits mask
2022-09-20 9:00 [PATCH 00/18] unify register access and macros Chunfeng Yun
` (7 preceding siblings ...)
2022-09-20 9:00 ` [PATCH 08/18] phy: mediatek: hdmi: mt2701: use common helper to access registers Chunfeng Yun
@ 2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 10/18] phy: mediatek: hdmi: mt8173: use FIELD_PREP to prepare bits field Chunfeng Yun
` (9 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: Chunfeng Yun @ 2022-09-20 9:00 UTC (permalink / raw)
To: Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Chunfeng Yun, Kishon Vijay Abraham I,
Matthias Brugger, dri-devel, linux-mediatek, linux-arm-kernel,
linux-phy, linux-kernel, Jitao Shi, Stanley Chu
Use GENMASK() macro to generate bits mask
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c | 88 +++++++++++-----------
1 file changed, 44 insertions(+), 44 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
index 6cdfdf5a698a..55fe97f5465d 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
@@ -8,38 +8,38 @@
#define HDMI_CON0 0x00
#define RG_HDMITX_PLL_EN BIT(31)
-#define RG_HDMITX_PLL_FBKDIV (0x7f << 24)
+#define RG_HDMITX_PLL_FBKDIV GENMASK(30, 24)
#define PLL_FBKDIV_SHIFT 24
-#define RG_HDMITX_PLL_FBKSEL (0x3 << 22)
+#define RG_HDMITX_PLL_FBKSEL GENMASK(23, 22)
#define PLL_FBKSEL_SHIFT 22
-#define RG_HDMITX_PLL_PREDIV (0x3 << 20)
+#define RG_HDMITX_PLL_PREDIV GENMASK(21, 20)
#define PREDIV_SHIFT 20
-#define RG_HDMITX_PLL_POSDIV (0x3 << 18)
+#define RG_HDMITX_PLL_POSDIV GENMASK(19, 18)
#define POSDIV_SHIFT 18
-#define RG_HDMITX_PLL_RST_DLY (0x3 << 16)
-#define RG_HDMITX_PLL_IR (0xf << 12)
+#define RG_HDMITX_PLL_RST_DLY GENMASK(17, 16)
+#define RG_HDMITX_PLL_IR GENMASK(15, 12)
#define PLL_IR_SHIFT 12
-#define RG_HDMITX_PLL_IC (0xf << 8)
+#define RG_HDMITX_PLL_IC GENMASK(11, 8)
#define PLL_IC_SHIFT 8
-#define RG_HDMITX_PLL_BP (0xf << 4)
+#define RG_HDMITX_PLL_BP GENMASK(7, 4)
#define PLL_BP_SHIFT 4
-#define RG_HDMITX_PLL_BR (0x3 << 2)
+#define RG_HDMITX_PLL_BR GENMASK(3, 2)
#define PLL_BR_SHIFT 2
-#define RG_HDMITX_PLL_BC (0x3 << 0)
+#define RG_HDMITX_PLL_BC GENMASK(1, 0)
#define PLL_BC_SHIFT 0
#define HDMI_CON1 0x04
-#define RG_HDMITX_PLL_DIVEN (0x7 << 29)
+#define RG_HDMITX_PLL_DIVEN GENMASK(31, 29)
#define PLL_DIVEN_SHIFT 29
#define RG_HDMITX_PLL_AUTOK_EN BIT(28)
-#define RG_HDMITX_PLL_AUTOK_KF (0x3 << 26)
-#define RG_HDMITX_PLL_AUTOK_KS (0x3 << 24)
+#define RG_HDMITX_PLL_AUTOK_KF GENMASK(27, 26)
+#define RG_HDMITX_PLL_AUTOK_KS GENMASK(25, 24)
#define RG_HDMITX_PLL_AUTOK_LOAD BIT(23)
-#define RG_HDMITX_PLL_BAND (0x3f << 16)
+#define RG_HDMITX_PLL_BAND GENMASK(21, 16)
#define RG_HDMITX_PLL_REF_SEL BIT(15)
#define RG_HDMITX_PLL_BIAS_EN BIT(14)
#define RG_HDMITX_PLL_BIAS_LPF_EN BIT(13)
#define RG_HDMITX_PLL_TXDIV_EN BIT(12)
-#define RG_HDMITX_PLL_TXDIV (0x3 << 10)
+#define RG_HDMITX_PLL_TXDIV GENMASK(11, 10)
#define PLL_TXDIV_SHIFT 10
#define RG_HDMITX_PLL_LVROD_EN BIT(9)
#define RG_HDMITX_PLL_MONVC_EN BIT(8)
@@ -47,64 +47,64 @@
#define RG_HDMITX_PLL_MONREF_EN BIT(6)
#define RG_HDMITX_PLL_TST_EN BIT(5)
#define RG_HDMITX_PLL_TST_CK_EN BIT(4)
-#define RG_HDMITX_PLL_TST_SEL (0xf << 0)
+#define RG_HDMITX_PLL_TST_SEL GENMASK(3, 0)
#define HDMI_CON2 0x08
-#define RGS_HDMITX_PLL_AUTOK_BAND (0x7f << 8)
+#define RGS_HDMITX_PLL_AUTOK_BAND GENMASK(14, 8)
#define RGS_HDMITX_PLL_AUTOK_FAIL BIT(1)
#define RG_HDMITX_EN_TX_CKLDO BIT(0)
#define HDMI_CON3 0x0c
-#define RG_HDMITX_SER_EN (0xf << 28)
-#define RG_HDMITX_PRD_EN (0xf << 24)
-#define RG_HDMITX_PRD_IMP_EN (0xf << 20)
-#define RG_HDMITX_DRV_EN (0xf << 16)
-#define RG_HDMITX_DRV_IMP_EN (0xf << 12)
+#define RG_HDMITX_SER_EN GENMASK(31, 28)
+#define RG_HDMITX_PRD_EN GENMASK(27, 24)
+#define RG_HDMITX_PRD_IMP_EN GENMASK(23, 20)
+#define RG_HDMITX_DRV_EN GENMASK(19, 16)
+#define RG_HDMITX_DRV_IMP_EN GENMASK(15, 12)
#define DRV_IMP_EN_SHIFT 12
#define RG_HDMITX_MHLCK_FORCE BIT(10)
#define RG_HDMITX_MHLCK_PPIX_EN BIT(9)
#define RG_HDMITX_MHLCK_EN BIT(8)
-#define RG_HDMITX_SER_DIN_SEL (0xf << 4)
+#define RG_HDMITX_SER_DIN_SEL GENMASK(7, 4)
#define RG_HDMITX_SER_5T1_BIST_EN BIT(3)
#define RG_HDMITX_SER_BIST_TOG BIT(2)
#define RG_HDMITX_SER_DIN_TOG BIT(1)
#define RG_HDMITX_SER_CLKDIG_INV BIT(0)
#define HDMI_CON4 0x10
-#define RG_HDMITX_PRD_IBIAS_CLK (0xf << 24)
-#define RG_HDMITX_PRD_IBIAS_D2 (0xf << 16)
-#define RG_HDMITX_PRD_IBIAS_D1 (0xf << 8)
-#define RG_HDMITX_PRD_IBIAS_D0 (0xf << 0)
+#define RG_HDMITX_PRD_IBIAS_CLK GENMASK(27, 24)
+#define RG_HDMITX_PRD_IBIAS_D2 GENMASK(19, 16)
+#define RG_HDMITX_PRD_IBIAS_D1 GENMASK(11, 8)
+#define RG_HDMITX_PRD_IBIAS_D0 GENMASK(3, 0)
#define PRD_IBIAS_CLK_SHIFT 24
#define PRD_IBIAS_D2_SHIFT 16
#define PRD_IBIAS_D1_SHIFT 8
#define PRD_IBIAS_D0_SHIFT 0
#define HDMI_CON5 0x14
-#define RG_HDMITX_DRV_IBIAS_CLK (0x3f << 24)
-#define RG_HDMITX_DRV_IBIAS_D2 (0x3f << 16)
-#define RG_HDMITX_DRV_IBIAS_D1 (0x3f << 8)
-#define RG_HDMITX_DRV_IBIAS_D0 (0x3f << 0)
+#define RG_HDMITX_DRV_IBIAS_CLK GENMASK(29, 24)
+#define RG_HDMITX_DRV_IBIAS_D2 GENMASK(21, 16)
+#define RG_HDMITX_DRV_IBIAS_D1 GENMASK(13, 8)
+#define RG_HDMITX_DRV_IBIAS_D0 GENMASK(5, 0)
#define DRV_IBIAS_CLK_SHIFT 24
#define DRV_IBIAS_D2_SHIFT 16
#define DRV_IBIAS_D1_SHIFT 8
#define DRV_IBIAS_D0_SHIFT 0
#define HDMI_CON6 0x18
-#define RG_HDMITX_DRV_IMP_CLK (0x3f << 24)
-#define RG_HDMITX_DRV_IMP_D2 (0x3f << 16)
-#define RG_HDMITX_DRV_IMP_D1 (0x3f << 8)
-#define RG_HDMITX_DRV_IMP_D0 (0x3f << 0)
+#define RG_HDMITX_DRV_IMP_CLK GENMASK(29, 24)
+#define RG_HDMITX_DRV_IMP_D2 GENMASK(21, 16)
+#define RG_HDMITX_DRV_IMP_D1 GENMASK(13, 8)
+#define RG_HDMITX_DRV_IMP_D0 GENMASK(5, 0)
#define DRV_IMP_CLK_SHIFT 24
#define DRV_IMP_D2_SHIFT 16
#define DRV_IMP_D1_SHIFT 8
#define DRV_IMP_D0_SHIFT 0
#define HDMI_CON7 0x1c
-#define RG_HDMITX_MHLCK_DRV_IBIAS (0x1f << 27)
-#define RG_HDMITX_SER_DIN (0x3ff << 16)
-#define RG_HDMITX_CHLDC_TST (0xf << 12)
-#define RG_HDMITX_CHLCK_TST (0xf << 8)
-#define RG_HDMITX_RESERVE (0xff << 0)
+#define RG_HDMITX_MHLCK_DRV_IBIAS GENMASK(31, 27)
+#define RG_HDMITX_SER_DIN GENMASK(25, 16)
+#define RG_HDMITX_CHLDC_TST GENMASK(15, 12)
+#define RG_HDMITX_CHLCK_TST GENMASK(11, 8)
+#define RG_HDMITX_RESERVE GENMASK(7, 0)
#define HDMI_CON8 0x20
-#define RGS_HDMITX_2T1_LEV (0xf << 16)
-#define RGS_HDMITX_2T1_EDG (0xf << 12)
-#define RGS_HDMITX_5T1_LEV (0xf << 8)
-#define RGS_HDMITX_5T1_EDG (0xf << 4)
+#define RGS_HDMITX_2T1_LEV GENMASK(19, 16)
+#define RGS_HDMITX_2T1_EDG GENMASK(15, 12)
+#define RGS_HDMITX_5T1_LEV GENMASK(11, 8)
+#define RGS_HDMITX_5T1_EDG GENMASK(7, 4)
#define RGS_HDMITX_PLUG_TST BIT(0)
static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
--
2.18.0
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^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH 09/18] phy: mediatek: hdmi: mt8173: use GENMASK to generate bits mask
2022-09-20 9:00 ` [PATCH 09/18] phy: mediatek: hdmi: mt8173: use GENMASK to generate bits mask Chunfeng Yun
@ 2022-09-21 8:13 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-09-21 8:13 UTC (permalink / raw)
To: Chunfeng Yun, Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Kishon Vijay Abraham I, Matthias Brugger,
dri-devel, linux-mediatek, linux-arm-kernel, linux-phy,
linux-kernel, Jitao Shi, Stanley Chu
Il 20/09/22 11:00, Chunfeng Yun ha scritto:
> Use GENMASK() macro to generate bits mask
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 10/18] phy: mediatek: hdmi: mt8173: use FIELD_PREP to prepare bits field
2022-09-20 9:00 [PATCH 00/18] unify register access and macros Chunfeng Yun
` (8 preceding siblings ...)
2022-09-20 9:00 ` [PATCH 09/18] phy: mediatek: hdmi: mt8173: use GENMASK to generate bits mask Chunfeng Yun
@ 2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 11/18] phy: mediatek: hdmi: mt8173: use common helper to access registers Chunfeng Yun
` (8 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: Chunfeng Yun @ 2022-09-20 9:00 UTC (permalink / raw)
To: Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Chunfeng Yun, Kishon Vijay Abraham I,
Matthias Brugger, dri-devel, linux-mediatek, linux-arm-kernel,
linux-phy, linux-kernel, Jitao Shi, Stanley Chu
Use FIELD_PREP() macro to prepare bits field value, then no need define
macros of bits offset.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c | 70 ++++++++--------------
1 file changed, 26 insertions(+), 44 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
index 55fe97f5465d..8f93991fb09d 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
@@ -9,27 +9,17 @@
#define HDMI_CON0 0x00
#define RG_HDMITX_PLL_EN BIT(31)
#define RG_HDMITX_PLL_FBKDIV GENMASK(30, 24)
-#define PLL_FBKDIV_SHIFT 24
#define RG_HDMITX_PLL_FBKSEL GENMASK(23, 22)
-#define PLL_FBKSEL_SHIFT 22
#define RG_HDMITX_PLL_PREDIV GENMASK(21, 20)
-#define PREDIV_SHIFT 20
#define RG_HDMITX_PLL_POSDIV GENMASK(19, 18)
-#define POSDIV_SHIFT 18
#define RG_HDMITX_PLL_RST_DLY GENMASK(17, 16)
#define RG_HDMITX_PLL_IR GENMASK(15, 12)
-#define PLL_IR_SHIFT 12
#define RG_HDMITX_PLL_IC GENMASK(11, 8)
-#define PLL_IC_SHIFT 8
#define RG_HDMITX_PLL_BP GENMASK(7, 4)
-#define PLL_BP_SHIFT 4
#define RG_HDMITX_PLL_BR GENMASK(3, 2)
-#define PLL_BR_SHIFT 2
#define RG_HDMITX_PLL_BC GENMASK(1, 0)
-#define PLL_BC_SHIFT 0
#define HDMI_CON1 0x04
#define RG_HDMITX_PLL_DIVEN GENMASK(31, 29)
-#define PLL_DIVEN_SHIFT 29
#define RG_HDMITX_PLL_AUTOK_EN BIT(28)
#define RG_HDMITX_PLL_AUTOK_KF GENMASK(27, 26)
#define RG_HDMITX_PLL_AUTOK_KS GENMASK(25, 24)
@@ -40,7 +30,6 @@
#define RG_HDMITX_PLL_BIAS_LPF_EN BIT(13)
#define RG_HDMITX_PLL_TXDIV_EN BIT(12)
#define RG_HDMITX_PLL_TXDIV GENMASK(11, 10)
-#define PLL_TXDIV_SHIFT 10
#define RG_HDMITX_PLL_LVROD_EN BIT(9)
#define RG_HDMITX_PLL_MONVC_EN BIT(8)
#define RG_HDMITX_PLL_MONCK_EN BIT(7)
@@ -58,7 +47,6 @@
#define RG_HDMITX_PRD_IMP_EN GENMASK(23, 20)
#define RG_HDMITX_DRV_EN GENMASK(19, 16)
#define RG_HDMITX_DRV_IMP_EN GENMASK(15, 12)
-#define DRV_IMP_EN_SHIFT 12
#define RG_HDMITX_MHLCK_FORCE BIT(10)
#define RG_HDMITX_MHLCK_PPIX_EN BIT(9)
#define RG_HDMITX_MHLCK_EN BIT(8)
@@ -72,28 +60,16 @@
#define RG_HDMITX_PRD_IBIAS_D2 GENMASK(19, 16)
#define RG_HDMITX_PRD_IBIAS_D1 GENMASK(11, 8)
#define RG_HDMITX_PRD_IBIAS_D0 GENMASK(3, 0)
-#define PRD_IBIAS_CLK_SHIFT 24
-#define PRD_IBIAS_D2_SHIFT 16
-#define PRD_IBIAS_D1_SHIFT 8
-#define PRD_IBIAS_D0_SHIFT 0
#define HDMI_CON5 0x14
#define RG_HDMITX_DRV_IBIAS_CLK GENMASK(29, 24)
#define RG_HDMITX_DRV_IBIAS_D2 GENMASK(21, 16)
#define RG_HDMITX_DRV_IBIAS_D1 GENMASK(13, 8)
#define RG_HDMITX_DRV_IBIAS_D0 GENMASK(5, 0)
-#define DRV_IBIAS_CLK_SHIFT 24
-#define DRV_IBIAS_D2_SHIFT 16
-#define DRV_IBIAS_D1_SHIFT 8
-#define DRV_IBIAS_D0_SHIFT 0
#define HDMI_CON6 0x18
#define RG_HDMITX_DRV_IMP_CLK GENMASK(29, 24)
#define RG_HDMITX_DRV_IMP_D2 GENMASK(21, 16)
#define RG_HDMITX_DRV_IMP_D1 GENMASK(13, 8)
#define RG_HDMITX_DRV_IMP_D0 GENMASK(5, 0)
-#define DRV_IMP_CLK_SHIFT 24
-#define DRV_IMP_D2_SHIFT 16
-#define DRV_IMP_D1_SHIFT 8
-#define DRV_IMP_D0_SHIFT 0
#define HDMI_CON7 0x1c
#define RG_HDMITX_MHLCK_DRV_IBIAS GENMASK(31, 27)
#define RG_HDMITX_SER_DIN GENMASK(25, 16)
@@ -178,21 +154,27 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
}
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
- (pre_div << PREDIV_SHIFT), RG_HDMITX_PLL_PREDIV);
+ FIELD_PREP(RG_HDMITX_PLL_PREDIV, pre_div),
+ RG_HDMITX_PLL_PREDIV);
mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
- (0x1 << PLL_IC_SHIFT) | (0x1 << PLL_IR_SHIFT),
+ FIELD_PREP(RG_HDMITX_PLL_IC, 0x1) |
+ FIELD_PREP(RG_HDMITX_PLL_IR, 0x1),
RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
- (div << PLL_TXDIV_SHIFT), RG_HDMITX_PLL_TXDIV);
+ FIELD_PREP(RG_HDMITX_PLL_TXDIV, div),
+ RG_HDMITX_PLL_TXDIV);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
- (0x1 << PLL_FBKSEL_SHIFT) | (19 << PLL_FBKDIV_SHIFT),
+ FIELD_PREP(RG_HDMITX_PLL_FBKSEL, 0x1) |
+ FIELD_PREP(RG_HDMITX_PLL_FBKDIV, 19),
RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
- (0x2 << PLL_DIVEN_SHIFT), RG_HDMITX_PLL_DIVEN);
+ FIELD_PREP(RG_HDMITX_PLL_DIVEN, 0x2),
+ RG_HDMITX_PLL_DIVEN);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
- (0xc << PLL_BP_SHIFT) | (0x2 << PLL_BC_SHIFT) |
- (0x1 << PLL_BR_SHIFT),
+ FIELD_PREP(RG_HDMITX_PLL_BP, 0xc) |
+ FIELD_PREP(RG_HDMITX_PLL_BC, 0x2) |
+ FIELD_PREP(RG_HDMITX_PLL_BR, 0x1),
RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
RG_HDMITX_PLL_BR);
if (rate < 165000000) {
@@ -209,29 +191,29 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
hdmi_ibias = hdmi_phy->ibias_up;
}
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
- (pre_ibias << PRD_IBIAS_CLK_SHIFT) |
- (pre_ibias << PRD_IBIAS_D2_SHIFT) |
- (pre_ibias << PRD_IBIAS_D1_SHIFT) |
- (pre_ibias << PRD_IBIAS_D0_SHIFT),
+ FIELD_PREP(RG_HDMITX_PRD_IBIAS_CLK, pre_ibias) |
+ FIELD_PREP(RG_HDMITX_PRD_IBIAS_D2, pre_ibias) |
+ FIELD_PREP(RG_HDMITX_PRD_IBIAS_D1, pre_ibias) |
+ FIELD_PREP(RG_HDMITX_PRD_IBIAS_D0, pre_ibias),
RG_HDMITX_PRD_IBIAS_CLK |
RG_HDMITX_PRD_IBIAS_D2 |
RG_HDMITX_PRD_IBIAS_D1 |
RG_HDMITX_PRD_IBIAS_D0);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
- (imp_en << DRV_IMP_EN_SHIFT),
+ FIELD_PREP(RG_HDMITX_DRV_IMP_EN, imp_en),
RG_HDMITX_DRV_IMP_EN);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
- (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
- (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
- (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
- (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),
+ FIELD_PREP(RG_HDMITX_DRV_IMP_CLK, hdmi_phy->drv_imp_clk) |
+ FIELD_PREP(RG_HDMITX_DRV_IMP_D2, hdmi_phy->drv_imp_d2) |
+ FIELD_PREP(RG_HDMITX_DRV_IMP_D1, hdmi_phy->drv_imp_d1) |
+ FIELD_PREP(RG_HDMITX_DRV_IMP_D0, hdmi_phy->drv_imp_d0),
RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
- (hdmi_ibias << DRV_IBIAS_CLK_SHIFT) |
- (hdmi_ibias << DRV_IBIAS_D2_SHIFT) |
- (hdmi_ibias << DRV_IBIAS_D1_SHIFT) |
- (hdmi_ibias << DRV_IBIAS_D0_SHIFT),
+ FIELD_PREP(RG_HDMITX_DRV_IBIAS_CLK, hdmi_ibias) |
+ FIELD_PREP(RG_HDMITX_DRV_IBIAS_D2, hdmi_ibias) |
+ FIELD_PREP(RG_HDMITX_DRV_IBIAS_D1, hdmi_ibias) |
+ FIELD_PREP(RG_HDMITX_DRV_IBIAS_D0, hdmi_ibias),
RG_HDMITX_DRV_IBIAS_CLK |
RG_HDMITX_DRV_IBIAS_D2 |
RG_HDMITX_DRV_IBIAS_D1 |
--
2.18.0
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH 10/18] phy: mediatek: hdmi: mt8173: use FIELD_PREP to prepare bits field
2022-09-20 9:00 ` [PATCH 10/18] phy: mediatek: hdmi: mt8173: use FIELD_PREP to prepare bits field Chunfeng Yun
@ 2022-09-21 8:13 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-09-21 8:13 UTC (permalink / raw)
To: Chunfeng Yun, Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Kishon Vijay Abraham I, Matthias Brugger,
dri-devel, linux-mediatek, linux-arm-kernel, linux-phy,
linux-kernel, Jitao Shi, Stanley Chu
Il 20/09/22 11:00, Chunfeng Yun ha scritto:
> Use FIELD_PREP() macro to prepare bits field value, then no need define
> macros of bits offset.
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 11/18] phy: mediatek: hdmi: mt8173: use common helper to access registers
2022-09-20 9:00 [PATCH 00/18] unify register access and macros Chunfeng Yun
` (9 preceding siblings ...)
2022-09-20 9:00 ` [PATCH 10/18] phy: mediatek: hdmi: mt8173: use FIELD_PREP to prepare bits field Chunfeng Yun
@ 2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 12/18] phy: mediatek: hdmi: remove register access helpers Chunfeng Yun
` (7 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: Chunfeng Yun @ 2022-09-20 9:00 UTC (permalink / raw)
To: Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Chunfeng Yun, Kishon Vijay Abraham I,
Matthias Brugger, dri-devel, linux-mediatek, linux-arm-kernel,
linux-phy, linux-kernel, Jitao Shi, Stanley Chu
Use MediaTek phy's common helper to access registers, then we can remove
hdmi's I/O helpers.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c | 140 ++++++++++-----------
1 file changed, 65 insertions(+), 75 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
index 8f93991fb09d..d04758396046 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c
@@ -5,6 +5,7 @@
*/
#include "phy-mtk-hdmi.h"
+#include "phy-mtk-io.h"
#define HDMI_CON0 0x00
#define RG_HDMITX_PLL_EN BIT(31)
@@ -86,16 +87,17 @@
static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
{
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
+ void __iomem *base = hdmi_phy->regs;
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_MHLCK_EN);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
+ mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
+ mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV);
+ mtk_phy_clear_bits(base + HDMI_CON3, RG_HDMITX_MHLCK_EN);
+ mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
usleep_range(100, 150);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
+ mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_EN);
usleep_range(100, 150);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
+ mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
+ mtk_phy_set_bits(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
return 0;
}
@@ -103,15 +105,16 @@ static int mtk_hdmi_pll_prepare(struct clk_hw *hw)
static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)
{
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
+ void __iomem *base = hdmi_phy->regs;
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
+ mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
+ mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
usleep_range(100, 150);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
+ mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_PLL_EN);
usleep_range(100, 150);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
+ mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
+ mtk_phy_clear_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV);
+ mtk_phy_clear_bits(base + HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
usleep_range(100, 150);
}
@@ -133,6 +136,7 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
+ void __iomem *base = hdmi_phy->regs;
unsigned int pre_div;
unsigned int div;
unsigned int pre_ibias;
@@ -153,71 +157,57 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
div = 1;
}
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
- FIELD_PREP(RG_HDMITX_PLL_PREDIV, pre_div),
- RG_HDMITX_PLL_PREDIV);
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
- FIELD_PREP(RG_HDMITX_PLL_IC, 0x1) |
- FIELD_PREP(RG_HDMITX_PLL_IR, 0x1),
- RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
- FIELD_PREP(RG_HDMITX_PLL_TXDIV, div),
- RG_HDMITX_PLL_TXDIV);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
- FIELD_PREP(RG_HDMITX_PLL_FBKSEL, 0x1) |
- FIELD_PREP(RG_HDMITX_PLL_FBKDIV, 19),
- RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
- FIELD_PREP(RG_HDMITX_PLL_DIVEN, 0x2),
- RG_HDMITX_PLL_DIVEN);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
- FIELD_PREP(RG_HDMITX_PLL_BP, 0xc) |
- FIELD_PREP(RG_HDMITX_PLL_BC, 0x2) |
- FIELD_PREP(RG_HDMITX_PLL_BR, 0x1),
- RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
- RG_HDMITX_PLL_BR);
+ mtk_phy_update_field(base + HDMI_CON0, RG_HDMITX_PLL_PREDIV, pre_div);
+ mtk_phy_set_bits(base + HDMI_CON0, RG_HDMITX_PLL_POSDIV);
+ mtk_phy_update_bits(base + HDMI_CON0,
+ RG_HDMITX_PLL_IC | RG_HDMITX_PLL_IR,
+ FIELD_PREP(RG_HDMITX_PLL_IC, 0x1) |
+ FIELD_PREP(RG_HDMITX_PLL_IR, 0x1));
+ mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PLL_TXDIV, div);
+ mtk_phy_update_bits(base + HDMI_CON0,
+ RG_HDMITX_PLL_FBKSEL | RG_HDMITX_PLL_FBKDIV,
+ FIELD_PREP(RG_HDMITX_PLL_FBKSEL, 0x1) |
+ FIELD_PREP(RG_HDMITX_PLL_FBKDIV, 19));
+ mtk_phy_update_field(base + HDMI_CON1, RG_HDMITX_PLL_DIVEN, 0x2);
+ mtk_phy_update_bits(base + HDMI_CON0,
+ RG_HDMITX_PLL_BP | RG_HDMITX_PLL_BC |
+ RG_HDMITX_PLL_BR,
+ FIELD_PREP(RG_HDMITX_PLL_BP, 0xc) |
+ FIELD_PREP(RG_HDMITX_PLL_BC, 0x2) |
+ FIELD_PREP(RG_HDMITX_PLL_BR, 0x1));
if (rate < 165000000) {
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
- RG_HDMITX_PRD_IMP_EN);
+ mtk_phy_clear_bits(base + HDMI_CON3, RG_HDMITX_PRD_IMP_EN);
pre_ibias = 0x3;
imp_en = 0x0;
hdmi_ibias = hdmi_phy->ibias;
} else {
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
- RG_HDMITX_PRD_IMP_EN);
+ mtk_phy_set_bits(base + HDMI_CON3, RG_HDMITX_PRD_IMP_EN);
pre_ibias = 0x6;
imp_en = 0xf;
hdmi_ibias = hdmi_phy->ibias_up;
}
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
- FIELD_PREP(RG_HDMITX_PRD_IBIAS_CLK, pre_ibias) |
- FIELD_PREP(RG_HDMITX_PRD_IBIAS_D2, pre_ibias) |
- FIELD_PREP(RG_HDMITX_PRD_IBIAS_D1, pre_ibias) |
- FIELD_PREP(RG_HDMITX_PRD_IBIAS_D0, pre_ibias),
- RG_HDMITX_PRD_IBIAS_CLK |
- RG_HDMITX_PRD_IBIAS_D2 |
- RG_HDMITX_PRD_IBIAS_D1 |
- RG_HDMITX_PRD_IBIAS_D0);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
- FIELD_PREP(RG_HDMITX_DRV_IMP_EN, imp_en),
- RG_HDMITX_DRV_IMP_EN);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
- FIELD_PREP(RG_HDMITX_DRV_IMP_CLK, hdmi_phy->drv_imp_clk) |
- FIELD_PREP(RG_HDMITX_DRV_IMP_D2, hdmi_phy->drv_imp_d2) |
- FIELD_PREP(RG_HDMITX_DRV_IMP_D1, hdmi_phy->drv_imp_d1) |
- FIELD_PREP(RG_HDMITX_DRV_IMP_D0, hdmi_phy->drv_imp_d0),
- RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
- RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0);
- mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
- FIELD_PREP(RG_HDMITX_DRV_IBIAS_CLK, hdmi_ibias) |
- FIELD_PREP(RG_HDMITX_DRV_IBIAS_D2, hdmi_ibias) |
- FIELD_PREP(RG_HDMITX_DRV_IBIAS_D1, hdmi_ibias) |
- FIELD_PREP(RG_HDMITX_DRV_IBIAS_D0, hdmi_ibias),
- RG_HDMITX_DRV_IBIAS_CLK |
- RG_HDMITX_DRV_IBIAS_D2 |
- RG_HDMITX_DRV_IBIAS_D1 |
- RG_HDMITX_DRV_IBIAS_D0);
+ mtk_phy_update_bits(base + HDMI_CON4,
+ RG_HDMITX_PRD_IBIAS_CLK | RG_HDMITX_PRD_IBIAS_D2 |
+ RG_HDMITX_PRD_IBIAS_D1 | RG_HDMITX_PRD_IBIAS_D0,
+ FIELD_PREP(RG_HDMITX_PRD_IBIAS_CLK, pre_ibias) |
+ FIELD_PREP(RG_HDMITX_PRD_IBIAS_D2, pre_ibias) |
+ FIELD_PREP(RG_HDMITX_PRD_IBIAS_D1, pre_ibias) |
+ FIELD_PREP(RG_HDMITX_PRD_IBIAS_D0, pre_ibias));
+ mtk_phy_update_field(base + HDMI_CON3, RG_HDMITX_DRV_IMP_EN, imp_en);
+ mtk_phy_update_bits(base + HDMI_CON6,
+ RG_HDMITX_DRV_IMP_CLK | RG_HDMITX_DRV_IMP_D2 |
+ RG_HDMITX_DRV_IMP_D1 | RG_HDMITX_DRV_IMP_D0,
+ FIELD_PREP(RG_HDMITX_DRV_IMP_CLK, hdmi_phy->drv_imp_clk) |
+ FIELD_PREP(RG_HDMITX_DRV_IMP_D2, hdmi_phy->drv_imp_d2) |
+ FIELD_PREP(RG_HDMITX_DRV_IMP_D1, hdmi_phy->drv_imp_d1) |
+ FIELD_PREP(RG_HDMITX_DRV_IMP_D0, hdmi_phy->drv_imp_d0));
+ mtk_phy_update_bits(base + HDMI_CON5,
+ RG_HDMITX_DRV_IBIAS_CLK | RG_HDMITX_DRV_IBIAS_D2 |
+ RG_HDMITX_DRV_IBIAS_D1 | RG_HDMITX_DRV_IBIAS_D0,
+ FIELD_PREP(RG_HDMITX_DRV_IBIAS_CLK, hdmi_ibias) |
+ FIELD_PREP(RG_HDMITX_DRV_IBIAS_D2, hdmi_ibias) |
+ FIELD_PREP(RG_HDMITX_DRV_IBIAS_D1, hdmi_ibias) |
+ FIELD_PREP(RG_HDMITX_DRV_IBIAS_D0, hdmi_ibias));
return 0;
}
@@ -239,17 +229,17 @@ static const struct clk_ops mtk_hdmi_phy_pll_ops = {
static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
{
- mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
- RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN |
- RG_HDMITX_DRV_EN);
+ mtk_phy_set_bits(hdmi_phy->regs + HDMI_CON3,
+ RG_HDMITX_SER_EN | RG_HDMITX_PRD_EN |
+ RG_HDMITX_DRV_EN);
usleep_range(100, 150);
}
static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
{
- mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
- RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN |
- RG_HDMITX_SER_EN);
+ mtk_phy_clear_bits(hdmi_phy->regs + HDMI_CON3,
+ RG_HDMITX_DRV_EN | RG_HDMITX_PRD_EN |
+ RG_HDMITX_SER_EN);
}
struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = {
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH 11/18] phy: mediatek: hdmi: mt8173: use common helper to access registers
2022-09-20 9:00 ` [PATCH 11/18] phy: mediatek: hdmi: mt8173: use common helper to access registers Chunfeng Yun
@ 2022-09-21 8:14 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-09-21 8:14 UTC (permalink / raw)
To: Chunfeng Yun, Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Kishon Vijay Abraham I, Matthias Brugger,
dri-devel, linux-mediatek, linux-arm-kernel, linux-phy,
linux-kernel, Jitao Shi, Stanley Chu
Il 20/09/22 11:00, Chunfeng Yun ha scritto:
> Use MediaTek phy's common helper to access registers, then we can remove
> hdmi's I/O helpers.
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 12/18] phy: mediatek: hdmi: remove register access helpers
2022-09-20 9:00 [PATCH 00/18] unify register access and macros Chunfeng Yun
` (10 preceding siblings ...)
2022-09-20 9:00 ` [PATCH 11/18] phy: mediatek: hdmi: mt8173: use common helper to access registers Chunfeng Yun
@ 2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 13/18] phy: mediatek: mipi: mt8173: use GENMASK to generate bits mask Chunfeng Yun
` (6 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: Chunfeng Yun @ 2022-09-20 9:00 UTC (permalink / raw)
To: Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Chunfeng Yun, Kishon Vijay Abraham I,
Matthias Brugger, dri-devel, linux-mediatek, linux-arm-kernel,
linux-phy, linux-kernel, Jitao Shi, Stanley Chu
Remove private register access helpers, use the common ones instead.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/phy/mediatek/phy-mtk-hdmi.c | 33 -----------------------------
drivers/phy/mediatek/phy-mtk-hdmi.h | 7 ------
2 files changed, 40 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.c b/drivers/phy/mediatek/phy-mtk-hdmi.c
index d4bd419abc3c..b16d437d6721 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi.c
@@ -15,39 +15,6 @@ static const struct phy_ops mtk_hdmi_phy_dev_ops = {
.owner = THIS_MODULE,
};
-void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
- u32 bits)
-{
- void __iomem *reg = hdmi_phy->regs + offset;
- u32 tmp;
-
- tmp = readl(reg);
- tmp &= ~bits;
- writel(tmp, reg);
-}
-
-void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
- u32 bits)
-{
- void __iomem *reg = hdmi_phy->regs + offset;
- u32 tmp;
-
- tmp = readl(reg);
- tmp |= bits;
- writel(tmp, reg);
-}
-
-void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
- u32 val, u32 mask)
-{
- void __iomem *reg = hdmi_phy->regs + offset;
- u32 tmp;
-
- tmp = readl(reg);
- tmp = (tmp & ~mask) | (val & mask);
- writel(tmp, reg);
-}
-
inline struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw)
{
return container_of(hw, struct mtk_hdmi_phy, pll_hw);
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.h b/drivers/phy/mediatek/phy-mtk-hdmi.h
index dcf9bb13699b..c7fa65cff989 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi.h
+++ b/drivers/phy/mediatek/phy-mtk-hdmi.h
@@ -9,7 +9,6 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
-#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_device.h>
@@ -42,12 +41,6 @@ struct mtk_hdmi_phy {
unsigned int ibias_up;
};
-void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
- u32 bits);
-void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
- u32 bits);
-void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
- u32 val, u32 mask);
struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw);
extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH 12/18] phy: mediatek: hdmi: remove register access helpers
2022-09-20 9:00 ` [PATCH 12/18] phy: mediatek: hdmi: remove register access helpers Chunfeng Yun
@ 2022-09-21 8:13 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-09-21 8:13 UTC (permalink / raw)
To: Chunfeng Yun, Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Kishon Vijay Abraham I, Matthias Brugger,
dri-devel, linux-mediatek, linux-arm-kernel, linux-phy,
linux-kernel, Jitao Shi, Stanley Chu
Il 20/09/22 11:00, Chunfeng Yun ha scritto:
> Remove private register access helpers, use the common ones instead.
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 13/18] phy: mediatek: mipi: mt8173: use GENMASK to generate bits mask
2022-09-20 9:00 [PATCH 00/18] unify register access and macros Chunfeng Yun
` (11 preceding siblings ...)
2022-09-20 9:00 ` [PATCH 12/18] phy: mediatek: hdmi: remove register access helpers Chunfeng Yun
@ 2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:13 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 14/18] phy: mediatek: mipi: mt8173: use FIELD_PREP to prepare bits field Chunfeng Yun
` (5 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: Chunfeng Yun @ 2022-09-20 9:00 UTC (permalink / raw)
To: Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Chunfeng Yun, Kishon Vijay Abraham I,
Matthias Brugger, dri-devel, linux-mediatek, linux-arm-kernel,
linux-phy, linux-kernel, Jitao Shi, Stanley Chu
Use GENMASK() macro to generate bits mask
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
.../phy/mediatek/phy-mtk-mipi-dsi-mt8173.c | 53 ++++++++++---------
1 file changed, 29 insertions(+), 24 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
index 7a847954594f..5c257d67d7be 100644
--- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
+++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
@@ -9,9 +9,9 @@
#define MIPITX_DSI_CON 0x00
#define RG_DSI_LDOCORE_EN BIT(0)
#define RG_DSI_CKG_LDOOUT_EN BIT(1)
-#define RG_DSI_BCLK_SEL (3 << 2)
-#define RG_DSI_LD_IDX_SEL (7 << 4)
-#define RG_DSI_PHYCLK_SEL (2 << 8)
+#define RG_DSI_BCLK_SEL GENMASK(3, 2)
+#define RG_DSI_LD_IDX_SEL GENMASK(6, 4)
+#define RG_DSI_PHYCLK_SEL GENMASK(9, 8)
#define RG_DSI_DSICLK_FREQ_SEL BIT(10)
#define RG_DSI_LPTX_CLMP_EN BIT(11)
@@ -27,41 +27,46 @@
#define RG_DSI_LNTx_LPTX_IMINUS BIT(4)
#define RG_DSI_LNTx_LPCD_IPLUS BIT(5)
#define RG_DSI_LNTx_LPCD_IMINUS BIT(6)
-#define RG_DSI_LNTx_RT_CODE (0xf << 8)
+#define RG_DSI_LNTx_RT_CODE GENMASK(11, 8)
#define MIPITX_DSI_TOP_CON 0x40
#define RG_DSI_LNT_INTR_EN BIT(0)
#define RG_DSI_LNT_HS_BIAS_EN BIT(1)
#define RG_DSI_LNT_IMP_CAL_EN BIT(2)
#define RG_DSI_LNT_TESTMODE_EN BIT(3)
-#define RG_DSI_LNT_IMP_CAL_CODE (0xf << 4)
-#define RG_DSI_LNT_AIO_SEL (7 << 8)
+#define RG_DSI_LNT_IMP_CAL_CODE GENMASK(7, 4)
+#define RG_DSI_LNT_AIO_SEL GENMASK(10, 8)
#define RG_DSI_PAD_TIE_LOW_EN BIT(11)
#define RG_DSI_DEBUG_INPUT_EN BIT(12)
-#define RG_DSI_PRESERVE (7 << 13)
+#define RG_DSI_PRESERVE GENMASK(15, 13)
#define MIPITX_DSI_BG_CON 0x44
#define RG_DSI_BG_CORE_EN BIT(0)
#define RG_DSI_BG_CKEN BIT(1)
-#define RG_DSI_BG_DIV (0x3 << 2)
+#define RG_DSI_BG_DIV GENMASK(3, 2)
#define RG_DSI_BG_FAST_CHARGE BIT(4)
-#define RG_DSI_VOUT_MSK (0x3ffff << 5)
-#define RG_DSI_V12_SEL (7 << 5)
-#define RG_DSI_V10_SEL (7 << 8)
-#define RG_DSI_V072_SEL (7 << 11)
-#define RG_DSI_V04_SEL (7 << 14)
-#define RG_DSI_V032_SEL (7 << 17)
-#define RG_DSI_V02_SEL (7 << 20)
-#define RG_DSI_BG_R1_TRIM (0xf << 24)
-#define RG_DSI_BG_R2_TRIM (0xf << 28)
+
+#define RG_DSI_V12_SEL GENMASK(7, 5)
+#define RG_DSI_V10_SEL GENMASK(10, 8)
+#define RG_DSI_V072_SEL GENMASK(13, 11)
+#define RG_DSI_V04_SEL GENMASK(16, 14)
+#define RG_DSI_V032_SEL GENMASK(19, 17)
+#define RG_DSI_V02_SEL GENMASK(22, 20)
+#define RG_DSI_VOUT_MSK \
+ (RG_DSI_V12_SEL | RG_DSI_V10_SEL | RG_DSI_V072_SEL | \
+ RG_DSI_V04_SEL | RG_DSI_V032_SEL | RG_DSI_V02_SEL)
+#define RG_DSI_BG_R1_TRIM GENMASK(27, 24)
+#define RG_DSI_BG_R2_TRIM GENMASK(31, 28)
#define MIPITX_DSI_PLL_CON0 0x50
#define RG_DSI_MPPLL_PLL_EN BIT(0)
-#define RG_DSI_MPPLL_DIV_MSK (0x1ff << 1)
-#define RG_DSI_MPPLL_PREDIV (3 << 1)
-#define RG_DSI_MPPLL_TXDIV0 (3 << 3)
-#define RG_DSI_MPPLL_TXDIV1 (3 << 5)
-#define RG_DSI_MPPLL_POSDIV (7 << 7)
+#define RG_DSI_MPPLL_PREDIV GENMASK(2, 1)
+#define RG_DSI_MPPLL_TXDIV0 GENMASK(4, 3)
+#define RG_DSI_MPPLL_TXDIV1 GENMASK(6, 5)
+#define RG_DSI_MPPLL_POSDIV GENMASK(9, 7)
+#define RG_DSI_MPPLL_DIV_MSK \
+ (RG_DSI_MPPLL_PREDIV | RG_DSI_MPPLL_TXDIV0 | \
+ RG_DSI_MPPLL_TXDIV1 | RG_DSI_MPPLL_POSDIV)
#define RG_DSI_MPPLL_MONVC_EN BIT(10)
#define RG_DSI_MPPLL_MONREF_EN BIT(11)
#define RG_DSI_MPPLL_VOD_EN BIT(12)
@@ -70,12 +75,12 @@
#define RG_DSI_MPPLL_SDM_FRA_EN BIT(0)
#define RG_DSI_MPPLL_SDM_SSC_PH_INIT BIT(1)
#define RG_DSI_MPPLL_SDM_SSC_EN BIT(2)
-#define RG_DSI_MPPLL_SDM_SSC_PRD (0xffff << 16)
+#define RG_DSI_MPPLL_SDM_SSC_PRD GENMASK(31, 16)
#define MIPITX_DSI_PLL_CON2 0x58
#define MIPITX_DSI_PLL_TOP 0x64
-#define RG_DSI_MPPLL_PRESERVE (0xff << 8)
+#define RG_DSI_MPPLL_PRESERVE GENMASK(15, 8)
#define MIPITX_DSI_PLL_PWR 0x68
#define RG_DSI_MPPLL_SDM_PWR_ON BIT(0)
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH 13/18] phy: mediatek: mipi: mt8173: use GENMASK to generate bits mask
2022-09-20 9:00 ` [PATCH 13/18] phy: mediatek: mipi: mt8173: use GENMASK to generate bits mask Chunfeng Yun
@ 2022-09-21 8:13 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-09-21 8:13 UTC (permalink / raw)
To: Chunfeng Yun, Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Kishon Vijay Abraham I, Matthias Brugger,
dri-devel, linux-mediatek, linux-arm-kernel, linux-phy,
linux-kernel, Jitao Shi, Stanley Chu
Il 20/09/22 11:00, Chunfeng Yun ha scritto:
> Use GENMASK() macro to generate bits mask
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 14/18] phy: mediatek: mipi: mt8173: use FIELD_PREP to prepare bits field
2022-09-20 9:00 [PATCH 00/18] unify register access and macros Chunfeng Yun
` (12 preceding siblings ...)
2022-09-20 9:00 ` [PATCH 13/18] phy: mediatek: mipi: mt8173: use GENMASK to generate bits mask Chunfeng Yun
@ 2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 15/18] phy: mediatek: mipi: mt8173: use common helper to access registers Chunfeng Yun
` (4 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: Chunfeng Yun @ 2022-09-20 9:00 UTC (permalink / raw)
To: Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Chunfeng Yun, Kishon Vijay Abraham I,
Matthias Brugger, dri-devel, linux-mediatek, linux-arm-kernel,
linux-phy, linux-kernel, Jitao Shi, Stanley Chu
Use FIELD_PREP() macro to prepare bits field value, then no need define
macros of bits offset.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
index 5c257d67d7be..1e2ad617e8e3 100644
--- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
+++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
@@ -153,15 +153,20 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_BG_CON,
RG_DSI_VOUT_MSK |
RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN,
- (4 << 20) | (4 << 17) | (4 << 14) |
- (4 << 11) | (4 << 8) | (4 << 5) |
+ FIELD_PREP(RG_DSI_V02_SEL, 4) |
+ FIELD_PREP(RG_DSI_V032_SEL, 4) |
+ FIELD_PREP(RG_DSI_V04_SEL, 4) |
+ FIELD_PREP(RG_DSI_V072_SEL, 4) |
+ FIELD_PREP(RG_DSI_V10_SEL, 4) |
+ FIELD_PREP(RG_DSI_V12_SEL, 4) |
RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN);
usleep_range(30, 100);
mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_TOP_CON,
RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN,
- (8 << 4) | RG_DSI_LNT_HS_BIAS_EN);
+ FIELD_PREP(RG_DSI_LNT_IMP_CAL_CODE, 8) |
+ RG_DSI_LNT_HS_BIAS_EN);
mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_CON,
RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN);
@@ -177,7 +182,8 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
RG_DSI_MPPLL_TXDIV0 | RG_DSI_MPPLL_TXDIV1 |
RG_DSI_MPPLL_PREDIV,
- (txdiv0 << 3) | (txdiv1 << 5));
+ FIELD_PREP(RG_DSI_MPPLL_TXDIV0, txdiv0) |
+ FIELD_PREP(RG_DSI_MPPLL_TXDIV1, txdiv1));
/*
* PLL PCW config
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH 14/18] phy: mediatek: mipi: mt8173: use FIELD_PREP to prepare bits field
2022-09-20 9:00 ` [PATCH 14/18] phy: mediatek: mipi: mt8173: use FIELD_PREP to prepare bits field Chunfeng Yun
@ 2022-09-21 8:14 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-09-21 8:14 UTC (permalink / raw)
To: Chunfeng Yun, Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Kishon Vijay Abraham I, Matthias Brugger,
dri-devel, linux-mediatek, linux-arm-kernel, linux-phy,
linux-kernel, Jitao Shi, Stanley Chu
Il 20/09/22 11:00, Chunfeng Yun ha scritto:
> Use FIELD_PREP() macro to prepare bits field value, then no need define
> macros of bits offset.
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 15/18] phy: mediatek: mipi: mt8173: use common helper to access registers
2022-09-20 9:00 [PATCH 00/18] unify register access and macros Chunfeng Yun
` (13 preceding siblings ...)
2022-09-20 9:00 ` [PATCH 14/18] phy: mediatek: mipi: mt8173: use FIELD_PREP to prepare bits field Chunfeng Yun
@ 2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 16/18] phy: mediatek: mipi: mt8183: use GENMASK to generate bits mask Chunfeng Yun
` (3 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: Chunfeng Yun @ 2022-09-20 9:00 UTC (permalink / raw)
To: Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Chunfeng Yun, Kishon Vijay Abraham I,
Matthias Brugger, dri-devel, linux-mediatek, linux-arm-kernel,
linux-phy, linux-kernel, Jitao Shi, Stanley Chu
Use MediaTek phy's common helper to access registers, then we can remove
mipi-dsi's I/O helpers.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
.../phy/mediatek/phy-mtk-mipi-dsi-mt8173.c | 117 ++++++++----------
1 file changed, 55 insertions(+), 62 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
index 1e2ad617e8e3..673cb0f08959 100644
--- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
+++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c
@@ -4,6 +4,7 @@
* Author: jitao.shi <jitao.shi@mediatek.com>
*/
+#include "phy-mtk-io.h"
#include "phy-mtk-mipi-dsi.h"
#define MIPITX_DSI_CON 0x00
@@ -121,6 +122,7 @@
static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
{
struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
+ void __iomem *base = mipi_tx->regs;
u8 txdiv, txdiv0, txdiv1;
u64 pcw;
@@ -150,40 +152,38 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
return -EINVAL;
}
- mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_BG_CON,
- RG_DSI_VOUT_MSK |
- RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN,
- FIELD_PREP(RG_DSI_V02_SEL, 4) |
- FIELD_PREP(RG_DSI_V032_SEL, 4) |
- FIELD_PREP(RG_DSI_V04_SEL, 4) |
- FIELD_PREP(RG_DSI_V072_SEL, 4) |
- FIELD_PREP(RG_DSI_V10_SEL, 4) |
- FIELD_PREP(RG_DSI_V12_SEL, 4) |
- RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN);
+ mtk_phy_update_bits(base + MIPITX_DSI_BG_CON,
+ RG_DSI_VOUT_MSK | RG_DSI_BG_CKEN |
+ RG_DSI_BG_CORE_EN,
+ FIELD_PREP(RG_DSI_V02_SEL, 4) |
+ FIELD_PREP(RG_DSI_V032_SEL, 4) |
+ FIELD_PREP(RG_DSI_V04_SEL, 4) |
+ FIELD_PREP(RG_DSI_V072_SEL, 4) |
+ FIELD_PREP(RG_DSI_V10_SEL, 4) |
+ FIELD_PREP(RG_DSI_V12_SEL, 4) |
+ RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN);
usleep_range(30, 100);
- mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_TOP_CON,
- RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN,
- FIELD_PREP(RG_DSI_LNT_IMP_CAL_CODE, 8) |
- RG_DSI_LNT_HS_BIAS_EN);
+ mtk_phy_update_bits(base + MIPITX_DSI_TOP_CON,
+ RG_DSI_LNT_IMP_CAL_CODE | RG_DSI_LNT_HS_BIAS_EN,
+ FIELD_PREP(RG_DSI_LNT_IMP_CAL_CODE, 8) |
+ RG_DSI_LNT_HS_BIAS_EN);
- mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_CON,
- RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN);
+ mtk_phy_set_bits(base + MIPITX_DSI_CON,
+ RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN);
- mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR,
- RG_DSI_MPPLL_SDM_PWR_ON |
- RG_DSI_MPPLL_SDM_ISO_EN,
- RG_DSI_MPPLL_SDM_PWR_ON);
+ mtk_phy_update_bits(base + MIPITX_DSI_PLL_PWR,
+ RG_DSI_MPPLL_SDM_PWR_ON | RG_DSI_MPPLL_SDM_ISO_EN,
+ RG_DSI_MPPLL_SDM_PWR_ON);
- mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
- RG_DSI_MPPLL_PLL_EN);
+ mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN);
- mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
- RG_DSI_MPPLL_TXDIV0 | RG_DSI_MPPLL_TXDIV1 |
- RG_DSI_MPPLL_PREDIV,
- FIELD_PREP(RG_DSI_MPPLL_TXDIV0, txdiv0) |
- FIELD_PREP(RG_DSI_MPPLL_TXDIV1, txdiv1));
+ mtk_phy_update_bits(base + MIPITX_DSI_PLL_CON0,
+ RG_DSI_MPPLL_TXDIV0 | RG_DSI_MPPLL_TXDIV1 |
+ RG_DSI_MPPLL_PREDIV,
+ FIELD_PREP(RG_DSI_MPPLL_TXDIV0, txdiv0) |
+ FIELD_PREP(RG_DSI_MPPLL_TXDIV1, txdiv1));
/*
* PLL PCW config
@@ -193,23 +193,20 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
* Post DIV =4, so need data_Rate*4
* Ref_clk is 26MHz
*/
- pcw = div_u64(((u64)mipi_tx->data_rate * 2 * txdiv) << 24,
- 26000000);
- writel(pcw, mipi_tx->regs + MIPITX_DSI_PLL_CON2);
+ pcw = div_u64(((u64)mipi_tx->data_rate * 2 * txdiv) << 24, 26000000);
+ writel(pcw, base + MIPITX_DSI_PLL_CON2);
- mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON1,
- RG_DSI_MPPLL_SDM_FRA_EN);
+ mtk_phy_set_bits(base + MIPITX_DSI_PLL_CON1, RG_DSI_MPPLL_SDM_FRA_EN);
- mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN);
+ mtk_phy_set_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN);
usleep_range(20, 100);
- mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON1,
- RG_DSI_MPPLL_SDM_SSC_EN);
+ mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON1, RG_DSI_MPPLL_SDM_SSC_EN);
- mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP,
- RG_DSI_MPPLL_PRESERVE,
- mipi_tx->driver_data->mppll_preserve);
+ mtk_phy_update_field(base + MIPITX_DSI_PLL_TOP,
+ RG_DSI_MPPLL_PRESERVE,
+ mipi_tx->driver_data->mppll_preserve);
return 0;
}
@@ -217,31 +214,27 @@ static int mtk_mipi_tx_pll_prepare(struct clk_hw *hw)
static void mtk_mipi_tx_pll_unprepare(struct clk_hw *hw)
{
struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
+ void __iomem *base = mipi_tx->regs;
dev_dbg(mipi_tx->dev, "unprepare\n");
- mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
- RG_DSI_MPPLL_PLL_EN);
+ mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_PLL_EN);
- mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_TOP,
- RG_DSI_MPPLL_PRESERVE, 0);
+ mtk_phy_clear_bits(base + MIPITX_DSI_PLL_TOP, RG_DSI_MPPLL_PRESERVE);
- mtk_mipi_tx_update_bits(mipi_tx, MIPITX_DSI_PLL_PWR,
- RG_DSI_MPPLL_SDM_ISO_EN |
- RG_DSI_MPPLL_SDM_PWR_ON,
- RG_DSI_MPPLL_SDM_ISO_EN);
+ mtk_phy_update_bits(base + MIPITX_DSI_PLL_PWR,
+ RG_DSI_MPPLL_SDM_ISO_EN | RG_DSI_MPPLL_SDM_PWR_ON,
+ RG_DSI_MPPLL_SDM_ISO_EN);
- mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_TOP_CON,
- RG_DSI_LNT_HS_BIAS_EN);
+ mtk_phy_clear_bits(base + MIPITX_DSI_TOP_CON, RG_DSI_LNT_HS_BIAS_EN);
- mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_CON,
- RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN);
+ mtk_phy_clear_bits(base + MIPITX_DSI_CON,
+ RG_DSI_CKG_LDOOUT_EN | RG_DSI_LDOCORE_EN);
- mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_BG_CON,
- RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN);
+ mtk_phy_clear_bits(base + MIPITX_DSI_BG_CON,
+ RG_DSI_BG_CKEN | RG_DSI_BG_CORE_EN);
- mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_PLL_CON0,
- RG_DSI_MPPLL_DIV_MSK);
+ mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_DIV_MSK);
}
static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
@@ -265,10 +258,10 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy)
for (reg = MIPITX_DSI_CLOCK_LANE;
reg <= MIPITX_DSI_DATA_LANE3; reg += 4)
- mtk_mipi_tx_set_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN);
+ mtk_phy_set_bits(mipi_tx->regs + reg, RG_DSI_LNTx_LDOOUT_EN);
- mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_DSI_TOP_CON,
- RG_DSI_PAD_TIE_LOW_EN);
+ mtk_phy_clear_bits(mipi_tx->regs + MIPITX_DSI_TOP_CON,
+ RG_DSI_PAD_TIE_LOW_EN);
}
static void mtk_mipi_tx_power_off_signal(struct phy *phy)
@@ -276,23 +269,23 @@ static void mtk_mipi_tx_power_off_signal(struct phy *phy)
struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
u32 reg;
- mtk_mipi_tx_set_bits(mipi_tx, MIPITX_DSI_TOP_CON,
- RG_DSI_PAD_TIE_LOW_EN);
+ mtk_phy_set_bits(mipi_tx->regs + MIPITX_DSI_TOP_CON,
+ RG_DSI_PAD_TIE_LOW_EN);
for (reg = MIPITX_DSI_CLOCK_LANE;
reg <= MIPITX_DSI_DATA_LANE3; reg += 4)
- mtk_mipi_tx_clear_bits(mipi_tx, reg, RG_DSI_LNTx_LDOOUT_EN);
+ mtk_phy_clear_bits(mipi_tx->regs + reg, RG_DSI_LNTx_LDOOUT_EN);
}
const struct mtk_mipitx_data mt2701_mipitx_data = {
- .mppll_preserve = (3 << 8),
+ .mppll_preserve = 3,
.mipi_tx_clk_ops = &mtk_mipi_tx_pll_ops,
.mipi_tx_enable_signal = mtk_mipi_tx_power_on_signal,
.mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal,
};
const struct mtk_mipitx_data mt8173_mipitx_data = {
- .mppll_preserve = (0 << 8),
+ .mppll_preserve = 0,
.mipi_tx_clk_ops = &mtk_mipi_tx_pll_ops,
.mipi_tx_enable_signal = mtk_mipi_tx_power_on_signal,
.mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal,
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH 15/18] phy: mediatek: mipi: mt8173: use common helper to access registers
2022-09-20 9:00 ` [PATCH 15/18] phy: mediatek: mipi: mt8173: use common helper to access registers Chunfeng Yun
@ 2022-09-21 8:14 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-09-21 8:14 UTC (permalink / raw)
To: Chunfeng Yun, Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Kishon Vijay Abraham I, Matthias Brugger,
dri-devel, linux-mediatek, linux-arm-kernel, linux-phy,
linux-kernel, Jitao Shi, Stanley Chu
Il 20/09/22 11:00, Chunfeng Yun ha scritto:
> Use MediaTek phy's common helper to access registers, then we can remove
> mipi-dsi's I/O helpers.
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 16/18] phy: mediatek: mipi: mt8183: use GENMASK to generate bits mask
2022-09-20 9:00 [PATCH 00/18] unify register access and macros Chunfeng Yun
` (14 preceding siblings ...)
2022-09-20 9:00 ` [PATCH 15/18] phy: mediatek: mipi: mt8173: use common helper to access registers Chunfeng Yun
@ 2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 17/18] phy: mediatek: mipi: mt8183: use common helper to access registers Chunfeng Yun
` (2 subsequent siblings)
18 siblings, 1 reply; 39+ messages in thread
From: Chunfeng Yun @ 2022-09-20 9:00 UTC (permalink / raw)
To: Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Chunfeng Yun, Kishon Vijay Abraham I,
Matthias Brugger, dri-devel, linux-mediatek, linux-arm-kernel,
linux-phy, linux-kernel, Jitao Shi, Stanley Chu
Use GENMASK() macro to generate bits mask
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
index 99108426d57c..1ec71ba2407e 100644
--- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
+++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
@@ -18,7 +18,7 @@
#define RG_DSI_PAD_TIEL_SEL BIT(8)
#define MIPITX_VOLTAGE_SEL 0x0010
-#define RG_DSI_HSTX_LDO_REF_SEL (0xf << 6)
+#define RG_DSI_HSTX_LDO_REF_SEL GENMASK(9, 6)
#define MIPITX_PLL_PWR 0x0028
#define MIPITX_PLL_CON0 0x002c
@@ -26,7 +26,7 @@
#define MIPITX_PLL_CON2 0x0034
#define MIPITX_PLL_CON3 0x0038
#define MIPITX_PLL_CON4 0x003c
-#define RG_DSI_PLL_IBIAS (3 << 10)
+#define RG_DSI_PLL_IBIAS GENMASK(11, 10)
#define MIPITX_D2P_RTCODE 0x0100
#define MIPITX_D2_SW_CTL_EN 0x0144
@@ -41,7 +41,7 @@
#define AD_DSI_PLL_SDM_ISO_EN BIT(1)
#define RG_DSI_PLL_EN BIT(4)
-#define RG_DSI_PLL_POSDIV (0x7 << 8)
+#define RG_DSI_PLL_POSDIV GENMASK(10, 8)
static int mtk_mipi_tx_pll_enable(struct clk_hw *hw)
{
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH 16/18] phy: mediatek: mipi: mt8183: use GENMASK to generate bits mask
2022-09-20 9:00 ` [PATCH 16/18] phy: mediatek: mipi: mt8183: use GENMASK to generate bits mask Chunfeng Yun
@ 2022-09-21 8:14 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-09-21 8:14 UTC (permalink / raw)
To: Chunfeng Yun, Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Kishon Vijay Abraham I, Matthias Brugger,
dri-devel, linux-mediatek, linux-arm-kernel, linux-phy,
linux-kernel, Jitao Shi, Stanley Chu
Il 20/09/22 11:00, Chunfeng Yun ha scritto:
> Use GENMASK() macro to generate bits mask
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 17/18] phy: mediatek: mipi: mt8183: use common helper to access registers
2022-09-20 9:00 [PATCH 00/18] unify register access and macros Chunfeng Yun
` (15 preceding siblings ...)
2022-09-20 9:00 ` [PATCH 16/18] phy: mediatek: mipi: mt8183: use GENMASK to generate bits mask Chunfeng Yun
@ 2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:14 ` AngeloGioacchino Del Regno
2022-09-20 9:00 ` [PATCH 18/18] phy: mediatek: mipi: remove register access helpers Chunfeng Yun
2022-09-24 6:28 ` [PATCH 00/18] unify register access and macros Vinod Koul
18 siblings, 1 reply; 39+ messages in thread
From: Chunfeng Yun @ 2022-09-20 9:00 UTC (permalink / raw)
To: Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Chunfeng Yun, Kishon Vijay Abraham I,
Matthias Brugger, dri-devel, linux-mediatek, linux-arm-kernel,
linux-phy, linux-kernel, Jitao Shi, Stanley Chu
Use MediaTek phy's common helper to access registers, then we can remove
mipi-dsi's I/O helpers.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
.../phy/mediatek/phy-mtk-mipi-dsi-mt8183.c | 68 +++++++++----------
1 file changed, 34 insertions(+), 34 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
index 1ec71ba2407e..f021ec5a70e5 100644
--- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
+++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
@@ -4,6 +4,7 @@
* Author: jitao.shi <jitao.shi@mediatek.com>
*/
+#include "phy-mtk-io.h"
#include "phy-mtk-mipi-dsi.h"
#define MIPITX_LANE_CON 0x000c
@@ -46,6 +47,7 @@
static int mtk_mipi_tx_pll_enable(struct clk_hw *hw)
{
struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
+ void __iomem *base = mipi_tx->regs;
unsigned int txdiv, txdiv0;
u64 pcw;
@@ -70,17 +72,16 @@ static int mtk_mipi_tx_pll_enable(struct clk_hw *hw)
return -EINVAL;
}
- mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS);
+ mtk_phy_clear_bits(base + MIPITX_PLL_CON4, RG_DSI_PLL_IBIAS);
- mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
- mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);
+ mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
+ mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
udelay(1);
- mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
+ mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
pcw = div_u64(((u64)mipi_tx->data_rate * txdiv) << 24, 26000000);
- writel(pcw, mipi_tx->regs + MIPITX_PLL_CON0);
- mtk_mipi_tx_update_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV,
- txdiv0 << 8);
- mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);
+ writel(pcw, base + MIPITX_PLL_CON0);
+ mtk_phy_update_field(base + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, txdiv0);
+ mtk_phy_set_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
return 0;
}
@@ -88,11 +89,12 @@ static int mtk_mipi_tx_pll_enable(struct clk_hw *hw)
static void mtk_mipi_tx_pll_disable(struct clk_hw *hw)
{
struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
+ void __iomem *base = mipi_tx->regs;
- mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_CON1, RG_DSI_PLL_EN);
+ mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
- mtk_mipi_tx_set_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
- mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
+ mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
+ mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
}
static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
@@ -121,7 +123,7 @@ static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx)
mipi_tx->rt_code[i] |= 0x10 << 5;
for (j = 0; j < 10; j++)
- mtk_mipi_tx_update_bits(mipi_tx,
+ mtk_phy_update_bits(mipi_tx->regs +
MIPITX_D2P_RTCODE * (i + 1) + j * 4,
1, mipi_tx->rt_code[i] >> j & 1);
}
@@ -130,44 +132,42 @@ static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx)
static void mtk_mipi_tx_power_on_signal(struct phy *phy)
{
struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
+ void __iomem *base = mipi_tx->regs;
/* BG_LPF_EN / BG_CORE_EN */
- writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN,
- mipi_tx->regs + MIPITX_LANE_CON);
+ writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN, base + MIPITX_LANE_CON);
usleep_range(30, 100);
- writel(RG_DSI_BG_CORE_EN | RG_DSI_BG_LPF_EN,
- mipi_tx->regs + MIPITX_LANE_CON);
+ writel(RG_DSI_BG_CORE_EN | RG_DSI_BG_LPF_EN, base + MIPITX_LANE_CON);
/* Switch OFF each Lane */
- mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
- mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
- mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
- mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
- mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
+ mtk_phy_clear_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
+ mtk_phy_clear_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
+ mtk_phy_clear_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
+ mtk_phy_clear_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
+ mtk_phy_clear_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
- mtk_mipi_tx_update_bits(mipi_tx, MIPITX_VOLTAGE_SEL,
- RG_DSI_HSTX_LDO_REF_SEL,
- (mipi_tx->mipitx_drive - 3000) / 200 << 6);
+ mtk_phy_update_field(base + MIPITX_VOLTAGE_SEL, RG_DSI_HSTX_LDO_REF_SEL,
+ (mipi_tx->mipitx_drive - 3000) / 200);
mtk_mipi_tx_config_calibration_data(mipi_tx);
- mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
+ mtk_phy_set_bits(base + MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
}
static void mtk_mipi_tx_power_off_signal(struct phy *phy)
{
struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
+ void __iomem *base = mipi_tx->regs;
/* Switch ON each Lane */
- mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
- mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
- mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
- mtk_mipi_tx_set_bits(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
- mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
-
- writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN,
- mipi_tx->regs + MIPITX_LANE_CON);
- writel(RG_DSI_PAD_TIEL_SEL, mipi_tx->regs + MIPITX_LANE_CON);
+ mtk_phy_set_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
+ mtk_phy_set_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
+ mtk_phy_set_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
+ mtk_phy_set_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
+ mtk_phy_set_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
+
+ writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN, base + MIPITX_LANE_CON);
+ writel(RG_DSI_PAD_TIEL_SEL, base + MIPITX_LANE_CON);
}
const struct mtk_mipitx_data mt8183_mipitx_data = {
--
2.18.0
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^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH 17/18] phy: mediatek: mipi: mt8183: use common helper to access registers
2022-09-20 9:00 ` [PATCH 17/18] phy: mediatek: mipi: mt8183: use common helper to access registers Chunfeng Yun
@ 2022-09-21 8:14 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-09-21 8:14 UTC (permalink / raw)
To: Chunfeng Yun, Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Kishon Vijay Abraham I, Matthias Brugger,
dri-devel, linux-mediatek, linux-arm-kernel, linux-phy,
linux-kernel, Jitao Shi, Stanley Chu
Il 20/09/22 11:00, Chunfeng Yun ha scritto:
> Use MediaTek phy's common helper to access registers, then we can remove
> mipi-dsi's I/O helpers.
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH 18/18] phy: mediatek: mipi: remove register access helpers
2022-09-20 9:00 [PATCH 00/18] unify register access and macros Chunfeng Yun
` (16 preceding siblings ...)
2022-09-20 9:00 ` [PATCH 17/18] phy: mediatek: mipi: mt8183: use common helper to access registers Chunfeng Yun
@ 2022-09-20 9:00 ` Chunfeng Yun
2022-09-21 8:15 ` AngeloGioacchino Del Regno
2022-09-24 6:28 ` [PATCH 00/18] unify register access and macros Vinod Koul
18 siblings, 1 reply; 39+ messages in thread
From: Chunfeng Yun @ 2022-09-20 9:00 UTC (permalink / raw)
To: Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Chunfeng Yun, Kishon Vijay Abraham I,
Matthias Brugger, dri-devel, linux-mediatek, linux-arm-kernel,
linux-phy, linux-kernel, Jitao Shi, Stanley Chu
Remove private register access helpers, use the common ones instead.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/phy/mediatek/phy-mtk-mipi-dsi.c | 24 ------------------------
drivers/phy/mediatek/phy-mtk-mipi-dsi.h | 5 -----
2 files changed, 29 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi.c
index 28506932bd91..cf9c386385bb 100644
--- a/drivers/phy/mediatek/phy-mtk-mipi-dsi.c
+++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi.c
@@ -10,30 +10,6 @@ inline struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw)
return container_of(hw, struct mtk_mipi_tx, pll_hw);
}
-void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
- u32 bits)
-{
- u32 temp = readl(mipi_tx->regs + offset);
-
- writel(temp & ~bits, mipi_tx->regs + offset);
-}
-
-void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
- u32 bits)
-{
- u32 temp = readl(mipi_tx->regs + offset);
-
- writel(temp | bits, mipi_tx->regs + offset);
-}
-
-void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset,
- u32 mask, u32 data)
-{
- u32 temp = readl(mipi_tx->regs + offset);
-
- writel((temp & ~mask) | (data & mask), mipi_tx->regs + offset);
-}
-
int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi.h b/drivers/phy/mediatek/phy-mtk-mipi-dsi.h
index c76f07c3fdeb..47b60b1a7226 100644
--- a/drivers/phy/mediatek/phy-mtk-mipi-dsi.h
+++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi.h
@@ -10,7 +10,6 @@
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/delay.h>
-#include <linux/io.h>
#include <linux/module.h>
#include <linux/nvmem-consumer.h>
#include <linux/of_device.h>
@@ -37,10 +36,6 @@ struct mtk_mipi_tx {
};
struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw);
-void mtk_mipi_tx_clear_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 bits);
-void mtk_mipi_tx_set_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 bits);
-void mtk_mipi_tx_update_bits(struct mtk_mipi_tx *mipi_tx, u32 offset, u32 mask,
- u32 data);
int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate);
unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
--
2.18.0
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^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH 18/18] phy: mediatek: mipi: remove register access helpers
2022-09-20 9:00 ` [PATCH 18/18] phy: mediatek: mipi: remove register access helpers Chunfeng Yun
@ 2022-09-21 8:15 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-09-21 8:15 UTC (permalink / raw)
To: Chunfeng Yun, Chun-Kuang Hu, Vinod Koul
Cc: Philipp Zabel, Kishon Vijay Abraham I, Matthias Brugger,
dri-devel, linux-mediatek, linux-arm-kernel, linux-phy,
linux-kernel, Jitao Shi, Stanley Chu
Il 20/09/22 11:00, Chunfeng Yun ha scritto:
> Remove private register access helpers, use the common ones instead.
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH 00/18] unify register access and macros
2022-09-20 9:00 [PATCH 00/18] unify register access and macros Chunfeng Yun
` (17 preceding siblings ...)
2022-09-20 9:00 ` [PATCH 18/18] phy: mediatek: mipi: remove register access helpers Chunfeng Yun
@ 2022-09-24 6:28 ` Vinod Koul
18 siblings, 0 replies; 39+ messages in thread
From: Vinod Koul @ 2022-09-24 6:28 UTC (permalink / raw)
To: Chunfeng Yun
Cc: Chun-Kuang Hu, Philipp Zabel, Kishon Vijay Abraham I,
Matthias Brugger, dri-devel, linux-mediatek, linux-arm-kernel,
linux-phy, linux-kernel, Jitao Shi, Stanley Chu
On 20-09-22, 17:00, Chunfeng Yun wrote:
> No need to define new macros to generate bits, mask and bitfield, use
> common ones instead, e.g. BIT, GENMASK and FIELD_PREP etc.
> Due to common register access helpers are defined for MediaTek's phy
> drivers, the similar helpers defined by ufs, hdmi and mipi phy drivers
> can be removed.
Applied, thanks
--
~Vinod
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^ permalink raw reply [flat|nested] 39+ messages in thread