From: bhelgaas@google.com (Bjorn Helgaas)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 24/32] pci: PCIe driver for Marvell Armada 370/XP systems
Date: Thu, 14 Feb 2013 17:36:39 -0700 [thread overview]
Message-ID: <CAErSpo6_6bYjo5XX5tzoBfMu5Htgpa__foNCyoCnCNEHocx67Q@mail.gmail.com> (raw)
In-Reply-To: <1360686546-24277-25-git-send-email-thomas.petazzoni@free-electrons.com>
On Tue, Feb 12, 2013 at 9:28 AM, Thomas Petazzoni
<thomas.petazzoni@free-electrons.com> wrote:
> --- a/drivers/pci/host/Kconfig
> +++ b/drivers/pci/host/Kconfig
> @@ -1,4 +1,10 @@
> menu "PCI host controller drivers"
> depends on PCI
>
> +config PCI_MVEBU
> + bool "Marvell EBU PCIe controller"
> + depends on ARCH_MVEBU
> + select PCI_SW_HOST_BRIDGE
> + select PCI_SW_PCI_PCI_BRIDGE
I think PCI_SW_HOST_BRIDGE and PCI_SW_PCI_PCI_BRIDGE are obsolete and
can be removed, right?
> --- /dev/null
> +++ b/drivers/pci/host/pci-mvebu.c
> ...
> +static void mvebu_pcie_setup_io_window(struct mvebu_pcie_port *port,
> + int enable)
> +{
> + unsigned long iobase, iolimit;
> +
> + if (port->bridge.iolimit < port->bridge.iobase)
> + return;
> +
> + iolimit = 0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
> + (port->bridge.iolimitupper << 16);
> + iobase = ((port->bridge.iobase & 0xF0) << 8) |
> + (port->bridge.iobaseupper << 16);
> +
> + if (enable) {
> + unsigned long physbase = port->pcie->io.start + iobase;
> + armada_370_xp_alloc_pcie_window(port->port, port->lane,
> + physbase, iobase,
> + iolimit-iobase,
> + IORESOURCE_IO);
> + pci_ioremap_io(iobase, physbase);
> + }
> + else
> + armada_370_xp_free_pcie_window(iobase);
> +}
> +
> +static void mvebu_pcie_setup_mem_window(struct mvebu_pcie_port *port,
> + int enable)
> +{
> + unsigned long membase, memlimit;
> +
> + if (port->bridge.memlimit < port->bridge.membase)
> + return;
> +
> + membase = ((port->bridge.membase & 0xFFF0) << 16);
> + memlimit = ((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF;
> +
> + if (enable)
> + armada_370_xp_alloc_pcie_window(port->port, port->lane,
> + membase, ORION_ADDR_MAP_NO_REMAP,
> + memlimit-membase,
> + IORESOURCE_MEM);
> + else
> + armada_370_xp_free_pcie_window(membase);
> +}
> +
> +static void mvebu_handle_pcie_command(struct mvebu_pcie_port *port, u16 old,
> + u16 new)
> +{
> + /* Enabling an I/O window ? */
> + if (!(old & PCI_COMMAND_IO) && (new & PCI_COMMAND_IO))
> + mvebu_pcie_setup_io_window(port, 1);
> +
> + /* Disabling an I/O window ? */
> + if ((old & PCI_COMMAND_IO) && !(new & PCI_COMMAND_IO))
> + mvebu_pcie_setup_io_window(port, 0);
> +
> + /* Enabling a memory window ? */
> + if (!(old & PCI_COMMAND_MEMORY) && (new & PCI_COMMAND_MEMORY))
> + mvebu_pcie_setup_mem_window(port, 1);
> +
> + /* Disabling a memory window ? */
> + if ((old & PCI_COMMAND_MEMORY) && !(new & PCI_COMMAND_MEMORY))
> + mvebu_pcie_setup_mem_window(port, 0);
> +}
> ...
> +/* Write to the PCI-to-PCI bridge configuration space */
> +static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
> + unsigned int where, int size, u32 value)
> +{
> + struct mvebu_sw_pci_bridge *bridge = &port->bridge;
> + u32 mask, reg;
> + int err;
> +
> + if (size == 4)
> + mask = 0x0;
> + else if (size == 2)
> + mask = ~(0xffff << ((where & 3) * 8));
> + else if (size == 1)
> + mask = ~(0xff << ((where & 3) * 8));
> + else
> + return PCIBIOS_BAD_REGISTER_NUMBER;
> +
> + err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, ®);
> + if (err)
> + return err;
> +
> + value = (reg & mask) | value << ((where & 3) * 8);
> +
> + switch (where & ~3) {
> + case PCI_COMMAND:
> + mvebu_handle_pcie_command(port, bridge->command,
> + value & 0xffff);
> + bridge->command = value & 0xffff;
> + bridge->status = value >> 16;
> + break;
> +
> + case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
> + bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
> + break;
> +
> + case PCI_IO_BASE:
> + /*
> + * We also keep bit 1 set, it is a read-only bit that
> + * indicates we support 32 bits addressing for the
> + * I/O
> + */
> + bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
> + bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
> + bridge->secondary_status = value >> 16;
> + break;
> +
> + case PCI_MEMORY_BASE:
> + bridge->membase = value & 0xffff;
> + bridge->memlimit = value >> 16;
> + break;
> +
> + case PCI_PREF_MEMORY_BASE:
> + bridge->prefmembase = value & 0xffff;
> + bridge->prefmemlimit = value >> 16;
> + break;
> +
> + case PCI_PREF_BASE_UPPER32:
> + bridge->prefbaseupper = value;
> + break;
> +
> + case PCI_PREF_LIMIT_UPPER32:
> + bridge->preflimitupper = value;
> + break;
You're relying on a subsequent PCI_COMMAND write to set PCI_COMMAND_IO
and/or PCI_COMMAND_MEMORY, and you program the bridge windows at that
time. It might be a good idea if the PCI core did clear those bits
while updating the windows, but I'm not sure we do. In any case,
delaying the update is a difference from a standard P2P bridge that
could cause issues later.
> + case PCI_IO_BASE_UPPER16:
> + bridge->iobaseupper = value & 0xffff;
> + bridge->iolimitupper = value >> 16;
> + break;
> +
> + case PCI_PRIMARY_BUS:
> + bridge->primary_bus = value & 0xff;
> + bridge->secondary_bus = (value >> 8) & 0xff;
> + bridge->subordinate_bus = (value >> 16) & 0xff;
> + bridge->secondary_latency_timer = (value >> 24) & 0xff;
> + orion_pcie_set_local_bus_nr(port->base, bridge->secondary_bus);
> + break;
> +
> + default:
> + break;
> + }
> +
> + return PCIBIOS_SUCCESSFUL;
> +}
Bjorn
next prev parent reply other threads:[~2013-02-15 0:36 UTC|newest]
Thread overview: 135+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-02-12 16:28 [PATCH v3] PCIe support for the Armada 370 and Armada XP SoCs Thomas Petazzoni
2013-02-12 16:28 ` [PATCH 01/32] of/pci: Provide support for parsing PCI DT ranges property Thomas Petazzoni
2013-02-12 16:28 ` [PATCH 02/32] of/pci: Add of_pci_get_devfn() function Thomas Petazzoni
2013-02-12 16:28 ` [PATCH 03/32] of/pci: Add of_pci_parse_bus_range() function Thomas Petazzoni
2013-02-12 16:28 ` [PATCH 04/32] ARM: pci: Allow passing per-controller private data Thomas Petazzoni
2013-02-12 16:28 ` [PATCH 05/32] lib: devres: don't enclose pcim_*() functions in CONFIG_HAS_IOPORT Thomas Petazzoni
2013-02-12 18:00 ` Arnd Bergmann
2013-02-12 18:58 ` Thomas Petazzoni
2013-02-12 22:36 ` Arnd Bergmann
2013-03-04 16:28 ` Thomas Petazzoni
2013-03-04 20:30 ` Arnd Bergmann
2013-02-12 16:28 ` [PATCH 06/32] arm: pci: add a align_resource hook Thomas Petazzoni
2013-02-12 18:03 ` Arnd Bergmann
2013-02-12 19:01 ` Thomas Petazzoni
2013-02-12 19:49 ` Russell King - ARM Linux
2013-02-12 16:28 ` [PATCH 07/32] arm: mvebu: fix address-cells in mpic DT node Thomas Petazzoni
2013-02-12 16:28 ` [PATCH 08/32] clk: mvebu: create parent-child relation for PCIe clocks on Armada 370 Thomas Petazzoni
2013-02-12 16:28 ` [PATCH 09/32] clk: mvebu: add more PCIe clocks for Armada XP Thomas Petazzoni
2013-02-12 16:28 ` [PATCH 10/32] arm: plat-orion: introduce WIN_CTRL_ENABLE in address mapping code Thomas Petazzoni
2013-02-12 16:28 ` [PATCH 11/32] arm: plat-orion: refactor the orion_disable_wins() function Thomas Petazzoni
2013-02-12 16:28 ` [PATCH 12/32] plat-orion: introduce ORION_ADDR_MAP_NO_REMAP Thomas Petazzoni
2013-02-12 16:28 ` [PATCH 13/32] arm: mach-dove: use ORION_ADDR_MAP_NO_REMAP Thomas Petazzoni
2013-02-12 16:28 ` [PATCH 14/32] arm: mach-kirkwood: " Thomas Petazzoni
2013-02-12 16:28 ` [PATCH 15/32] arm: mach-mvebu: " Thomas Petazzoni
2013-02-12 16:28 ` [PATCH 16/32] arm: mach-orion5x: " Thomas Petazzoni
2013-02-12 16:28 ` [PATCH 17/32] arm: plat-orion: convert 'int remap' to 'u32 remap' Thomas Petazzoni
2013-02-12 16:28 ` [PATCH 18/32] arm: plat-orion: remove __init from addr-map functions needed after boot time Thomas Petazzoni
2013-02-12 16:28 ` [PATCH 19/32] arm: plat-orion: introduce orion_{alloc, free}_cpu_win() functions Thomas Petazzoni
2013-02-12 16:28 ` [PATCH 20/32] arm: plat-orion: remove __init from PCIe functions needed after boot time Thomas Petazzoni
2013-02-12 16:28 ` [PATCH 21/32] arm: mvebu: add functions to alloc/free PCIe decoding windows Thomas Petazzoni
2013-02-12 16:28 ` [PATCH 22/32] arm: plat-orion: make common PCIe code usable on mvebu Thomas Petazzoni
2013-02-12 16:28 ` [PATCH 23/32] pci: infrastructure to add drivers in drivers/pci/host Thomas Petazzoni
2013-02-12 16:28 ` [PATCH 24/32] pci: PCIe driver for Marvell Armada 370/XP systems Thomas Petazzoni
2013-02-12 18:30 ` Arnd Bergmann
2013-02-12 19:22 ` Thomas Petazzoni
2013-02-12 19:49 ` Jason Gunthorpe
2013-02-12 22:59 ` Arnd Bergmann
2013-02-13 0:41 ` Jason Gunthorpe
2013-02-13 9:18 ` Arnd Bergmann
2013-02-13 9:31 ` Thomas Petazzoni
2013-02-13 10:23 ` Arnd Bergmann
2013-02-13 8:23 ` Thomas Petazzoni
2013-02-13 9:29 ` Arnd Bergmann
2013-02-13 9:40 ` Thomas Petazzoni
2013-02-13 10:37 ` Arnd Bergmann
2013-03-06 9:50 ` Thomas Petazzoni
2013-03-06 10:43 ` Arnd Bergmann
2013-02-12 22:35 ` Jason Gunthorpe
2013-02-13 8:57 ` Thomas Petazzoni
2013-02-13 18:04 ` Jason Gunthorpe
2013-02-13 19:33 ` Arnd Bergmann
2013-03-06 9:54 ` Thomas Petazzoni
2013-03-06 12:11 ` Thierry Reding
2013-03-06 18:09 ` Jason Gunthorpe
2013-03-07 8:08 ` Thierry Reding
2013-03-07 17:49 ` Jason Gunthorpe
2013-03-07 19:48 ` Thierry Reding
2013-03-07 20:02 ` Jason Gunthorpe
2013-03-07 20:47 ` Thierry Reding
2013-03-08 0:05 ` Rob Herring
2013-03-08 7:14 ` Thierry Reding
2013-03-08 16:52 ` Jason Gunthorpe
2013-03-08 19:12 ` Thierry Reding
2013-03-08 19:43 ` Mitch Bradley
2013-03-08 20:02 ` Jason Gunthorpe
2013-03-08 20:13 ` Thierry Reding
2013-03-10 15:09 ` Thomas Petazzoni
2013-03-11 8:08 ` Thierry Reding
2013-03-08 23:46 ` Mitch Bradley
2013-03-09 1:31 ` Jason Gunthorpe
2013-03-10 4:52 ` Mitch Bradley
2013-03-10 6:55 ` Jason Gunthorpe
2013-03-11 5:46 ` Mitch Bradley
2013-03-11 7:46 ` Thierry Reding
2013-03-11 18:04 ` Mitch Bradley
2013-03-11 18:23 ` Jason Gunthorpe
2013-03-11 19:49 ` Mitch Bradley
2013-03-11 18:15 ` Jason Gunthorpe
2013-03-11 21:50 ` Mitch Bradley
2013-03-11 23:25 ` Jason Gunthorpe
2013-03-11 23:38 ` Mitch Bradley
2013-03-12 7:08 ` Thierry Reding
2013-03-12 15:57 ` Jason Gunthorpe
2013-03-12 20:38 ` Thierry Reding
2013-03-12 21:03 ` Jason Gunthorpe
2013-03-12 21:30 ` Thierry Reding
2013-03-12 22:08 ` Jason Gunthorpe
2013-03-12 23:25 ` Mitch Bradley
2013-03-13 8:18 ` Thierry Reding
2013-03-13 17:02 ` Jason Gunthorpe
2013-03-13 19:26 ` Thierry Reding
2013-03-13 19:59 ` Jason Gunthorpe
2013-03-13 20:54 ` Thierry Reding
2013-03-13 20:58 ` Mitch Bradley
2013-03-13 21:33 ` Thierry Reding
2013-03-13 22:48 ` Mitch Bradley
2013-03-14 0:43 ` Rob Herring
2013-03-14 1:20 ` Mitch Bradley
2013-03-14 7:11 ` Thierry Reding
2013-03-14 4:56 ` Stephen Warren
2013-03-13 22:02 ` Thierry Reding
2013-03-13 22:21 ` Jason Gunthorpe
2013-03-14 9:01 ` Thierry Reding
2013-03-14 17:25 ` Jason Gunthorpe
2013-03-14 20:38 ` Thierry Reding
2013-03-14 21:05 ` Jason Gunthorpe
2013-03-14 21:10 ` Mitch Bradley
2013-03-14 21:09 ` Thierry Reding
2013-03-14 21:29 ` Jason Gunthorpe
2013-03-14 21:37 ` Thierry Reding
2013-03-13 22:22 ` Jason Gunthorpe
2013-03-09 8:58 ` Thomas Petazzoni
2013-03-08 23:12 ` Rob Herring
2013-03-09 11:10 ` Thierry Reding
2013-03-10 5:04 ` Mitch Bradley
2013-03-10 15:06 ` Thomas Petazzoni
2013-03-10 18:33 ` Mitch Bradley
2013-02-15 0:36 ` Bjorn Helgaas [this message]
2013-02-15 5:06 ` Thomas Petazzoni
2013-02-15 16:26 ` Bjorn Helgaas
2013-02-15 16:44 ` Jason Gunthorpe
2013-02-12 16:28 ` [PATCH 25/32] arm: mvebu: PCIe support is now available on mvebu Thomas Petazzoni
2013-02-12 16:29 ` [PATCH 26/32] arm: mvebu: add PCIe Device Tree informations for Armada 370 Thomas Petazzoni
2013-02-12 16:29 ` [PATCH 27/32] arm: mvebu: add PCIe Device Tree informations for Armada XP Thomas Petazzoni
2013-02-12 16:29 ` [PATCH 28/32] arm: mvebu: PCIe Device Tree informations for OpenBlocks AX3-4 Thomas Petazzoni
2013-02-12 16:29 ` [PATCH 29/32] arm: mvebu: PCIe Device Tree informations for Armada XP DB Thomas Petazzoni
2013-02-12 16:29 ` [PATCH 30/32] arm: mvebu: PCIe Device Tree informations for Armada 370 Mirabox Thomas Petazzoni
2013-02-12 16:29 ` [PATCH 31/32] arm: mvebu: PCIe Device Tree informations for Armada 370 DB Thomas Petazzoni
2013-02-12 16:29 ` [PATCH 32/32] arm: mvebu: update defconfig with PCI and USB support Thomas Petazzoni
2013-02-12 18:12 ` [PATCH v3] PCIe support for the Armada 370 and Armada XP SoCs Arnd Bergmann
2013-02-12 19:04 ` Thomas Petazzoni
2013-02-13 8:50 ` Thomas Petazzoni
2013-02-13 9:37 ` Arnd Bergmann
2013-02-13 15:27 ` Christophe Vu-Brugier
2013-02-13 15:30 ` Thomas Petazzoni
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