* [PATCH v2] PCI: aardvark: fix big endian support
@ 2019-07-16 12:12 Grzegorz Jaszczyk
2019-09-30 8:17 ` Grzegorz Jaszczyk
2019-10-17 12:43 ` Lorenzo Pieralisi
0 siblings, 2 replies; 5+ messages in thread
From: Grzegorz Jaszczyk @ 2019-07-16 12:12 UTC (permalink / raw)
To: thomas.petazzoni, lorenzo.pieralisi, bhelgaas
Cc: linux-pci, mw, linux-arm-kernel, Grzegorz Jaszczyk
Initialise every not-byte wide fields of emulated pci bridge config
space with proper cpu_to_le* macro. This is required since the structure
describing config space of emulated bridge assumes little-endian
convention.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
---
v1->v2
- add missing cpu_to_le32 for class_revison assignment (issues found by
Thomas Petazzoni and also detected by Sparse tool).
drivers/pci/controller/pci-aardvark.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 134e030..178e92f 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -479,18 +479,20 @@ static void advk_sw_pci_bridge_init(struct advk_pcie *pcie)
{
struct pci_bridge_emul *bridge = &pcie->bridge;
- bridge->conf.vendor = advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff;
- bridge->conf.device = advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16;
+ bridge->conf.vendor =
+ cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff);
+ bridge->conf.device =
+ cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16);
bridge->conf.class_revision =
- advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff;
+ cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff);
/* Support 32 bits I/O addressing */
bridge->conf.iobase = PCI_IO_RANGE_TYPE_32;
bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
/* Support 64 bits memory pref */
- bridge->conf.pref_mem_base = PCI_PREF_RANGE_TYPE_64;
- bridge->conf.pref_mem_limit = PCI_PREF_RANGE_TYPE_64;
+ bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
+ bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
/* Support interrupt A for MSI feature */
bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE;
--
2.7.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH v2] PCI: aardvark: fix big endian support
2019-07-16 12:12 [PATCH v2] PCI: aardvark: fix big endian support Grzegorz Jaszczyk
@ 2019-09-30 8:17 ` Grzegorz Jaszczyk
2019-09-30 14:39 ` Lorenzo Pieralisi
2019-10-17 12:43 ` Lorenzo Pieralisi
1 sibling, 1 reply; 5+ messages in thread
From: Grzegorz Jaszczyk @ 2019-09-30 8:17 UTC (permalink / raw)
To: Thomas Petazzoni, lorenzo.pieralisi, Bjorn Helgaas
Cc: linux-pci, Marcin Wojtas, Russell King - ARM Linux, linux-arm-kernel
Hello,
I want to kindly remind about this patch.
Best regards,
Grzegorz
wt., 16 lip 2019 o 14:12 Grzegorz Jaszczyk <jaz@semihalf.com> napisał(a):
>
> Initialise every not-byte wide fields of emulated pci bridge config
> space with proper cpu_to_le* macro. This is required since the structure
> describing config space of emulated bridge assumes little-endian
> convention.
>
> Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
> ---
> v1->v2
> - add missing cpu_to_le32 for class_revison assignment (issues found by
> Thomas Petazzoni and also detected by Sparse tool).
>
> drivers/pci/controller/pci-aardvark.c | 12 +++++++-----
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
> index 134e030..178e92f 100644
> --- a/drivers/pci/controller/pci-aardvark.c
> +++ b/drivers/pci/controller/pci-aardvark.c
> @@ -479,18 +479,20 @@ static void advk_sw_pci_bridge_init(struct advk_pcie *pcie)
> {
> struct pci_bridge_emul *bridge = &pcie->bridge;
>
> - bridge->conf.vendor = advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff;
> - bridge->conf.device = advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16;
> + bridge->conf.vendor =
> + cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff);
> + bridge->conf.device =
> + cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16);
> bridge->conf.class_revision =
> - advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff;
> + cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff);
>
> /* Support 32 bits I/O addressing */
> bridge->conf.iobase = PCI_IO_RANGE_TYPE_32;
> bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
>
> /* Support 64 bits memory pref */
> - bridge->conf.pref_mem_base = PCI_PREF_RANGE_TYPE_64;
> - bridge->conf.pref_mem_limit = PCI_PREF_RANGE_TYPE_64;
> + bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
> + bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
>
> /* Support interrupt A for MSI feature */
> bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE;
> --
> 2.7.4
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v2] PCI: aardvark: fix big endian support
2019-09-30 8:17 ` Grzegorz Jaszczyk
@ 2019-09-30 14:39 ` Lorenzo Pieralisi
2019-10-04 8:38 ` Grzegorz Jaszczyk
0 siblings, 1 reply; 5+ messages in thread
From: Lorenzo Pieralisi @ 2019-09-30 14:39 UTC (permalink / raw)
To: Grzegorz Jaszczyk
Cc: linux-pci, Russell King - ARM Linux, Thomas Petazzoni,
Bjorn Helgaas, Marcin Wojtas, linux-arm-kernel
On Mon, Sep 30, 2019 at 10:17:33AM +0200, Grzegorz Jaszczyk wrote:
> Hello,
>
> I want to kindly remind about this patch.
I need Thomas' ACK on these patches to merge them.
Thanks,
Lorenzo
> Best regards,
> Grzegorz
>
> wt., 16 lip 2019 o 14:12 Grzegorz Jaszczyk <jaz@semihalf.com> napisał(a):
> >
> > Initialise every not-byte wide fields of emulated pci bridge config
> > space with proper cpu_to_le* macro. This is required since the structure
> > describing config space of emulated bridge assumes little-endian
> > convention.
> >
> > Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
> > ---
> > v1->v2
> > - add missing cpu_to_le32 for class_revison assignment (issues found by
> > Thomas Petazzoni and also detected by Sparse tool).
> >
> > drivers/pci/controller/pci-aardvark.c | 12 +++++++-----
> > 1 file changed, 7 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
> > index 134e030..178e92f 100644
> > --- a/drivers/pci/controller/pci-aardvark.c
> > +++ b/drivers/pci/controller/pci-aardvark.c
> > @@ -479,18 +479,20 @@ static void advk_sw_pci_bridge_init(struct advk_pcie *pcie)
> > {
> > struct pci_bridge_emul *bridge = &pcie->bridge;
> >
> > - bridge->conf.vendor = advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff;
> > - bridge->conf.device = advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16;
> > + bridge->conf.vendor =
> > + cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff);
> > + bridge->conf.device =
> > + cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16);
> > bridge->conf.class_revision =
> > - advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff;
> > + cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff);
> >
> > /* Support 32 bits I/O addressing */
> > bridge->conf.iobase = PCI_IO_RANGE_TYPE_32;
> > bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
> >
> > /* Support 64 bits memory pref */
> > - bridge->conf.pref_mem_base = PCI_PREF_RANGE_TYPE_64;
> > - bridge->conf.pref_mem_limit = PCI_PREF_RANGE_TYPE_64;
> > + bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
> > + bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
> >
> > /* Support interrupt A for MSI feature */
> > bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE;
> > --
> > 2.7.4
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2] PCI: aardvark: fix big endian support
2019-07-16 12:12 [PATCH v2] PCI: aardvark: fix big endian support Grzegorz Jaszczyk
2019-09-30 8:17 ` Grzegorz Jaszczyk
@ 2019-10-17 12:43 ` Lorenzo Pieralisi
1 sibling, 0 replies; 5+ messages in thread
From: Lorenzo Pieralisi @ 2019-10-17 12:43 UTC (permalink / raw)
To: Grzegorz Jaszczyk
Cc: bhelgaas, linux-pci, mw, linux-arm-kernel, thomas.petazzoni
On Tue, Jul 16, 2019 at 02:12:07PM +0200, Grzegorz Jaszczyk wrote:
> Initialise every not-byte wide fields of emulated pci bridge config
> space with proper cpu_to_le* macro. This is required since the structure
> describing config space of emulated bridge assumes little-endian
> convention.
>
> Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
> ---
> v1->v2
> - add missing cpu_to_le32 for class_revison assignment (issues found by
> Thomas Petazzoni and also detected by Sparse tool).
>
> drivers/pci/controller/pci-aardvark.c | 12 +++++++-----
> 1 file changed, 7 insertions(+), 5 deletions(-)
Applied to pci/aardvark, thanks.
Lorenzo
> diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
> index 134e030..178e92f 100644
> --- a/drivers/pci/controller/pci-aardvark.c
> +++ b/drivers/pci/controller/pci-aardvark.c
> @@ -479,18 +479,20 @@ static void advk_sw_pci_bridge_init(struct advk_pcie *pcie)
> {
> struct pci_bridge_emul *bridge = &pcie->bridge;
>
> - bridge->conf.vendor = advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff;
> - bridge->conf.device = advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16;
> + bridge->conf.vendor =
> + cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff);
> + bridge->conf.device =
> + cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16);
> bridge->conf.class_revision =
> - advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff;
> + cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff);
>
> /* Support 32 bits I/O addressing */
> bridge->conf.iobase = PCI_IO_RANGE_TYPE_32;
> bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
>
> /* Support 64 bits memory pref */
> - bridge->conf.pref_mem_base = PCI_PREF_RANGE_TYPE_64;
> - bridge->conf.pref_mem_limit = PCI_PREF_RANGE_TYPE_64;
> + bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
> + bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
>
> /* Support interrupt A for MSI feature */
> bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE;
> --
> 2.7.4
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2019-10-17 12:44 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-07-16 12:12 [PATCH v2] PCI: aardvark: fix big endian support Grzegorz Jaszczyk
2019-09-30 8:17 ` Grzegorz Jaszczyk
2019-09-30 14:39 ` Lorenzo Pieralisi
2019-10-04 8:38 ` Grzegorz Jaszczyk
2019-10-17 12:43 ` Lorenzo Pieralisi
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).