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From: Mike Leach <mike.leach@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Coresight ML <coresight@lists.linaro.org>,
	anshuman.khandual@arm.com,
	Mathieu Poirier <mathieu.poirier@linaro.org>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	Leo Yan <leo.yan@linaro.org>
Subject: Re: [PATCH 18/19] coresight: etm4x: Add support for sysreg only devices
Date: Wed, 23 Sep 2020 17:55:12 +0100	[thread overview]
Message-ID: <CAJ9a7VhCdhrWueHSSKpv2T8R3HqOhNaSxPX0LW49Vz+wEbDAuA@mail.gmail.com> (raw)
In-Reply-To: <5092f3d7-0dfa-b4b0-6854-5ad861c8e657@arm.com>

Hi Suzuki,

On Wed, 23 Sep 2020 at 12:47, Suzuki K Poulose <suzuki.poulose@arm.com> wrote:
>
> Hi Mike
>
> On 09/18/2020 04:35 PM, Mike Leach wrote:
> > Hi Suzuki,
> >
> > On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose <suzuki.poulose@arm.com> wrote:
> >>
> >> Add support for devices with system instruction access only.
> >> They don't have a memory mapped interface and thus are not
> >> AMBA devices.
> >>
> >> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> >> Cc: Mike Leach <mike.leach@linaro.org>
> >> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> >> ---
> >>   drivers/hwtracing/coresight/coresight-etm4x.c | 42 ++++++++++++++++++-
> >>   1 file changed, 40 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> >> index 7d5f942c2108..212713ffa37e 100644
> >> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> >> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> >> @@ -26,6 +26,7 @@
> >>   #include <linux/seq_file.h>
> >>   #include <linux/uaccess.h>
> >>   #include <linux/perf_event.h>
> >> +#include <linux/platform_device.h>
> >>   #include <linux/pm_runtime.h>
> >>   #include <linux/property.h>
> >>   #include <asm/sections.h>
> >> @@ -1712,6 +1713,20 @@ static int etm4_probe_amba(struct amba_device *adev, const struct amba_id *id)
> >>          return ret;
> >>   }
> >>
> >> +static int etm4_probe_platform_dev(struct platform_device *pdev)
> >> +{
> >> +       int ret;
> >> +
> >> +       pm_runtime_get_noresume(&pdev->dev);
> >> +       pm_runtime_set_active(&pdev->dev);
> >> +       pm_runtime_enable(&pdev->dev);
> >> +
> >
> > Right about here is where I would expect the sysreg access to
> > TRCDEVARCH etc, to determine if this is an ETM device that can be
> > supported by the driver.
> > This matches approximately the similar ID table checks that the AMBA
> > driver did to ensure a valid device match.
>
> The problem is, we have to do this on the target CPU and later do another
> one for feature check.
>
> > This logically separates "is this a device we support" from "what
> > features does this supported device have"
>

The additional point is that it also keeps the register access
specific code encapsulated in the register access specific area. The
whole point of the access abstraction is that the common code just
works.
Is it not better that the access decision is made as early as possible
and the access abstraction is set up, then the more code is common and
maintenance is easier going forwards?

> While I understand the logical argument, it doesn't buy us much. Even now we do an
> additional check on the supported architecture in the etm4x_probe() anyway and reject
> the unsupported CPUs there.

I do question the value of that check. It's been around since the
start of the driver, but perhaps has outlived its usefulness.

Even in the AMBA memory mapped case, by the time we get there, we have
matched the device based on supplied part numbers & binding
information in the device tree, so checking 4 bits (major version
number) out of a register does seem curious! If we have somehow got a
bunch of other things wrong, there is a 1 in 16 chance that this check
will fail too with a false positive.

Obviously I can see why you wouldn't want to rely on just that to
validate the component type for register access - DEVARCH is far
better for that use case.

The etmv3 version is a little more interesting - it checks 8 bits,
both maj and min versions, with specific checks on 3.3, 3.5, 1.0 and
1.1 (pft),

The remainder of the coresight drivers simply trust the part number
detection mechanisms.
Would it not be more consistent to do the same for ETMv4 as well?

> The only change here is we move the supported architecture
> check in to the etm4_init_arch_data() and stop the hard work if it is not supported.
>
> I would prefer to keep the current method if possible, while cleaning up the detection
> of the supported (old) devices as agreed in the other patch.
>
>
> Cheers
> Suzuki


Cheers

Mike

-- 
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

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  reply	other threads:[~2020-09-23 16:57 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-11  8:41 [PATCH 00/19] coresight: Support for ETMv4.4 system instructions Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 01/19] coresight: Introduce device access abstraction Suzuki K Poulose
2020-09-18 15:33   ` Mike Leach
2020-09-11  8:41 ` [PATCH 02/19] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 03/19] coresight: Convert coresight_timeout to use " Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 04/19] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 05/19] coresight: Use device access layer for Software lock/unlock operations Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-18 15:52     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 06/19] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 07/19] coresight: etm4x: Convert all register accesses Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 08/19] coresight: etm4x: Add commentary on the registers Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 09/19] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 10/19] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-22 10:20     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 11/19] coresight: etm4x: Check for OS and Software Lock Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 10:44     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 12/19] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 10:55     ` Suzuki K Poulose
2020-09-22 12:47       ` Mike Leach
2020-09-30 10:32         ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 13/19] coresight: etm4x: Clean up " Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 10:59     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 14/19] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 15/19] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 11:18     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 16/19] coresight: etm4x: Detect system instructions support Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 11:59     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 17/19] coresight: etm4x: Refactor probing routine Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-11  8:41 ` [PATCH 18/19] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-23 11:52     ` Suzuki K Poulose
2020-09-23 16:55       ` Mike Leach [this message]
2020-09-11  8:41 ` [PATCH 19/19] dts: bindings: coresight: ETMv4.4 system register access only units Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-24  9:48     ` Suzuki K Poulose
2020-09-24 10:08       ` Mike Leach
2020-09-18 15:33 ` [PATCH 00/19] coresight: Support for ETMv4.4 system instructions Mike Leach
2020-09-25  9:55   ` Suzuki K Poulose
2020-09-29 16:42     ` Mike Leach

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