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From: Mike Leach <mike.leach@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Coresight ML <coresight@lists.linaro.org>,
	Anshuman.Khandual@arm.com,
	Mathieu Poirier <mathieu.poirier@linaro.org>,
	linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
	Leo Yan <leo.yan@linaro.org>
Subject: Re: [PATCH 02/19] coresight: tpiu: Prepare for using coresight device access abstraction
Date: Fri, 18 Sep 2020 16:34:01 +0100	[thread overview]
Message-ID: <CAJ9a7VjapNFtf+R4uis7qGs2U1j+xUTVJgEU7tqAN6tAYrKM+g@mail.gmail.com> (raw)
In-Reply-To: <20200911084119.1080694-3-suzuki.poulose@arm.com>

Reviewed-by: Mike Leach <mike.leach@linaro.org>


On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose <suzuki.poulose@arm.com> wrote:
>
> Prepare the TPIU driver to make use of the CoreSight device access
> abstraction layer. The driver touches the device even before the
> coresight device is registered. Thus we could be accessing the
> devices without a csdev. As we are about to use the abstraction
> layer for accessing the device, pass in the access directly
> to avoid having to deal with the un-initialised csdev.
>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-tpiu.c | 30 +++++++++-----------
>  1 file changed, 13 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-tpiu.c b/drivers/hwtracing/coresight/coresight-tpiu.c
> index 4eb3f50618b6..cc7d7ed474f5 100644
> --- a/drivers/hwtracing/coresight/coresight-tpiu.c
> +++ b/drivers/hwtracing/coresight/coresight-tpiu.c
> @@ -60,49 +60,45 @@ struct tpiu_drvdata {
>         struct coresight_device *csdev;
>  };
>
> -static void tpiu_enable_hw(struct tpiu_drvdata *drvdata)
> +static void tpiu_enable_hw(struct csdev_access *csa)
>  {
> -       CS_UNLOCK(drvdata->base);
> +       CS_UNLOCK(csa->base);
>
>         /* TODO: fill this up */
>
> -       CS_LOCK(drvdata->base);
> +       CS_LOCK(csa->base);
>  }
>
>  static int tpiu_enable(struct coresight_device *csdev, u32 mode, void *__unused)
>  {
> -       struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> -
> -       tpiu_enable_hw(drvdata);
> +       tpiu_enable_hw(&csdev->access);
>         atomic_inc(csdev->refcnt);
>         dev_dbg(&csdev->dev, "TPIU enabled\n");
>         return 0;
>  }
>
> -static void tpiu_disable_hw(struct tpiu_drvdata *drvdata)
> +static void tpiu_disable_hw(struct csdev_access *csa)
>  {
> -       CS_UNLOCK(drvdata->base);
> +       CS_UNLOCK(csa->base);
>
>         /* Clear formatter and stop on flush */
> -       writel_relaxed(FFCR_STOP_FI, drvdata->base + TPIU_FFCR);
> +       csdev_access_relaxed_write32(csa, FFCR_STOP_FI, TPIU_FFCR);
>         /* Generate manual flush */
> -       writel_relaxed(FFCR_STOP_FI | FFCR_FON_MAN, drvdata->base + TPIU_FFCR);
> +       csdev_access_relaxed_write32(csa, FFCR_STOP_FI | FFCR_FON_MAN, TPIU_FFCR);
>         /* Wait for flush to complete */
> -       coresight_timeout(drvdata->base, TPIU_FFCR, FFCR_FON_MAN_BIT, 0);
> +       coresight_timeout(csa->base, TPIU_FFCR, FFCR_FON_MAN_BIT, 0);
>         /* Wait for formatter to stop */
> -       coresight_timeout(drvdata->base, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1);
> +       coresight_timeout(csa->base, TPIU_FFSR, FFSR_FT_STOPPED_BIT, 1);
>
> -       CS_LOCK(drvdata->base);
> +       CS_LOCK(csa->base);
>  }
>
>  static int tpiu_disable(struct coresight_device *csdev)
>  {
> -       struct tpiu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> -
>         if (atomic_dec_return(csdev->refcnt))
>                 return -EBUSY;
>
> -       tpiu_disable_hw(drvdata);
> +       tpiu_disable_hw(&csdev->access);
>
>         dev_dbg(&csdev->dev, "TPIU disabled\n");
>         return 0;
> @@ -152,7 +148,7 @@ static int tpiu_probe(struct amba_device *adev, const struct amba_id *id)
>         desc.access = CSDEV_ACCESS_IOMEM(base);
>
>         /* Disable tpiu to support older devices */
> -       tpiu_disable_hw(drvdata);
> +       tpiu_disable_hw(&desc.access);
>
>         pdata = coresight_get_platform_data(dev);
>         if (IS_ERR(pdata))
> --
> 2.24.1
>


--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

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  reply	other threads:[~2020-09-18 15:36 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-11  8:41 [PATCH 00/19] coresight: Support for ETMv4.4 system instructions Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 01/19] coresight: Introduce device access abstraction Suzuki K Poulose
2020-09-18 15:33   ` Mike Leach
2020-09-11  8:41 ` [PATCH 02/19] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach [this message]
2020-09-11  8:41 ` [PATCH 03/19] coresight: Convert coresight_timeout to use " Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 04/19] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 05/19] coresight: Use device access layer for Software lock/unlock operations Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-18 15:52     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 06/19] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 07/19] coresight: etm4x: Convert all register accesses Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 08/19] coresight: etm4x: Add commentary on the registers Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 09/19] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-11  8:41 ` [PATCH 10/19] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose
2020-09-18 15:34   ` Mike Leach
2020-09-22 10:20     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 11/19] coresight: etm4x: Check for OS and Software Lock Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 10:44     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 12/19] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 10:55     ` Suzuki K Poulose
2020-09-22 12:47       ` Mike Leach
2020-09-30 10:32         ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 13/19] coresight: etm4x: Clean up " Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 10:59     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 14/19] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 15/19] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 11:18     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 16/19] coresight: etm4x: Detect system instructions support Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-22 11:59     ` Suzuki K Poulose
2020-09-11  8:41 ` [PATCH 17/19] coresight: etm4x: Refactor probing routine Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-11  8:41 ` [PATCH 18/19] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-23 11:52     ` Suzuki K Poulose
2020-09-23 16:55       ` Mike Leach
2020-09-11  8:41 ` [PATCH 19/19] dts: bindings: coresight: ETMv4.4 system register access only units Suzuki K Poulose
2020-09-18 15:35   ` Mike Leach
2020-09-24  9:48     ` Suzuki K Poulose
2020-09-24 10:08       ` Mike Leach
2020-09-18 15:33 ` [PATCH 00/19] coresight: Support for ETMv4.4 system instructions Mike Leach
2020-09-25  9:55   ` Suzuki K Poulose
2020-09-29 16:42     ` Mike Leach

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