From: Mike Leach <mike.leach@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Coresight ML <coresight@lists.linaro.org>,
Anshuman.Khandual@arm.com,
Mathieu Poirier <mathieu.poirier@linaro.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
Leo Yan <leo.yan@linaro.org>
Subject: Re: [PATCH 12/19] coresight: etm4x: Cleanup secure exception level masks
Date: Fri, 18 Sep 2020 16:35:10 +0100 [thread overview]
Message-ID: <CAJ9a7ViX8EOFvnGExreF7PHHHJPf4q-smNsOjunkEkxkaQHPpQ@mail.gmail.com> (raw)
In-Reply-To: <20200911084119.1080694-13-suzuki.poulose@arm.com>
On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose <suzuki.poulose@arm.com> wrote:
>
> We rely on the ETM architecture version to decide whether
> Secure EL2 is available on the CPU for excluding the level
> for address comparators and viewinst main control register.
> We must instead use the TRCDIDR3.EXLEVEL_S field to detect
> the supported levels.
>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> drivers/hwtracing/coresight/coresight-etm4x.c | 13 +++----------
> drivers/hwtracing/coresight/coresight-etm4x.h | 6 ++++--
> 2 files changed, 7 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> index 7feb57108bdc..439e9da41006 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> @@ -758,7 +758,6 @@ static void etm4_init_arch_data(void *info)
> * TRCARCHMAJ, bits[11:8] architecture major versin number
> */
> drvdata->arch = BMVAL(etmidr1, 4, 11);
> - drvdata->config.arch = drvdata->arch;
>
> /* maximum size of resources */
> etmidr2 = etm4x_relaxed_read32(&csa, TRCIDR2);
> @@ -774,6 +773,7 @@ static void etm4_init_arch_data(void *info)
> drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
> /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
> drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
> + drvdata->config.s_ex_level = drvdata->s_ex_level;
> /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
> drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
>
> @@ -935,16 +935,9 @@ static u64 etm4_get_ns_access_type(struct etmv4_config *config)
> static u64 etm4_get_access_type(struct etmv4_config *config)
> {
> u64 access_type = etm4_get_ns_access_type(config);
> - u64 s_hyp = (config->arch & 0x0f) >= 0x4 ? ETM_EXLEVEL_S_HYP : 0;
>
> - /*
> - * EXLEVEL_S, bits[11:8], don't trace anything happening
> - * in secure state.
> - */
> - access_type |= (ETM_EXLEVEL_S_APP |
> - ETM_EXLEVEL_S_OS |
> - s_hyp |
> - ETM_EXLEVEL_S_MON);
> + /* All supported secure ELs are excluded */
> + access_type |= (u64)config->s_ex_level << TRCACATR_EXLEVEL_SHIFT;
>
What is the << TRCACATR_EXLEVEL_SHIFT doing here?
> return access_type;
> }
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index efd903688edd..407ad6647f36 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -522,6 +522,8 @@
> /* PowerDown Control Register bits */
> #define TRCPDCR_PU BIT(3)
>
> +#define TRCACATR_EXLEVEL_SHIFT 8
> +
> /* secure state access levels - TRCACATRn */
> #define ETM_EXLEVEL_S_APP BIT(8)
> #define ETM_EXLEVEL_S_OS BIT(9)
> @@ -604,7 +606,7 @@
> * @vmid_mask0: VM ID comparator mask for comparator 0-3.
> * @vmid_mask1: VM ID comparator mask for comparator 4-7.
> * @ext_inp: External input selection.
> - * @arch: ETM architecture version (for arch dependent config).
> + * @s_ex_level: Secure ELs where tracing is supported.
> */
> struct etmv4_config {
> u32 mode;
> @@ -648,7 +650,7 @@ struct etmv4_config {
> u32 vmid_mask0;
> u32 vmid_mask1;
> u32 ext_inp;
> - u8 arch;
> + u8 s_ex_level;
> };
>
> /**
> --
> 2.24.1
>
Perhaps this patch could be combined with the next patch as it
operates on the same set of flags.
Regards
Mike
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-09-18 15:40 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-11 8:41 [PATCH 00/19] coresight: Support for ETMv4.4 system instructions Suzuki K Poulose
2020-09-11 8:41 ` [PATCH 01/19] coresight: Introduce device access abstraction Suzuki K Poulose
2020-09-18 15:33 ` Mike Leach
2020-09-11 8:41 ` [PATCH 02/19] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose
2020-09-18 15:34 ` Mike Leach
2020-09-11 8:41 ` [PATCH 03/19] coresight: Convert coresight_timeout to use " Suzuki K Poulose
2020-09-18 15:34 ` Mike Leach
2020-09-11 8:41 ` [PATCH 04/19] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose
2020-09-18 15:34 ` Mike Leach
2020-09-11 8:41 ` [PATCH 05/19] coresight: Use device access layer for Software lock/unlock operations Suzuki K Poulose
2020-09-18 15:34 ` Mike Leach
2020-09-18 15:52 ` Suzuki K Poulose
2020-09-11 8:41 ` [PATCH 06/19] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose
2020-09-18 15:34 ` Mike Leach
2020-09-11 8:41 ` [PATCH 07/19] coresight: etm4x: Convert all register accesses Suzuki K Poulose
2020-09-18 15:34 ` Mike Leach
2020-09-11 8:41 ` [PATCH 08/19] coresight: etm4x: Add commentary on the registers Suzuki K Poulose
2020-09-18 15:34 ` Mike Leach
2020-09-11 8:41 ` [PATCH 09/19] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose
2020-09-18 15:34 ` Mike Leach
2020-09-11 8:41 ` [PATCH 10/19] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose
2020-09-18 15:34 ` Mike Leach
2020-09-22 10:20 ` Suzuki K Poulose
2020-09-11 8:41 ` [PATCH 11/19] coresight: etm4x: Check for OS and Software Lock Suzuki K Poulose
2020-09-18 15:35 ` Mike Leach
2020-09-22 10:44 ` Suzuki K Poulose
2020-09-11 8:41 ` [PATCH 12/19] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose
2020-09-18 15:35 ` Mike Leach [this message]
2020-09-22 10:55 ` Suzuki K Poulose
2020-09-22 12:47 ` Mike Leach
2020-09-30 10:32 ` Suzuki K Poulose
2020-09-11 8:41 ` [PATCH 13/19] coresight: etm4x: Clean up " Suzuki K Poulose
2020-09-18 15:35 ` Mike Leach
2020-09-22 10:59 ` Suzuki K Poulose
2020-09-11 8:41 ` [PATCH 14/19] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose
2020-09-11 8:41 ` [PATCH 15/19] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose
2020-09-18 15:35 ` Mike Leach
2020-09-22 11:18 ` Suzuki K Poulose
2020-09-11 8:41 ` [PATCH 16/19] coresight: etm4x: Detect system instructions support Suzuki K Poulose
2020-09-18 15:35 ` Mike Leach
2020-09-22 11:59 ` Suzuki K Poulose
2020-09-11 8:41 ` [PATCH 17/19] coresight: etm4x: Refactor probing routine Suzuki K Poulose
2020-09-18 15:35 ` Mike Leach
2020-09-11 8:41 ` [PATCH 18/19] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose
2020-09-18 15:35 ` Mike Leach
2020-09-23 11:52 ` Suzuki K Poulose
2020-09-23 16:55 ` Mike Leach
2020-09-11 8:41 ` [PATCH 19/19] dts: bindings: coresight: ETMv4.4 system register access only units Suzuki K Poulose
2020-09-18 15:35 ` Mike Leach
2020-09-24 9:48 ` Suzuki K Poulose
2020-09-24 10:08 ` Mike Leach
2020-09-18 15:33 ` [PATCH 00/19] coresight: Support for ETMv4.4 system instructions Mike Leach
2020-09-25 9:55 ` Suzuki K Poulose
2020-09-29 16:42 ` Mike Leach
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAJ9a7ViX8EOFvnGExreF7PHHHJPf4q-smNsOjunkEkxkaQHPpQ@mail.gmail.com \
--to=mike.leach@linaro.org \
--cc=Anshuman.Khandual@arm.com \
--cc=coresight@lists.linaro.org \
--cc=leo.yan@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=mathieu.poirier@linaro.org \
--cc=suzuki.poulose@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).