* [PATCH v3 1/9] memory: tegra: Implement SID override programming
2021-06-03 16:46 [PATCH v3 0/9] arm64: tegra: Prevent early SMMU faults Thierry Reding
@ 2021-06-03 16:46 ` Thierry Reding
2021-06-03 16:46 ` [PATCH v3 2/9] dt-bindings: arm-smmu: Add Tegra186 compatible string Thierry Reding
` (9 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Thierry Reding @ 2021-06-03 16:46 UTC (permalink / raw)
To: Thierry Reding, Will Deacon, Krzysztof Kozlowski
Cc: Joerg Roedel, iommu, Jon Hunter, Nicolin Chen, linux-tegra,
Robin Murphy, linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
Instead of programming all SID overrides during early boot, perform the
operation on-demand after the SMMU translations have been set up for a
device. This reuses data from device tree to match memory clients for a
device and programs the SID specified in device tree, which corresponds
to the SID used for the SMMU context banks for the device.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
drivers/memory/tegra/mc.c | 9 +++++
drivers/memory/tegra/tegra186.c | 72 +++++++++++++++++++++++++++++++++
include/soc/tegra/mc.h | 3 ++
3 files changed, 84 insertions(+)
diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index 11b83de9361c..3c5aae7abf35 100644
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -97,6 +97,15 @@ struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev)
}
EXPORT_SYMBOL_GPL(devm_tegra_memory_controller_get);
+int tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev)
+{
+ if (mc->soc->ops && mc->soc->ops->probe_device)
+ return mc->soc->ops->probe_device(mc, dev);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(tegra_mc_probe_device);
+
static int tegra_mc_block_dma_common(struct tegra_mc *mc,
const struct tegra_mc_reset *rst)
{
diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c
index 1f87915ccd62..e65eac5764d4 100644
--- a/drivers/memory/tegra/tegra186.c
+++ b/drivers/memory/tegra/tegra186.c
@@ -4,6 +4,7 @@
*/
#include <linux/io.h>
+#include <linux/iommu.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/of_device.h>
@@ -15,6 +16,10 @@
#include <dt-bindings/memory/tegra186-mc.h>
#endif
+#define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0)
+#define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16)
+#define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8)
+
static void tegra186_mc_program_sid(struct tegra_mc *mc)
{
unsigned int i;
@@ -66,10 +71,77 @@ static int tegra186_mc_resume(struct tegra_mc *mc)
return 0;
}
+static void tegra186_mc_client_sid_override(struct tegra_mc *mc,
+ const struct tegra_mc_client *client,
+ unsigned int sid)
+{
+ u32 value, old;
+
+ value = readl(mc->regs + client->regs.sid.security);
+ if ((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0) {
+ /*
+ * If the secure firmware has locked this down the override
+ * for this memory client, there's nothing we can do here.
+ */
+ if (value & MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED)
+ return;
+
+ /*
+ * Otherwise, try to set the override itself. Typically the
+ * secure firmware will never have set this configuration.
+ * Instead, it will either have disabled write access to
+ * this field, or it will already have set an explicit
+ * override itself.
+ */
+ WARN_ON((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0);
+
+ value |= MC_SID_STREAMID_SECURITY_OVERRIDE;
+ writel(value, mc->regs + client->regs.sid.security);
+ }
+
+ value = readl(mc->regs + client->regs.sid.override);
+ old = value & MC_SID_STREAMID_OVERRIDE_MASK;
+
+ if (old != sid) {
+ dev_dbg(mc->dev, "overriding SID %x for %s with %x\n", old,
+ client->name, sid);
+ writel(sid, mc->regs + client->regs.sid.override);
+ }
+}
+
+static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)
+{
+#if IS_ENABLED(CONFIG_IOMMU_API)
+ struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
+ struct of_phandle_args args;
+ unsigned int i, index = 0;
+
+ while (!of_parse_phandle_with_args(dev->of_node, "interconnects", "#interconnect-cells",
+ index, &args)) {
+ if (args.np == mc->dev->of_node && args.args_count != 0) {
+ for (i = 0; i < mc->soc->num_clients; i++) {
+ const struct tegra_mc_client *client = &mc->soc->clients[i];
+
+ if (client->id == args.args[0]) {
+ u32 sid = fwspec->ids[0] & MC_SID_STREAMID_OVERRIDE_MASK;
+
+ tegra186_mc_client_sid_override(mc, client, sid);
+ }
+ }
+ }
+
+ index++;
+ }
+#endif
+
+ return 0;
+}
+
const struct tegra_mc_ops tegra186_mc_ops = {
.probe = tegra186_mc_probe,
.remove = tegra186_mc_remove,
.resume = tegra186_mc_resume,
+ .probe_device = tegra186_mc_probe_device,
};
#if defined(CONFIG_ARCH_TEGRA_186_SOC)
diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h
index 1bd5aed81868..e19c2504a14b 100644
--- a/include/soc/tegra/mc.h
+++ b/include/soc/tegra/mc.h
@@ -180,6 +180,7 @@ struct tegra_mc_ops {
int (*suspend)(struct tegra_mc *mc);
int (*resume)(struct tegra_mc *mc);
irqreturn_t (*handle_irq)(int irq, void *data);
+ int (*probe_device)(struct tegra_mc *mc, struct device *dev);
};
struct tegra_mc_soc {
@@ -244,4 +245,6 @@ devm_tegra_memory_controller_get(struct device *dev)
}
#endif
+int tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev);
+
#endif /* __SOC_TEGRA_MC_H__ */
--
2.31.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v3 2/9] dt-bindings: arm-smmu: Add Tegra186 compatible string
2021-06-03 16:46 [PATCH v3 0/9] arm64: tegra: Prevent early SMMU faults Thierry Reding
2021-06-03 16:46 ` [PATCH v3 1/9] memory: tegra: Implement SID override programming Thierry Reding
@ 2021-06-03 16:46 ` Thierry Reding
2021-06-18 19:47 ` Rob Herring
2021-06-03 16:46 ` [PATCH v3 3/9] iommu/arm-smmu: Implement ->probe_finalize() Thierry Reding
` (8 subsequent siblings)
10 siblings, 1 reply; 23+ messages in thread
From: Thierry Reding @ 2021-06-03 16:46 UTC (permalink / raw)
To: Thierry Reding, Will Deacon, Krzysztof Kozlowski
Cc: Joerg Roedel, iommu, Jon Hunter, Nicolin Chen, linux-tegra,
Robin Murphy, linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
The ARM SMMU instantiations found on Tegra186 and later need inter-
operation with the memory controller in order to correctly program
stream ID overrides.
Furthermore, on Tegra194 multiple instances of the SMMU can gang up
to achieve higher throughput. In order to do this, they have to be
programmed identically so that the memory controller can interleave
memory accesses between them.
Add the Tegra186 compatible string to make sure the interoperation
with the memory controller can be enabled on that SoC generation.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index 9d27aa5111d4..1181b590db71 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -54,8 +54,14 @@ properties:
- const: arm,mmu-500
- description: NVIDIA SoCs that program two ARM MMU-500s identically
items:
+ - description: NVIDIA SoCs that require memory controller interaction
+ and may program multiple ARM MMU-500s identically with the memory
+ controller interleaving translations between multiple instances
+ for improved performance.
+ items:
- enum:
- - nvidia,tegra194-smmu
+ - const: nvidia,tegra194-smmu
+ - const: nvidia,tegra186-smmu
- const: nvidia,smmu-500
- items:
- const: arm,mmu-500
@@ -165,10 +171,11 @@ allOf:
contains:
enum:
- nvidia,tegra194-smmu
+ - nvidia,tegra186-smmu
then:
properties:
reg:
- minItems: 2
+ minItems: 1
maxItems: 2
else:
properties:
--
2.31.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PATCH v3 2/9] dt-bindings: arm-smmu: Add Tegra186 compatible string
2021-06-03 16:46 ` [PATCH v3 2/9] dt-bindings: arm-smmu: Add Tegra186 compatible string Thierry Reding
@ 2021-06-18 19:47 ` Rob Herring
2021-06-21 6:46 ` Krzysztof Kozlowski
0 siblings, 1 reply; 23+ messages in thread
From: Rob Herring @ 2021-06-18 19:47 UTC (permalink / raw)
To: Thierry Reding, Will Deacon
Cc: Krzysztof Kozlowski, Joerg Roedel, Linux IOMMU, Jon Hunter,
Nicolin Chen, linux-tegra, Robin Murphy, linux-arm-kernel
On Thu, Jun 3, 2021 at 10:49 AM Thierry Reding <thierry.reding@gmail.com> wrote:
>
> From: Thierry Reding <treding@nvidia.com>
>
> The ARM SMMU instantiations found on Tegra186 and later need inter-
> operation with the memory controller in order to correctly program
> stream ID overrides.
>
> Furthermore, on Tegra194 multiple instances of the SMMU can gang up
> to achieve higher throughput. In order to do this, they have to be
> programmed identically so that the memory controller can interleave
> memory accesses between them.
>
> Add the Tegra186 compatible string to make sure the interoperation
> with the memory controller can be enabled on that SoC generation.
>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> index 9d27aa5111d4..1181b590db71 100644
> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> @@ -54,8 +54,14 @@ properties:
> - const: arm,mmu-500
> - description: NVIDIA SoCs that program two ARM MMU-500s identically
> items:
> + - description: NVIDIA SoCs that require memory controller interaction
This is not valid jsonschema:
/builds/robherring/linux-dt/Documentation/devicetree/bindings/iommu/arm,smmu.yaml:
properties:compatible:oneOf:4:items: 'anyOf' conditional failed, one
must be fixed:
None is not of type 'object', 'boolean'
None is not of type 'array'
from schema $id: http://json-schema.org/draft-07/schema#
/builds/robherring/linux-dt/Documentation/devicetree/bindings/iommu/arm,smmu.yaml:
properties:compatible:oneOf:4:items: 'oneOf' conditional failed, one
must be fixed:
None is not of type 'object'
None is not of type 'array'
from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
/builds/robherring/linux-dt/Documentation/devicetree/bindings/iommu/arm,smmu.yaml:
properties:compatible:oneOf:4:items: 'oneOf' conditional failed, one
must be fixed:
None is not of type 'object'
None is not of type 'array'
from schema $id: http://devicetree.org/meta-schemas/string-array.yaml#
/builds/robherring/linux-dt/Documentation/devicetree/bindings/iommu/arm,smmu.yaml:
properties:compatible:oneOf:5:items: 'oneOf' conditional failed, one
must be fixed:
[{'enum': [{'const': 'nvidia,tegra194-smmu'}, {'const':
'nvidia,tegra186-smmu'}]}, {'const': 'nvidia,smmu-500'}] is not of
type 'object'
{'const': 'nvidia,tegra194-smmu'} is not of type 'string'
{'const': 'nvidia,tegra186-smmu'} is not of type 'string'
from schema $id: http://devicetree.org/meta-schemas/string-array.yaml#
This was not reviewed nor tested since the DT list was not Cc'ed.
Rob
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 2/9] dt-bindings: arm-smmu: Add Tegra186 compatible string
2021-06-18 19:47 ` Rob Herring
@ 2021-06-21 6:46 ` Krzysztof Kozlowski
2021-06-21 14:11 ` Thierry Reding
0 siblings, 1 reply; 23+ messages in thread
From: Krzysztof Kozlowski @ 2021-06-21 6:46 UTC (permalink / raw)
To: Rob Herring, Thierry Reding, Will Deacon
Cc: Joerg Roedel, Linux IOMMU, Jon Hunter, Nicolin Chen, linux-tegra,
Robin Murphy, linux-arm-kernel
On 18/06/2021 21:47, Rob Herring wrote:
> On Thu, Jun 3, 2021 at 10:49 AM Thierry Reding <thierry.reding@gmail.com> wrote:
>>
>> From: Thierry Reding <treding@nvidia.com>
>>
>> The ARM SMMU instantiations found on Tegra186 and later need inter-
>> operation with the memory controller in order to correctly program
>> stream ID overrides.
>>
>> Furthermore, on Tegra194 multiple instances of the SMMU can gang up
>> to achieve higher throughput. In order to do this, they have to be
>> programmed identically so that the memory controller can interleave
>> memory accesses between them.
>>
>> Add the Tegra186 compatible string to make sure the interoperation
>> with the memory controller can be enabled on that SoC generation.
>>
>> Signed-off-by: Thierry Reding <treding@nvidia.com>
>> ---
>> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 11 +++++++++--
>> 1 file changed, 9 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
>> index 9d27aa5111d4..1181b590db71 100644
>> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
>> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
>> @@ -54,8 +54,14 @@ properties:
>> - const: arm,mmu-500
>> - description: NVIDIA SoCs that program two ARM MMU-500s identically
>> items:
>> + - description: NVIDIA SoCs that require memory controller interaction
>
> This is not valid jsonschema:
>
> /builds/robherring/linux-dt/Documentation/devicetree/bindings/iommu/arm,smmu.yaml:
> properties:compatible:oneOf:4:items: 'anyOf' conditional failed, one
> must be fixed:
> None is not of type 'object', 'boolean'
> None is not of type 'array'
> from schema $id: http://json-schema.org/draft-07/schema#
> /builds/robherring/linux-dt/Documentation/devicetree/bindings/iommu/arm,smmu.yaml:
> properties:compatible:oneOf:4:items: 'oneOf' conditional failed, one
> must be fixed:
> None is not of type 'object'
> None is not of type 'array'
> from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
> /builds/robherring/linux-dt/Documentation/devicetree/bindings/iommu/arm,smmu.yaml:
> properties:compatible:oneOf:4:items: 'oneOf' conditional failed, one
> must be fixed:
> None is not of type 'object'
> None is not of type 'array'
> from schema $id: http://devicetree.org/meta-schemas/string-array.yaml#
> /builds/robherring/linux-dt/Documentation/devicetree/bindings/iommu/arm,smmu.yaml:
> properties:compatible:oneOf:5:items: 'oneOf' conditional failed, one
> must be fixed:
> [{'enum': [{'const': 'nvidia,tegra194-smmu'}, {'const':
> 'nvidia,tegra186-smmu'}]}, {'const': 'nvidia,smmu-500'}] is not of
> type 'object'
> {'const': 'nvidia,tegra194-smmu'} is not of type 'string'
> {'const': 'nvidia,tegra186-smmu'} is not of type 'string'
> from schema $id: http://devicetree.org/meta-schemas/string-array.yaml#
>
>
> This was not reviewed nor tested since the DT list was not Cc'ed.
Ugh, I see now weird empty item on a list... and not only DT list was
skipped - Thierry did not Cc you either.
My bad, I did not check that patch thoroughly before applying.
Thierry, please Cc folks mentioned by get_maintainer.pl. Either sent a
fix or a revert, if fix needs more time.
Additionally, why the patch changes reg to "minItems: 1" for
nvidia,tegra194-smmu?
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 2/9] dt-bindings: arm-smmu: Add Tegra186 compatible string
2021-06-21 6:46 ` Krzysztof Kozlowski
@ 2021-06-21 14:11 ` Thierry Reding
2021-06-21 15:54 ` Will Deacon
0 siblings, 1 reply; 23+ messages in thread
From: Thierry Reding @ 2021-06-21 14:11 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Will Deacon, Joerg Roedel, Linux IOMMU, Jon Hunter,
Nicolin Chen, linux-tegra, Robin Murphy, linux-arm-kernel
[-- Attachment #1.1: Type: text/plain, Size: 5100 bytes --]
On Mon, Jun 21, 2021 at 08:46:54AM +0200, Krzysztof Kozlowski wrote:
> On 18/06/2021 21:47, Rob Herring wrote:
> > On Thu, Jun 3, 2021 at 10:49 AM Thierry Reding <thierry.reding@gmail.com> wrote:
> >>
> >> From: Thierry Reding <treding@nvidia.com>
> >>
> >> The ARM SMMU instantiations found on Tegra186 and later need inter-
> >> operation with the memory controller in order to correctly program
> >> stream ID overrides.
> >>
> >> Furthermore, on Tegra194 multiple instances of the SMMU can gang up
> >> to achieve higher throughput. In order to do this, they have to be
> >> programmed identically so that the memory controller can interleave
> >> memory accesses between them.
> >>
> >> Add the Tegra186 compatible string to make sure the interoperation
> >> with the memory controller can be enabled on that SoC generation.
> >>
> >> Signed-off-by: Thierry Reding <treding@nvidia.com>
> >> ---
> >> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 11 +++++++++--
> >> 1 file changed, 9 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> >> index 9d27aa5111d4..1181b590db71 100644
> >> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> >> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> >> @@ -54,8 +54,14 @@ properties:
> >> - const: arm,mmu-500
> >> - description: NVIDIA SoCs that program two ARM MMU-500s identically
> >> items:
> >> + - description: NVIDIA SoCs that require memory controller interaction
> >
> > This is not valid jsonschema:
> >
> > /builds/robherring/linux-dt/Documentation/devicetree/bindings/iommu/arm,smmu.yaml:
> > properties:compatible:oneOf:4:items: 'anyOf' conditional failed, one
> > must be fixed:
> > None is not of type 'object', 'boolean'
> > None is not of type 'array'
> > from schema $id: http://json-schema.org/draft-07/schema#
> > /builds/robherring/linux-dt/Documentation/devicetree/bindings/iommu/arm,smmu.yaml:
> > properties:compatible:oneOf:4:items: 'oneOf' conditional failed, one
> > must be fixed:
> > None is not of type 'object'
> > None is not of type 'array'
> > from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
> > /builds/robherring/linux-dt/Documentation/devicetree/bindings/iommu/arm,smmu.yaml:
> > properties:compatible:oneOf:4:items: 'oneOf' conditional failed, one
> > must be fixed:
> > None is not of type 'object'
> > None is not of type 'array'
> > from schema $id: http://devicetree.org/meta-schemas/string-array.yaml#
> > /builds/robherring/linux-dt/Documentation/devicetree/bindings/iommu/arm,smmu.yaml:
> > properties:compatible:oneOf:5:items: 'oneOf' conditional failed, one
> > must be fixed:
> > [{'enum': [{'const': 'nvidia,tegra194-smmu'}, {'const':
> > 'nvidia,tegra186-smmu'}]}, {'const': 'nvidia,smmu-500'}] is not of
> > type 'object'
> > {'const': 'nvidia,tegra194-smmu'} is not of type 'string'
> > {'const': 'nvidia,tegra186-smmu'} is not of type 'string'
> > from schema $id: http://devicetree.org/meta-schemas/string-array.yaml#
> >
> >
> > This was not reviewed nor tested since the DT list was not Cc'ed.
>
> Ugh, I see now weird empty item on a list... and not only DT list was
> skipped - Thierry did not Cc you either.
This seemed like a too trivial addition to waste Rob's time on, so I
didn't add him (or the DT list for that matter) on Cc. The ARM SMMU
maintainers had reviewed this, which seemed like it was enough for what
the DT bindings change was doing.
In any case, I clearly should've checked the DT binding check output
more carefully. It's rather messy for Tegra because there's quite a few
that we haven't converted yet. I'll have to resume my effort to convert
the remaining ones and fixup the device trees so that we can actually
run the DT binding and DTB validation checks more usefully.
> My bad, I did not check that patch thoroughly before applying.
>
> Thierry, please Cc folks mentioned by get_maintainer.pl. Either sent a
> fix or a revert, if fix needs more time.
I've sent out a follow-up fix that removes the two bogus lines. It looks
like that was the result of a bad conflict resolution on my part.
> Additionally, why the patch changes reg to "minItems: 1" for
> nvidia,tegra194-smmu?
This is because originally the Tegra194 SMMU nodes were supposed to only
represent a "dual" instance. However, on Tegra194 there are three SMMU
instances in total, with the third instance (dedicated for isochronous
traffic) being completely separate and having only a single range of
registers.
That third instance was previously supposed to be covered by the normal
"arm,mmu-500" compatible string, but given that we really need that
interoperation between SMMU and memory controller for SID override
programming, we need the Tegra-specific compatible for the ISO instance
of the SMMU as well. And since that uses only one set of registers,
minItems had to become 1.
Thierry
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 2/9] dt-bindings: arm-smmu: Add Tegra186 compatible string
2021-06-21 14:11 ` Thierry Reding
@ 2021-06-21 15:54 ` Will Deacon
2021-06-21 16:03 ` Thierry Reding
0 siblings, 1 reply; 23+ messages in thread
From: Will Deacon @ 2021-06-21 15:54 UTC (permalink / raw)
To: Thierry Reding
Cc: Krzysztof Kozlowski, Rob Herring, Joerg Roedel, Linux IOMMU,
Jon Hunter, Nicolin Chen, linux-tegra, Robin Murphy,
linux-arm-kernel
On Mon, Jun 21, 2021 at 04:11:55PM +0200, Thierry Reding wrote:
> On Mon, Jun 21, 2021 at 08:46:54AM +0200, Krzysztof Kozlowski wrote:
> > On 18/06/2021 21:47, Rob Herring wrote:
> > > On Thu, Jun 3, 2021 at 10:49 AM Thierry Reding <thierry.reding@gmail.com> wrote:
> > >> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> > >> index 9d27aa5111d4..1181b590db71 100644
> > >> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> > >> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> > >> @@ -54,8 +54,14 @@ properties:
> > >> - const: arm,mmu-500
> > >> - description: NVIDIA SoCs that program two ARM MMU-500s identically
> > >> items:
> > >> + - description: NVIDIA SoCs that require memory controller interaction
> > >
> > > This is not valid jsonschema:
> > >
> > > /builds/robherring/linux-dt/Documentation/devicetree/bindings/iommu/arm,smmu.yaml:
> > > properties:compatible:oneOf:4:items: 'anyOf' conditional failed, one
> > > must be fixed:
> > > None is not of type 'object', 'boolean'
> > > None is not of type 'array'
> > > from schema $id: http://json-schema.org/draft-07/schema#
> > > /builds/robherring/linux-dt/Documentation/devicetree/bindings/iommu/arm,smmu.yaml:
> > > properties:compatible:oneOf:4:items: 'oneOf' conditional failed, one
> > > must be fixed:
> > > None is not of type 'object'
> > > None is not of type 'array'
> > > from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
> > > /builds/robherring/linux-dt/Documentation/devicetree/bindings/iommu/arm,smmu.yaml:
> > > properties:compatible:oneOf:4:items: 'oneOf' conditional failed, one
> > > must be fixed:
> > > None is not of type 'object'
> > > None is not of type 'array'
> > > from schema $id: http://devicetree.org/meta-schemas/string-array.yaml#
> > > /builds/robherring/linux-dt/Documentation/devicetree/bindings/iommu/arm,smmu.yaml:
> > > properties:compatible:oneOf:5:items: 'oneOf' conditional failed, one
> > > must be fixed:
> > > [{'enum': [{'const': 'nvidia,tegra194-smmu'}, {'const':
> > > 'nvidia,tegra186-smmu'}]}, {'const': 'nvidia,smmu-500'}] is not of
> > > type 'object'
> > > {'const': 'nvidia,tegra194-smmu'} is not of type 'string'
> > > {'const': 'nvidia,tegra186-smmu'} is not of type 'string'
> > > from schema $id: http://devicetree.org/meta-schemas/string-array.yaml#
> > >
> > >
> > > This was not reviewed nor tested since the DT list was not Cc'ed.
> >
> > Ugh, I see now weird empty item on a list... and not only DT list was
> > skipped - Thierry did not Cc you either.
>
> This seemed like a too trivial addition to waste Rob's time on, so I
> didn't add him (or the DT list for that matter) on Cc. The ARM SMMU
> maintainers had reviewed this, which seemed like it was enough for what
> the DT bindings change was doing.
Hmm, I didn't review it. I find the yaml stuff unreadable so I usually
wait for the DT folks to ack bindings changes before I queue them in the
SMMU tree.
Will
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 2/9] dt-bindings: arm-smmu: Add Tegra186 compatible string
2021-06-21 15:54 ` Will Deacon
@ 2021-06-21 16:03 ` Thierry Reding
0 siblings, 0 replies; 23+ messages in thread
From: Thierry Reding @ 2021-06-21 16:03 UTC (permalink / raw)
To: Will Deacon
Cc: Krzysztof Kozlowski, Rob Herring, Joerg Roedel, Linux IOMMU,
Jon Hunter, Nicolin Chen, linux-tegra, Robin Murphy,
linux-arm-kernel
[-- Attachment #1.1: Type: text/plain, Size: 3393 bytes --]
On Mon, Jun 21, 2021 at 04:54:18PM +0100, Will Deacon wrote:
> On Mon, Jun 21, 2021 at 04:11:55PM +0200, Thierry Reding wrote:
> > On Mon, Jun 21, 2021 at 08:46:54AM +0200, Krzysztof Kozlowski wrote:
> > > On 18/06/2021 21:47, Rob Herring wrote:
> > > > On Thu, Jun 3, 2021 at 10:49 AM Thierry Reding <thierry.reding@gmail.com> wrote:
> > > >> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> > > >> index 9d27aa5111d4..1181b590db71 100644
> > > >> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> > > >> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> > > >> @@ -54,8 +54,14 @@ properties:
> > > >> - const: arm,mmu-500
> > > >> - description: NVIDIA SoCs that program two ARM MMU-500s identically
> > > >> items:
> > > >> + - description: NVIDIA SoCs that require memory controller interaction
> > > >
> > > > This is not valid jsonschema:
> > > >
> > > > /builds/robherring/linux-dt/Documentation/devicetree/bindings/iommu/arm,smmu.yaml:
> > > > properties:compatible:oneOf:4:items: 'anyOf' conditional failed, one
> > > > must be fixed:
> > > > None is not of type 'object', 'boolean'
> > > > None is not of type 'array'
> > > > from schema $id: http://json-schema.org/draft-07/schema#
> > > > /builds/robherring/linux-dt/Documentation/devicetree/bindings/iommu/arm,smmu.yaml:
> > > > properties:compatible:oneOf:4:items: 'oneOf' conditional failed, one
> > > > must be fixed:
> > > > None is not of type 'object'
> > > > None is not of type 'array'
> > > > from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
> > > > /builds/robherring/linux-dt/Documentation/devicetree/bindings/iommu/arm,smmu.yaml:
> > > > properties:compatible:oneOf:4:items: 'oneOf' conditional failed, one
> > > > must be fixed:
> > > > None is not of type 'object'
> > > > None is not of type 'array'
> > > > from schema $id: http://devicetree.org/meta-schemas/string-array.yaml#
> > > > /builds/robherring/linux-dt/Documentation/devicetree/bindings/iommu/arm,smmu.yaml:
> > > > properties:compatible:oneOf:5:items: 'oneOf' conditional failed, one
> > > > must be fixed:
> > > > [{'enum': [{'const': 'nvidia,tegra194-smmu'}, {'const':
> > > > 'nvidia,tegra186-smmu'}]}, {'const': 'nvidia,smmu-500'}] is not of
> > > > type 'object'
> > > > {'const': 'nvidia,tegra194-smmu'} is not of type 'string'
> > > > {'const': 'nvidia,tegra186-smmu'} is not of type 'string'
> > > > from schema $id: http://devicetree.org/meta-schemas/string-array.yaml#
> > > >
> > > >
> > > > This was not reviewed nor tested since the DT list was not Cc'ed.
> > >
> > > Ugh, I see now weird empty item on a list... and not only DT list was
> > > skipped - Thierry did not Cc you either.
> >
> > This seemed like a too trivial addition to waste Rob's time on, so I
> > didn't add him (or the DT list for that matter) on Cc. The ARM SMMU
> > maintainers had reviewed this, which seemed like it was enough for what
> > the DT bindings change was doing.
>
> Hmm, I didn't review it. I find the yaml stuff unreadable so I usually
> wait for the DT folks to ack bindings changes before I queue them in the
> SMMU tree.
Alright... in the future I'll make sure to always Cc DT folks, even for
trivial stuff like this.
Thierry
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v3 3/9] iommu/arm-smmu: Implement ->probe_finalize()
2021-06-03 16:46 [PATCH v3 0/9] arm64: tegra: Prevent early SMMU faults Thierry Reding
2021-06-03 16:46 ` [PATCH v3 1/9] memory: tegra: Implement SID override programming Thierry Reding
2021-06-03 16:46 ` [PATCH v3 2/9] dt-bindings: arm-smmu: Add Tegra186 compatible string Thierry Reding
@ 2021-06-03 16:46 ` Thierry Reding
[not found] ` <CGME20210615180133eucas1p2563c2a173eca1fb5a1c5ccf654c23778@eucas1p2.samsung.com>
2021-06-03 16:46 ` [PATCH v3 4/9] iommu/arm-smmu: tegra: Detect number of instances at runtime Thierry Reding
` (7 subsequent siblings)
10 siblings, 1 reply; 23+ messages in thread
From: Thierry Reding @ 2021-06-03 16:46 UTC (permalink / raw)
To: Thierry Reding, Will Deacon, Krzysztof Kozlowski
Cc: Joerg Roedel, iommu, Jon Hunter, Nicolin Chen, linux-tegra,
Robin Murphy, linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
Implement a ->probe_finalize() callback that can be used by vendor
implementations to perform extra programming necessary after devices
have been attached to the SMMU.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- remove unnecessarily paranoid check
drivers/iommu/arm/arm-smmu/arm-smmu.c | 13 +++++++++++++
drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
index 6f72c4d208ca..d20ce4d57df2 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
@@ -1450,6 +1450,18 @@ static void arm_smmu_release_device(struct device *dev)
iommu_fwspec_free(dev);
}
+static void arm_smmu_probe_finalize(struct device *dev)
+{
+ struct arm_smmu_master_cfg *cfg;
+ struct arm_smmu_device *smmu;
+
+ cfg = dev_iommu_priv_get(dev);
+ smmu = cfg->smmu;
+
+ if (smmu->impl->probe_finalize)
+ smmu->impl->probe_finalize(smmu, dev);
+}
+
static struct iommu_group *arm_smmu_device_group(struct device *dev)
{
struct arm_smmu_master_cfg *cfg = dev_iommu_priv_get(dev);
@@ -1569,6 +1581,7 @@ static struct iommu_ops arm_smmu_ops = {
.iova_to_phys = arm_smmu_iova_to_phys,
.probe_device = arm_smmu_probe_device,
.release_device = arm_smmu_release_device,
+ .probe_finalize = arm_smmu_probe_finalize,
.device_group = arm_smmu_device_group,
.enable_nesting = arm_smmu_enable_nesting,
.set_pgtable_quirks = arm_smmu_set_pgtable_quirks,
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h
index c31a59d35c64..147c95e7c59c 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
@@ -439,6 +439,7 @@ struct arm_smmu_impl {
struct device *dev, int start);
void (*write_s2cr)(struct arm_smmu_device *smmu, int idx);
void (*write_sctlr)(struct arm_smmu_device *smmu, int idx, u32 reg);
+ void (*probe_finalize)(struct arm_smmu_device *smmu, struct device *dev);
};
#define INVALID_SMENDX -1
--
2.31.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v3 4/9] iommu/arm-smmu: tegra: Detect number of instances at runtime
2021-06-03 16:46 [PATCH v3 0/9] arm64: tegra: Prevent early SMMU faults Thierry Reding
` (2 preceding siblings ...)
2021-06-03 16:46 ` [PATCH v3 3/9] iommu/arm-smmu: Implement ->probe_finalize() Thierry Reding
@ 2021-06-03 16:46 ` Thierry Reding
2021-06-03 16:46 ` [PATCH v3 5/9] iommu/arm-smmu: tegra: Implement SID override programming Thierry Reding
` (6 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Thierry Reding @ 2021-06-03 16:46 UTC (permalink / raw)
To: Thierry Reding, Will Deacon, Krzysztof Kozlowski
Cc: Joerg Roedel, iommu, Jon Hunter, Nicolin Chen, linux-tegra,
Robin Murphy, linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
Parse the reg property in device tree and detect the number of instances
represented by a device tree node. This is subsequently needed in order
to support single-instance SMMUs with the Tegra implementation because
additional programming is needed to properly configure the SID override
registers in the memory controller.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v3:
- move .probe_finalize initialization to later patch
Changes in v2:
- provide a separate implementation to simplify single instances
drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c | 57 ++++++++++++++------
1 file changed, 41 insertions(+), 16 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
index 29117444e5a0..23889090eb01 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
@@ -20,13 +20,19 @@
* The third instance usage is through standard arm-smmu driver itself and
* is out of scope of this implementation.
*/
-#define NUM_SMMU_INSTANCES 2
+#define MAX_SMMU_INSTANCES 2
struct nvidia_smmu {
- struct arm_smmu_device smmu;
- void __iomem *bases[NUM_SMMU_INSTANCES];
+ struct arm_smmu_device smmu;
+ void __iomem *bases[MAX_SMMU_INSTANCES];
+ unsigned int num_instances;
};
+static inline struct nvidia_smmu *to_nvidia_smmu(struct arm_smmu_device *smmu)
+{
+ return container_of(smmu, struct nvidia_smmu, smmu);
+}
+
static inline void __iomem *nvidia_smmu_page(struct arm_smmu_device *smmu,
unsigned int inst, int page)
{
@@ -47,9 +53,10 @@ static u32 nvidia_smmu_read_reg(struct arm_smmu_device *smmu,
static void nvidia_smmu_write_reg(struct arm_smmu_device *smmu,
int page, int offset, u32 val)
{
+ struct nvidia_smmu *nvidia = to_nvidia_smmu(smmu);
unsigned int i;
- for (i = 0; i < NUM_SMMU_INSTANCES; i++) {
+ for (i = 0; i < nvidia->num_instances; i++) {
void __iomem *reg = nvidia_smmu_page(smmu, i, page) + offset;
writel_relaxed(val, reg);
@@ -67,9 +74,10 @@ static u64 nvidia_smmu_read_reg64(struct arm_smmu_device *smmu,
static void nvidia_smmu_write_reg64(struct arm_smmu_device *smmu,
int page, int offset, u64 val)
{
+ struct nvidia_smmu *nvidia = to_nvidia_smmu(smmu);
unsigned int i;
- for (i = 0; i < NUM_SMMU_INSTANCES; i++) {
+ for (i = 0; i < nvidia->num_instances; i++) {
void __iomem *reg = nvidia_smmu_page(smmu, i, page) + offset;
writeq_relaxed(val, reg);
@@ -79,6 +87,7 @@ static void nvidia_smmu_write_reg64(struct arm_smmu_device *smmu,
static void nvidia_smmu_tlb_sync(struct arm_smmu_device *smmu, int page,
int sync, int status)
{
+ struct nvidia_smmu *nvidia = to_nvidia_smmu(smmu);
unsigned int delay;
arm_smmu_writel(smmu, page, sync, 0);
@@ -90,7 +99,7 @@ static void nvidia_smmu_tlb_sync(struct arm_smmu_device *smmu, int page,
u32 val = 0;
unsigned int i;
- for (i = 0; i < NUM_SMMU_INSTANCES; i++) {
+ for (i = 0; i < nvidia->num_instances; i++) {
void __iomem *reg;
reg = nvidia_smmu_page(smmu, i, page) + status;
@@ -112,9 +121,10 @@ static void nvidia_smmu_tlb_sync(struct arm_smmu_device *smmu, int page,
static int nvidia_smmu_reset(struct arm_smmu_device *smmu)
{
+ struct nvidia_smmu *nvidia = to_nvidia_smmu(smmu);
unsigned int i;
- for (i = 0; i < NUM_SMMU_INSTANCES; i++) {
+ for (i = 0; i < nvidia->num_instances; i++) {
u32 val;
void __iomem *reg = nvidia_smmu_page(smmu, i, ARM_SMMU_GR0) +
ARM_SMMU_GR0_sGFSR;
@@ -157,8 +167,9 @@ static irqreturn_t nvidia_smmu_global_fault(int irq, void *dev)
unsigned int inst;
irqreturn_t ret = IRQ_NONE;
struct arm_smmu_device *smmu = dev;
+ struct nvidia_smmu *nvidia = to_nvidia_smmu(smmu);
- for (inst = 0; inst < NUM_SMMU_INSTANCES; inst++) {
+ for (inst = 0; inst < nvidia->num_instances; inst++) {
irqreturn_t irq_ret;
irq_ret = nvidia_smmu_global_fault_inst(irq, smmu, inst);
@@ -202,11 +213,13 @@ static irqreturn_t nvidia_smmu_context_fault(int irq, void *dev)
struct arm_smmu_device *smmu;
struct iommu_domain *domain = dev;
struct arm_smmu_domain *smmu_domain;
+ struct nvidia_smmu *nvidia;
smmu_domain = container_of(domain, struct arm_smmu_domain, domain);
smmu = smmu_domain->smmu;
+ nvidia = to_nvidia_smmu(smmu);
- for (inst = 0; inst < NUM_SMMU_INSTANCES; inst++) {
+ for (inst = 0; inst < nvidia->num_instances; inst++) {
irqreturn_t irq_ret;
/*
@@ -235,12 +248,16 @@ static const struct arm_smmu_impl nvidia_smmu_impl = {
.context_fault = nvidia_smmu_context_fault,
};
+static const struct arm_smmu_impl nvidia_smmu_single_impl = {
+};
+
struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu)
{
struct resource *res;
struct device *dev = smmu->dev;
struct nvidia_smmu *nvidia_smmu;
struct platform_device *pdev = to_platform_device(dev);
+ unsigned int i;
nvidia_smmu = devm_krealloc(dev, smmu, sizeof(*nvidia_smmu), GFP_KERNEL);
if (!nvidia_smmu)
@@ -248,16 +265,24 @@ struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu)
/* Instance 0 is ioremapped by arm-smmu.c. */
nvidia_smmu->bases[0] = smmu->base;
+ nvidia_smmu->num_instances++;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- if (!res)
- return ERR_PTR(-ENODEV);
+ for (i = 1; i < MAX_SMMU_INSTANCES; i++) {
+ res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+ if (!res)
+ break;
- nvidia_smmu->bases[1] = devm_ioremap_resource(dev, res);
- if (IS_ERR(nvidia_smmu->bases[1]))
- return ERR_CAST(nvidia_smmu->bases[1]);
+ nvidia_smmu->bases[i] = devm_ioremap_resource(dev, res);
+ if (IS_ERR(nvidia_smmu->bases[i]))
+ return ERR_CAST(nvidia_smmu->bases[i]);
+
+ nvidia_smmu->num_instances++;
+ }
- nvidia_smmu->smmu.impl = &nvidia_smmu_impl;
+ if (nvidia_smmu->num_instances == 1)
+ nvidia_smmu->smmu.impl = &nvidia_smmu_single_impl;
+ else
+ nvidia_smmu->smmu.impl = &nvidia_smmu_impl;
return &nvidia_smmu->smmu;
}
--
2.31.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v3 5/9] iommu/arm-smmu: tegra: Implement SID override programming
2021-06-03 16:46 [PATCH v3 0/9] arm64: tegra: Prevent early SMMU faults Thierry Reding
` (3 preceding siblings ...)
2021-06-03 16:46 ` [PATCH v3 4/9] iommu/arm-smmu: tegra: Detect number of instances at runtime Thierry Reding
@ 2021-06-03 16:46 ` Thierry Reding
2021-06-03 16:46 ` [PATCH v3 6/9] iommu/arm-smmu: Use Tegra implementation on Tegra186 Thierry Reding
` (5 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Thierry Reding @ 2021-06-03 16:46 UTC (permalink / raw)
To: Thierry Reding, Will Deacon, Krzysztof Kozlowski
Cc: Joerg Roedel, iommu, Jon Hunter, Nicolin Chen, linux-tegra,
Robin Murphy, linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
The secure firmware keeps some SID override registers set as passthrough
in order to allow devices such as the display controller to operate with
no knowledge of SMMU translations until an operating system driver takes
over. This is needed in order to seamlessly transition from the firmware
framebuffer to the OS framebuffer.
Upon successfully attaching a device to the SMMU and in the process
creating identity mappings for memory regions that are being accessed,
the Tegra implementation will call into the memory controller driver to
program the override SIDs appropriately.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v3:
- move .probe_finalize initialization to this patch
drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c | 33 ++++++++++++++++++--
1 file changed, 30 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
index 23889090eb01..01e9b50b10a1 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
@@ -7,6 +7,8 @@
#include <linux/platform_device.h>
#include <linux/slab.h>
+#include <soc/tegra/mc.h>
+
#include "arm-smmu.h"
/*
@@ -15,10 +17,17 @@
* interleaved IOVA accesses across them and translates accesses from
* non-isochronous HW devices.
* Third one is used for translating accesses from isochronous HW devices.
+ *
+ * In addition, the SMMU driver needs to coordinate with the memory controller
+ * driver to ensure that the right SID override is programmed for any given
+ * memory client. This is necessary to allow for use-case such as seamlessly
+ * handing over the display controller configuration from the firmware to the
+ * kernel.
+ *
* This implementation supports programming of the two instances that must
- * be programmed identically.
- * The third instance usage is through standard arm-smmu driver itself and
- * is out of scope of this implementation.
+ * be programmed identically and takes care of invoking the memory controller
+ * driver for SID override programming after devices have been attached to an
+ * SMMU instance.
*/
#define MAX_SMMU_INSTANCES 2
@@ -26,6 +35,7 @@ struct nvidia_smmu {
struct arm_smmu_device smmu;
void __iomem *bases[MAX_SMMU_INSTANCES];
unsigned int num_instances;
+ struct tegra_mc *mc;
};
static inline struct nvidia_smmu *to_nvidia_smmu(struct arm_smmu_device *smmu)
@@ -237,6 +247,17 @@ static irqreturn_t nvidia_smmu_context_fault(int irq, void *dev)
return ret;
}
+static void nvidia_smmu_probe_finalize(struct arm_smmu_device *smmu, struct device *dev)
+{
+ struct nvidia_smmu *nvidia = to_nvidia_smmu(smmu);
+ int err;
+
+ err = tegra_mc_probe_device(nvidia->mc, dev);
+ if (err < 0)
+ dev_err(smmu->dev, "memory controller probe failed for %s: %d\n",
+ dev_name(dev), err);
+}
+
static const struct arm_smmu_impl nvidia_smmu_impl = {
.read_reg = nvidia_smmu_read_reg,
.write_reg = nvidia_smmu_write_reg,
@@ -246,9 +267,11 @@ static const struct arm_smmu_impl nvidia_smmu_impl = {
.tlb_sync = nvidia_smmu_tlb_sync,
.global_fault = nvidia_smmu_global_fault,
.context_fault = nvidia_smmu_context_fault,
+ .probe_finalize = nvidia_smmu_probe_finalize,
};
static const struct arm_smmu_impl nvidia_smmu_single_impl = {
+ .probe_finalize = nvidia_smmu_probe_finalize,
};
struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu)
@@ -263,6 +286,10 @@ struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu)
if (!nvidia_smmu)
return ERR_PTR(-ENOMEM);
+ nvidia_smmu->mc = devm_tegra_memory_controller_get(dev);
+ if (IS_ERR(nvidia_smmu->mc))
+ return ERR_CAST(nvidia_smmu->mc);
+
/* Instance 0 is ioremapped by arm-smmu.c. */
nvidia_smmu->bases[0] = smmu->base;
nvidia_smmu->num_instances++;
--
2.31.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v3 6/9] iommu/arm-smmu: Use Tegra implementation on Tegra186
2021-06-03 16:46 [PATCH v3 0/9] arm64: tegra: Prevent early SMMU faults Thierry Reding
` (4 preceding siblings ...)
2021-06-03 16:46 ` [PATCH v3 5/9] iommu/arm-smmu: tegra: Implement SID override programming Thierry Reding
@ 2021-06-03 16:46 ` Thierry Reding
2021-06-03 16:46 ` [PATCH v3 7/9] arm64: tegra: Use correct compatible string for Tegra186 SMMU Thierry Reding
` (4 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Thierry Reding @ 2021-06-03 16:46 UTC (permalink / raw)
To: Thierry Reding, Will Deacon, Krzysztof Kozlowski
Cc: Joerg Roedel, iommu, Jon Hunter, Nicolin Chen, linux-tegra,
Robin Murphy, linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
Tegra186 requires the same SID override programming as Tegra194 in order
to seamlessly transition from the firmware framebuffer to the Linux
framebuffer, so the Tegra implementation needs to be used on Tegra186
devices as well.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
drivers/iommu/arm/arm-smmu/arm-smmu-impl.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
index 136872e77195..9f465e146799 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-impl.c
@@ -211,7 +211,8 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu)
if (of_property_read_bool(np, "calxeda,smmu-secure-config-access"))
smmu->impl = &calxeda_impl;
- if (of_device_is_compatible(np, "nvidia,tegra194-smmu"))
+ if (of_device_is_compatible(np, "nvidia,tegra194-smmu") ||
+ of_device_is_compatible(np, "nvidia,tegra186-smmu"))
return nvidia_smmu_impl_init(smmu);
smmu = qcom_smmu_impl_init(smmu);
--
2.31.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v3 7/9] arm64: tegra: Use correct compatible string for Tegra186 SMMU
2021-06-03 16:46 [PATCH v3 0/9] arm64: tegra: Prevent early SMMU faults Thierry Reding
` (5 preceding siblings ...)
2021-06-03 16:46 ` [PATCH v3 6/9] iommu/arm-smmu: Use Tegra implementation on Tegra186 Thierry Reding
@ 2021-06-03 16:46 ` Thierry Reding
2021-06-03 16:46 ` [PATCH v3 8/9] arm64: tegra: Hook up memory controller to SMMU on Tegra186 Thierry Reding
` (3 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Thierry Reding @ 2021-06-03 16:46 UTC (permalink / raw)
To: Thierry Reding, Will Deacon, Krzysztof Kozlowski
Cc: Joerg Roedel, iommu, Jon Hunter, Nicolin Chen, linux-tegra,
Robin Murphy, linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
The SMMU found on Tegra186 requires interoperation with the memory
controller in order to program stream ID overrides. The generic ARM SMMU
500 compatible is therefore inaccurate. Replace it with a more correct,
SoC-specific compatible string.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 9f75bbf00cf7..a173f40256ae 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1082,7 +1082,7 @@ pci@3,0 {
};
smmu: iommu@12000000 {
- compatible = "arm,mmu-500";
+ compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500";
reg = <0 0x12000000 0 0x800000>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
--
2.31.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v3 8/9] arm64: tegra: Hook up memory controller to SMMU on Tegra186
2021-06-03 16:46 [PATCH v3 0/9] arm64: tegra: Prevent early SMMU faults Thierry Reding
` (6 preceding siblings ...)
2021-06-03 16:46 ` [PATCH v3 7/9] arm64: tegra: Use correct compatible string for Tegra186 SMMU Thierry Reding
@ 2021-06-03 16:46 ` Thierry Reding
2021-06-03 16:46 ` [PATCH v3 9/9] arm64: tegra: Enable SMMU support on Tegra194 Thierry Reding
` (2 subsequent siblings)
10 siblings, 0 replies; 23+ messages in thread
From: Thierry Reding @ 2021-06-03 16:46 UTC (permalink / raw)
To: Thierry Reding, Will Deacon, Krzysztof Kozlowski
Cc: Joerg Roedel, iommu, Jon Hunter, Nicolin Chen, linux-tegra,
Robin Murphy, linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
On Tegra186 and later, the memory controller needs to be programmed in
coordination with any of the ARM SMMU instances to configure the stream
ID used for each memory client.
To support this, add a phandle reference to the memory controller to the
SMMU device tree node.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index a173f40256ae..d02f6bf3e2ca 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1152,6 +1152,8 @@ smmu: iommu@12000000 {
stream-match-mask = <0x7f80>;
#global-interrupts = <1>;
#iommu-cells = <1>;
+
+ nvidia,memory-controller = <&mc>;
};
host1x@13e00000 {
--
2.31.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 23+ messages in thread
* [PATCH v3 9/9] arm64: tegra: Enable SMMU support on Tegra194
2021-06-03 16:46 [PATCH v3 0/9] arm64: tegra: Prevent early SMMU faults Thierry Reding
` (7 preceding siblings ...)
2021-06-03 16:46 ` [PATCH v3 8/9] arm64: tegra: Hook up memory controller to SMMU on Tegra186 Thierry Reding
@ 2021-06-03 16:46 ` Thierry Reding
2021-06-03 19:51 ` (subset) [PATCH v3 0/9] arm64: tegra: Prevent early SMMU faults Krzysztof Kozlowski
2021-06-11 6:48 ` Krzysztof Kozlowski
10 siblings, 0 replies; 23+ messages in thread
From: Thierry Reding @ 2021-06-03 16:46 UTC (permalink / raw)
To: Thierry Reding, Will Deacon, Krzysztof Kozlowski
Cc: Joerg Roedel, iommu, Jon Hunter, Nicolin Chen, linux-tegra,
Robin Murphy, linux-arm-kernel
From: Thierry Reding <treding@nvidia.com>
Add the device tree node for the dual-SMMU found on Tegra194 and hook up
peripherals such as host1x, BPMP, HDA, SDMMC, EQOS and VIC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 86 ++++++++++++++++++++++++
1 file changed, 86 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index ee71e0d9f895..94e1d8f1a79f 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -62,6 +62,7 @@ ethernet@2490000 {
interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_EQOS>;
status = "disabled";
snps,write-requests = <1>;
@@ -733,6 +734,7 @@ sdmmc1: mmc@3400000 {
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
<&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_SDMMC1>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout =
<0x07>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout =
@@ -759,6 +761,7 @@ sdmmc3: mmc@3440000 {
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_SDMMC3>;
nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
@@ -790,6 +793,7 @@ sdmmc4: mmc@3460000 {
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,
<&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_SDMMC4>;
nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
@@ -821,6 +825,7 @@ hda@3510000 {
interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_HDA>;
status = "disabled";
};
@@ -1300,6 +1305,84 @@ pmc: pmc@c360000 {
interrupt-controller;
};
+ smmu: iommu@12000000 {
+ compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
+ reg = <0x12000000 0x800000>,
+ <0x11000000 0x800000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ stream-match-mask = <0x7f80>;
+ #global-interrupts = <2>;
+ #iommu-cells = <1>;
+
+ nvidia,memory-controller = <&mc>;
+ status = "okay";
+ };
+
host1x@13e00000 {
compatible = "nvidia,tegra194-host1x";
reg = <0x13e00000 0x10000>,
@@ -1319,6 +1402,7 @@ host1x@13e00000 {
ranges = <0x15000000 0x15000000 0x01000000>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;
interconnect-names = "dma-mem";
+ iommus = <&smmu TEGRA194_SID_HOST1X>;
display-hub@15200000 {
compatible = "nvidia,tegra194-display";
@@ -1430,6 +1514,7 @@ vic@15340000 {
interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>,
<&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_VIC>;
};
dpaux0: dpaux@155c0000 {
@@ -2136,6 +2221,7 @@ bpmp: bpmp {
<&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>;
interconnect-names = "read", "write", "dma-mem", "dma-write";
+ iommus = <&smmu TEGRA194_SID_BPMP>;
bpmp_i2c: i2c {
compatible = "nvidia,tegra186-bpmp-i2c";
--
2.31.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: (subset) [PATCH v3 0/9] arm64: tegra: Prevent early SMMU faults
2021-06-03 16:46 [PATCH v3 0/9] arm64: tegra: Prevent early SMMU faults Thierry Reding
` (8 preceding siblings ...)
2021-06-03 16:46 ` [PATCH v3 9/9] arm64: tegra: Enable SMMU support on Tegra194 Thierry Reding
@ 2021-06-03 19:51 ` Krzysztof Kozlowski
2021-06-11 6:48 ` Krzysztof Kozlowski
10 siblings, 0 replies; 23+ messages in thread
From: Krzysztof Kozlowski @ 2021-06-03 19:51 UTC (permalink / raw)
To: Thierry Reding, Will Deacon
Cc: Krzysztof Kozlowski, linux-tegra, Nicolin Chen, linux-arm-kernel,
Robin Murphy, Jon Hunter, iommu
On Thu, 3 Jun 2021 18:46:23 +0200, Thierry Reding wrote:
> this is a set of patches that is the result of earlier discussions
> regarding early identity mappings that are needed to avoid SMMU faults
> during early boot.
>
> The goal here is to avoid early identity mappings altogether and instead
> postpone the need for the identity mappings to when devices are attached
> to the SMMU. This works by making the SMMU driver coordinate with the
> memory controller driver on when to start enforcing SMMU translations.
> This makes Tegra behave in a more standard way and pushes the code to
> deal with the Tegra-specific programming into the NVIDIA SMMU
> implementation.
>
> [...]
Applied, thanks!
[1/9] memory: tegra: Implement SID override programming
commit: 393d66fd2cacba3e6aa95d7bb38790bfb7b1cc3a
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 0/9] arm64: tegra: Prevent early SMMU faults
2021-06-03 16:46 [PATCH v3 0/9] arm64: tegra: Prevent early SMMU faults Thierry Reding
` (9 preceding siblings ...)
2021-06-03 19:51 ` (subset) [PATCH v3 0/9] arm64: tegra: Prevent early SMMU faults Krzysztof Kozlowski
@ 2021-06-11 6:48 ` Krzysztof Kozlowski
2021-06-11 12:05 ` Thierry Reding
10 siblings, 1 reply; 23+ messages in thread
From: Krzysztof Kozlowski @ 2021-06-11 6:48 UTC (permalink / raw)
To: Will Deacon, Thierry Reding
Cc: Krzysztof Kozlowski, Joerg Roedel, iommu, Jon Hunter,
Nicolin Chen, linux-tegra, Robin Murphy, linux-arm-kernel
On Thu, 3 Jun 2021 18:46:23 +0200, Thierry Reding wrote:
> this is a set of patches that is the result of earlier discussions
> regarding early identity mappings that are needed to avoid SMMU faults
> during early boot.
>
> The goal here is to avoid early identity mappings altogether and instead
> postpone the need for the identity mappings to when devices are attached
> to the SMMU. This works by making the SMMU driver coordinate with the
> memory controller driver on when to start enforcing SMMU translations.
> This makes Tegra behave in a more standard way and pushes the code to
> deal with the Tegra-specific programming into the NVIDIA SMMU
> implementation.
>
> [...]
Applied, thanks!
[1/9] memory: tegra: Implement SID override programming
(no commit info)
[2/9] dt-bindings: arm-smmu: Add Tegra186 compatible string
commit: 4287861dca9d77490ee50de42aa3ada92da86c9d
[3/9] - skipped
[4/9] iommu/arm-smmu: tegra: Detect number of instances at runtime
commit: 7ecbf253f8d64c08de28d16a66e3abbe873f6c9f
[5/9] iommu/arm-smmu: tegra: Implement SID override programming
commit: 8eb68595475ac5fcaaa3718a173283df48cb4ef1
[6/9] iommu/arm-smmu: Use Tegra implementation on Tegra186
commit: 2c1bc371268862a991a6498e1dddc8971b9076b8
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 0/9] arm64: tegra: Prevent early SMMU faults
2021-06-11 6:48 ` Krzysztof Kozlowski
@ 2021-06-11 12:05 ` Thierry Reding
0 siblings, 0 replies; 23+ messages in thread
From: Thierry Reding @ 2021-06-11 12:05 UTC (permalink / raw)
To: Krzysztof Kozlowski, Will Deacon
Cc: Joerg Roedel, iommu, Jon Hunter, Nicolin Chen, linux-tegra,
Robin Murphy, linux-arm-kernel
[-- Attachment #1.1: Type: text/plain, Size: 1569 bytes --]
On Fri, Jun 11, 2021 at 08:48:00AM +0200, Krzysztof Kozlowski wrote:
> On Thu, 3 Jun 2021 18:46:23 +0200, Thierry Reding wrote:
> > this is a set of patches that is the result of earlier discussions
> > regarding early identity mappings that are needed to avoid SMMU faults
> > during early boot.
> >
> > The goal here is to avoid early identity mappings altogether and instead
> > postpone the need for the identity mappings to when devices are attached
> > to the SMMU. This works by making the SMMU driver coordinate with the
> > memory controller driver on when to start enforcing SMMU translations.
> > This makes Tegra behave in a more standard way and pushes the code to
> > deal with the Tegra-specific programming into the NVIDIA SMMU
> > implementation.
> >
> > [...]
>
> Applied, thanks!
>
> [1/9] memory: tegra: Implement SID override programming
> (no commit info)
> [2/9] dt-bindings: arm-smmu: Add Tegra186 compatible string
> commit: 4287861dca9d77490ee50de42aa3ada92da86c9d
>
> [3/9] - skipped
>
> [4/9] iommu/arm-smmu: tegra: Detect number of instances at runtime
> commit: 7ecbf253f8d64c08de28d16a66e3abbe873f6c9f
> [5/9] iommu/arm-smmu: tegra: Implement SID override programming
> commit: 8eb68595475ac5fcaaa3718a173283df48cb4ef1
> [6/9] iommu/arm-smmu: Use Tegra implementation on Tegra186
> commit: 2c1bc371268862a991a6498e1dddc8971b9076b8
I've applied patches 7-9 to the Tegra tree.
Thanks Krzysztof and Will for your help in getting this over the finish
line!
Thierry
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 23+ messages in thread