From: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
To: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
Rajendra Nayak <rnayak@codeaurora.org>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
MSM <linux-arm-msm@vger.kernel.org>,
Marc Gonzalez <marc.w.gonzalez@free.fr>,
lkml <linux-kernel@vger.kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
David Brown <david.brown@linaro.org>,
Andy Gross <agross@kernel.org>,
Sibi Sankar <sibis@codeaurora.org>,
Vivek Gautam <vivek.gautam@codeaurora.org>,
Leo Yan <leo.yan@linaro.org>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCHv9 2/3] arm64: dts: qcom: msm8998: Add Coresight support
Date: Tue, 1 Oct 2019 10:13:47 -0600 [thread overview]
Message-ID: <CAOCk7NrK+wY8jfHdS8781NOQtyLm2RRe1NW2Rm3_zeaot0Q99Q@mail.gmail.com> (raw)
In-Reply-To: <90114e06825e537c3aafd3de5c78743a9de6fadc.1564550873.git.saiprakash.ranjan@codeaurora.org>
Sai,
This patch breaks boot on the 835 laptops. However, I haven't seen
the same issue on the MTP. I wonder, is coresight expected to work
with production fused devices? I wonder if thats the difference
between the laptop and MTP that is causing the issue.
Let me know what I can do to help debug.
On Tue, Jul 30, 2019 at 11:59 PM Sai Prakash Ranjan
<saiprakash.ranjan@codeaurora.org> wrote:
>
> Enable coresight support by adding device nodes for the
> available source, sinks and channel blocks on MSM8998.
>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> arch/arm64/boot/dts/qcom/msm8998.dtsi | 435 ++++++++++++++++++++++++++
> 1 file changed, 435 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> index c13ed7aeb1e0..ad661fcc9e1b 100644
> --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
> @@ -822,6 +822,441 @@
> #interrupt-cells = <0x2>;
> };
>
> + stm@6002000 {
> + compatible = "arm,coresight-stm", "arm,primecell";
> + reg = <0x06002000 0x1000>,
> + <0x16280000 0x180000>;
> + reg-names = "stm-base", "stm-data-base";
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + out-ports {
> + port {
> + stm_out: endpoint {
> + remote-endpoint = <&funnel0_in7>;
> + };
> + };
> + };
> + };
> +
> + funnel@6041000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + reg = <0x06041000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + out-ports {
> + port {
> + funnel0_out: endpoint {
> + remote-endpoint =
> + <&merge_funnel_in0>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@7 {
> + reg = <7>;
> + funnel0_in7: endpoint {
> + remote-endpoint = <&stm_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@6042000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + reg = <0x06042000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + out-ports {
> + port {
> + funnel1_out: endpoint {
> + remote-endpoint =
> + <&merge_funnel_in1>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@6 {
> + reg = <6>;
> + funnel1_in6: endpoint {
> + remote-endpoint =
> + <&apss_merge_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@6045000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + reg = <0x06045000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + out-ports {
> + port {
> + merge_funnel_out: endpoint {
> + remote-endpoint =
> + <&etf_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + merge_funnel_in0: endpoint {
> + remote-endpoint =
> + <&funnel0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + merge_funnel_in1: endpoint {
> + remote-endpoint =
> + <&funnel1_out>;
> + };
> + };
> + };
> + };
> +
> + replicator@6046000 {
> + compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> + reg = <0x06046000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + out-ports {
> + port {
> + replicator_out: endpoint {
> + remote-endpoint = <&etr_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + port {
> + replicator_in: endpoint {
> + remote-endpoint = <&etf_out>;
> + };
> + };
> + };
> + };
> +
> + etf@6047000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x06047000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + out-ports {
> + port {
> + etf_out: endpoint {
> + remote-endpoint =
> + <&replicator_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + port {
> + etf_in: endpoint {
> + remote-endpoint =
> + <&merge_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + etr@6048000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0x06048000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> + arm,scatter-gather;
> +
> + in-ports {
> + port {
> + etr_in: endpoint {
> + remote-endpoint =
> + <&replicator_out>;
> + };
> + };
> + };
> + };
> +
> + etm@7840000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x07840000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + cpu = <&CPU0>;
> +
> + out-ports {
> + port {
> + etm0_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in0>;
> + };
> + };
> + };
> + };
> +
> + etm@7940000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x07940000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + cpu = <&CPU1>;
> +
> + out-ports {
> + port {
> + etm1_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in1>;
> + };
> + };
> + };
> + };
> +
> + etm@7a40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x07a40000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + cpu = <&CPU2>;
> +
> + out-ports {
> + port {
> + etm2_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in2>;
> + };
> + };
> + };
> + };
> +
> + etm@7b40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x07b40000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + cpu = <&CPU3>;
> +
> + out-ports {
> + port {
> + etm3_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in3>;
> + };
> + };
> + };
> + };
> +
> + funnel@7b60000 { /* APSS Funnel */
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x07b60000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + out-ports {
> + port {
> + apss_funnel_out: endpoint {
> + remote-endpoint =
> + <&apss_merge_funnel_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + apss_funnel_in0: endpoint {
> + remote-endpoint =
> + <&etm0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + apss_funnel_in1: endpoint {
> + remote-endpoint =
> + <&etm1_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + apss_funnel_in2: endpoint {
> + remote-endpoint =
> + <&etm2_out>;
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> + apss_funnel_in3: endpoint {
> + remote-endpoint =
> + <&etm3_out>;
> + };
> + };
> +
> + port@4 {
> + reg = <4>;
> + apss_funnel_in4: endpoint {
> + remote-endpoint =
> + <&etm4_out>;
> + };
> + };
> +
> + port@5 {
> + reg = <5>;
> + apss_funnel_in5: endpoint {
> + remote-endpoint =
> + <&etm5_out>;
> + };
> + };
> +
> + port@6 {
> + reg = <6>;
> + apss_funnel_in6: endpoint {
> + remote-endpoint =
> + <&etm6_out>;
> + };
> + };
> +
> + port@7 {
> + reg = <7>;
> + apss_funnel_in7: endpoint {
> + remote-endpoint =
> + <&etm7_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@7b70000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + reg = <0x07b70000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + out-ports {
> + port {
> + apss_merge_funnel_out: endpoint {
> + remote-endpoint =
> + <&funnel1_in6>;
> + };
> + };
> + };
> +
> + in-ports {
> + port {
> + apss_merge_funnel_in: endpoint {
> + remote-endpoint =
> + <&apss_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + etm@7c40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x07c40000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + cpu = <&CPU4>;
> +
> + port{
> + etm4_out: endpoint {
> + remote-endpoint = <&apss_funnel_in4>;
> + };
> + };
> + };
> +
> + etm@7d40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x07d40000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + cpu = <&CPU5>;
> +
> + port{
> + etm5_out: endpoint {
> + remote-endpoint = <&apss_funnel_in5>;
> + };
> + };
> + };
> +
> + etm@7e40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x07e40000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + cpu = <&CPU6>;
> +
> + port{
> + etm6_out: endpoint {
> + remote-endpoint = <&apss_funnel_in6>;
> + };
> + };
> + };
> +
> + etm@7f40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0x07f40000 0x1000>;
> +
> + clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
> + clock-names = "apb_pclk", "atclk";
> +
> + cpu = <&CPU7>;
> +
> + port{
> + etm7_out: endpoint {
> + remote-endpoint = <&apss_funnel_in7>;
> + };
> + };
> + };
> +
> spmi_bus: spmi@800f000 {
> compatible = "qcom,spmi-pmic-arb";
> reg = <0x800f000 0x1000>,
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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next prev parent reply other threads:[~2019-10-01 16:14 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-31 5:57 [PATCHv9 0/3] Add coresight support for SDM845, MSM8998 and MSM8996 Sai Prakash Ranjan
2019-07-31 5:58 ` [PATCHv9 1/3] arm64: dts: qcom: sdm845: Add Coresight support Sai Prakash Ranjan
2019-07-31 6:05 ` Sai Prakash Ranjan
2019-08-07 10:08 ` Sai Prakash Ranjan
2019-08-07 10:12 ` Suzuki K Poulose
2019-08-07 11:16 ` Sai Prakash Ranjan
2019-07-31 5:58 ` [PATCHv9 2/3] arm64: dts: qcom: msm8998: " Sai Prakash Ranjan
2019-10-01 16:13 ` Jeffrey Hugo [this message]
2019-10-01 17:04 ` Sai Prakash Ranjan
2019-10-01 17:14 ` Jeffrey Hugo
2019-10-01 17:31 ` Suzuki K Poulose
2019-10-01 17:52 ` Sai Prakash Ranjan
2019-10-01 18:01 ` Jeffrey Hugo
2019-10-01 18:05 ` Sai Prakash Ranjan
2019-10-02 15:03 ` Mathieu Poirier
2019-10-02 15:21 ` Marc Gonzalez
2019-10-02 15:34 ` Mathieu Poirier
2019-10-02 15:49 ` Jeffrey Hugo
2019-10-03 10:20 ` Daniel Thompson
2019-10-03 10:52 ` Suzuki K Poulose
2019-10-03 12:52 ` Daniel Thompson
2019-07-31 5:58 ` [PATCHv9 3/3] arm64: dts: qcom: msm8996: " Sai Prakash Ranjan
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