From: Catalin Marinas <catalin.marinas@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: Mark Brown <broonie@kernel.org>, Will Deacon <will@kernel.org>,
Oleg Nesterov <oleg@redhat.com>,
James Morse <james.morse@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Shuah Khan <shuah@kernel.org>,
Alan Hayward <alan.hayward@arm.com>,
Luis Machado <luis.machado@arm.com>,
Szabolcs Nagy <szabolcs.nagy@arm.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v4 07/21] arm64/sme: Enable host kernel to access ZT0
Date: Mon, 6 Feb 2023 16:44:05 +0000 [thread overview]
Message-ID: <Y+EuVbkpQJk6z+Zu@arm.com> (raw)
In-Reply-To: <86y1pbywbb.wl-maz@kernel.org>
On Mon, Feb 06, 2023 at 09:31:20AM +0000, Marc Zyngier wrote:
> From a6c4aaccd33e453ffc8d8ea23a4dd4d9a263cc89 Mon Sep 17 00:00:00 2001
> From: Marc Zyngier <maz@kernel.org>
> Date: Mon, 6 Feb 2023 09:24:40 +0000
> Subject: [PATCH] arm64/sme: Fix __finalise_el2 SMEver check
>
> When checking for ID_AA64SMFR0_EL1.SMEver, __check_override assumes
> that the ID_AA64SMFR0_EL1 value is in x1, and the intent of the code
> is to reuse value read a few lines above.
>
> However, as the comment says at the beginning of the macro, x1 will
> be clobbered, and the checks always fails.
>
> The easiest fix is just to reload the id register before checking it.
>
> Fixes: f122576f3533 ("arm64/sme: Enable host kernel to access ZT0")
> Signed-off-by: Marc Zyngier <maz@kernel.org>
Thanks Marc. I queued it on top of the for-next/sme2 branch.
--
Catalin
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next prev parent reply other threads:[~2023-02-06 16:45 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-16 16:04 [PATCH v4 00/21] arm64/sme: Support SME 2 and SME 2.1 Mark Brown
2023-01-16 16:04 ` [PATCH v4 01/21] arm64/sme: Rename za_state to sme_state Mark Brown
2023-01-16 16:04 ` [PATCH v4 02/21] arm64: Document boot requirements for SME 2 Mark Brown
2023-01-16 16:04 ` [PATCH v4 03/21] arm64/sysreg: Update system registers for SME 2 and 2.1 Mark Brown
2023-01-16 16:04 ` [PATCH v4 04/21] arm64/sme: Document SME 2 and SME 2.1 ABI Mark Brown
2023-01-16 16:04 ` [PATCH v4 05/21] arm64/esr: Document ISS for ZT0 being disabled Mark Brown
2023-01-16 16:04 ` [PATCH v4 06/21] arm64/sme: Manually encode ZT0 load and store instructions Mark Brown
2023-01-16 16:04 ` [PATCH v4 07/21] arm64/sme: Enable host kernel to access ZT0 Mark Brown
2023-02-06 9:31 ` Marc Zyngier
2023-02-06 13:02 ` Mark Brown
2023-02-06 16:44 ` Catalin Marinas [this message]
2023-01-16 16:04 ` [PATCH v4 08/21] arm64/sme: Add basic enumeration for SME2 Mark Brown
2023-01-16 16:04 ` [PATCH v4 09/21] arm64/sme: Provide storage for ZT0 Mark Brown
2023-01-16 16:04 ` [PATCH v4 10/21] arm64/sme: Implement context switching " Mark Brown
2023-01-16 16:04 ` [PATCH v4 11/21] arm64/sme: Implement signal handling for ZT Mark Brown
2023-01-16 16:04 ` [PATCH v4 12/21] arm64/sme: Implement ZT0 ptrace support Mark Brown
2023-01-16 16:04 ` [PATCH v4 13/21] arm64/sme: Add hwcaps for SME 2 and 2.1 features Mark Brown
2023-01-16 16:04 ` [PATCH v4 14/21] kselftest/arm64: Add a stress test program for ZT0 Mark Brown
2023-01-16 16:04 ` [PATCH v4 15/21] kselftest/arm64: Cover ZT in the FP stress test Mark Brown
2023-01-16 16:04 ` [PATCH v4 16/21] kselftest/arm64: Enumerate SME2 in the signal test utility code Mark Brown
2023-01-16 16:04 ` [PATCH v4 17/21] kselftest/arm64: Teach the generic signal context validation about ZT Mark Brown
2023-01-16 16:04 ` [PATCH v4 18/21] kselftest/arm64: Add test coverage for ZT register signal frames Mark Brown
2023-01-16 16:04 ` [PATCH v4 19/21] kselftest/arm64: Add SME2 coverage to syscall-abi Mark Brown
2023-01-16 16:04 ` [PATCH v4 20/21] kselftest/arm64: Add coverage of the ZT ptrace regset Mark Brown
2023-01-16 16:04 ` [PATCH v4 21/21] kselftest/arm64: Add coverage of SME 2 and 2.1 hwcaps Mark Brown
2023-01-20 16:59 ` [PATCH v4 00/21] arm64/sme: Support SME 2 and SME 2.1 Catalin Marinas
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