From: Teresa Remmet <T.Remmet@phytec.de>
To: "linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"marex@denx.de" <marex@denx.de>
Cc: "aisheng.dong@nxp.com" <aisheng.dong@nxp.com>,
"peng.fan@nxp.com" <peng.fan@nxp.com>, "hs@denx.de" <hs@denx.de>,
"shawnguo@kernel.org" <shawnguo@kernel.org>,
"linux-imx@nxp.com" <linux-imx@nxp.com>
Subject: Re: [PATCH 2/2] arm64: dts: freescale: Add support EQOS MAC on phyBOARD-Pollux-i.MX8MP
Date: Wed, 17 Feb 2021 20:17:40 +0000 [thread overview]
Message-ID: <f06b614808941c7c91741ba1da2d9599498ba2ee.camel@phytec.de> (raw)
In-Reply-To: <20210216093825.61154-2-marex@denx.de>
Hello Marek,
Am Dienstag, den 16.02.2021, 10:38 +0100 schrieb Marek Vasut:
> The board has both MACs routed out, enable the EQOS.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Dong Aisheng <aisheng.dong@nxp.com>
> Cc: Heiko Schocher <hs@denx.de>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Teresa Remmet <t.remmet@phytec.de>
> ---
> .../dts/freescale/imx8mp-phycore-som.dtsi | 44
> +++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> index 44a8c2337cee4..526197b6972c3 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
> @@ -38,6 +38,30 @@
> cpu-supply = <&buck2>;
> };
>
> +&eqos {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_eqos>;
> + phy-mode = "rgmii-id";
> + phy-handle = <ðphy0>;
> + status = "okay";
> +
> + mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy0: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0x1>;
> + ti,rx-internal-delay =
> <DP83867_RGMIIDCTL_1_50_NS>;
> + ti,tx-internal-delay =
> <DP83867_RGMIIDCTL_1_50_NS>;
> + ti,fifo-depth =
> <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
> + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
> + enet-phy-lane-no-swap;
> + };
> + };
> +};
I would prefer having this added to imx8mp-phyboard-pollux-rdk.dts.
The phy of eqos is populated on the carrier board and not on the SoM.
Boards using the same SoM should not need to patch in the imx8mp-phycore-som.dtsi
to make it fit for their selected phy.
Thanks!
Regards,
Teresa
> +
> /* ethernet 1 */
> &fec {
> pinctrl-names = "default";
> @@ -197,6 +221,26 @@
> };
>
> &iomuxc {
> + pinctrl_eqos: eqosgrp {
> + fsl,pins = <
> + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC
> 0x3
> + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO
> 0x3
> + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0
> 0x91
> + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1
> 0x91
> + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2
> 0x91
> + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3
> 0x91
> + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENER
> ATE_RX_CLK 0x91
> + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL
> 0x91
> + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0
> 0x1f
> + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1
> 0x1f
> + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2
> 0x1f
> + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3
> 0x1f
> + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL
> 0x1f
> + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENER
> ATE_TX_CLK 0x1f
> + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20
> 0x10
> + >;
> + };
> +
> pinctrl_fec: fecgrp {
> fsl,pins = <
> MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
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next prev parent reply other threads:[~2021-02-17 20:19 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-16 9:38 [PATCH 1/2] arm64: dts: imx8mp: add eqos node and alias Marek Vasut
2021-02-16 9:38 ` [PATCH 2/2] arm64: dts: freescale: Add support EQOS MAC on phyBOARD-Pollux-i.MX8MP Marek Vasut
2021-02-17 20:17 ` Teresa Remmet [this message]
2021-02-28 21:14 ` Marek Vasut
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