From: Abhinav Kumar <quic_abhinavk@quicinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
Abhinav Kumar <abhinavk@codeaurora.org>
Cc: Stephen Boyd <sboyd@kernel.org>, <linux-arm-msm@vger.kernel.org>,
<dri-devel@lists.freedesktop.org>,
David Airlie <airlied@linux.ie>,
"Daniel Vetter" <daniel@ffwll.ch>,
<freedreno@lists.freedesktop.org>
Subject: Re: [Freedreno] [PATCH v2 3/4] drm/msm/dpu: simplify DPU_SSPP features checks
Date: Tue, 7 Dec 2021 11:45:52 -0800 [thread overview]
Message-ID: <11a9574b-cfde-c4c6-4b2b-578bcc02d4f2@quicinc.com> (raw)
In-Reply-To: <20211201225140.2481577-4-dmitry.baryshkov@linaro.org>
On 12/1/2021 2:51 PM, Dmitry Baryshkov wrote:
> Add DPU_SSPP_CSC_ANY denoting any CSC block. As we are at it, rewrite
> DPU_SSPP_SCALER (any scaler) to use BIT(x) instead of hand-coded
> bitshifts.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 16 +++++++++++-----
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 3 +--
> 2 files changed, 12 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> index ad2002d75739..3c53bd03bdeb 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
> @@ -25,11 +25,17 @@ struct dpu_hw_pipe;
> /**
> * Define all scaler feature bits in catalog
> */
> -#define DPU_SSPP_SCALER ((1UL << DPU_SSPP_SCALER_RGB) | \
> - (1UL << DPU_SSPP_SCALER_QSEED2) | \
> - (1UL << DPU_SSPP_SCALER_QSEED3) | \
> - (1UL << DPU_SSPP_SCALER_QSEED3LITE) | \
> - (1UL << DPU_SSPP_SCALER_QSEED4))
> +#define DPU_SSPP_SCALER (BIT(DPU_SSPP_SCALER_RGB) | \
> + BIT(DPU_SSPP_SCALER_QSEED2) | \
> + BIT(DPU_SSPP_SCALER_QSEED3) | \
> + BIT(DPU_SSPP_SCALER_QSEED3LITE) | \
> + BIT(DPU_SSPP_SCALER_QSEED4))
> +
> +/*
> + * Define all CSC feature bits in catalog
> + */
> +#define DPU_SSPP_CSC_ANY (BIT(DPU_SSPP_CSC) | \
> + BIT(DPU_SSPP_CSC_10BIT))
>
> /**
> * Component indices
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index c7b065b14c5c..911f5f0b41d8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -1010,8 +1010,7 @@ static int dpu_plane_atomic_check(struct drm_plane *plane,
>
> if (DPU_FORMAT_IS_YUV(fmt) &&
> (!(pdpu->pipe_hw->cap->features & DPU_SSPP_SCALER) ||
> - !(pdpu->pipe_hw->cap->features & (BIT(DPU_SSPP_CSC)
> - | BIT(DPU_SSPP_CSC_10BIT))))) {
> + !(pdpu->pipe_hw->cap->features & DPU_SSPP_CSC_ANY))) {
> DPU_DEBUG_PLANE(pdpu,
> "plane doesn't have scaler/csc for yuv\n");
> return -EINVAL;
>
next prev parent reply other threads:[~2021-12-07 19:45 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-01 22:51 [PATCH v2 0/4] drm/msm/dpu: cleanup plane state Dmitry Baryshkov
2021-12-01 22:51 ` [PATCH v2 1/4] drm/msm/dpu: drop scaler config from " Dmitry Baryshkov
2021-12-07 19:30 ` Abhinav Kumar
2021-12-01 22:51 ` [PATCH v2 2/4] drm/msm/dpu: drop pe argument from _dpu_hw_sspp_setup_scaler3 Dmitry Baryshkov
2021-12-07 19:43 ` Abhinav Kumar
2021-12-01 22:51 ` [PATCH v2 3/4] drm/msm/dpu: simplify DPU_SSPP features checks Dmitry Baryshkov
2021-12-07 19:45 ` Abhinav Kumar [this message]
2021-12-01 22:51 ` [PATCH v2 4/4] drm/msm/dpu: fix CDP setup to account for multirect index Dmitry Baryshkov
2021-12-07 20:06 ` Abhinav Kumar
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