* [PATCH 1/6] dt-bindings: soc: qcom: Add interconnect binding for GENI QUP
2019-01-21 11:21 [PATCH 0/6] Add interconnect support for GENI QUPs Alok Chauhan
@ 2019-01-21 11:21 ` Alok Chauhan
2019-01-22 6:43 ` alokc
2019-01-21 11:21 ` [PATCH 2/6] soc: qcom: Add wrapper to support for Interconnect path Alok Chauhan
` (4 subsequent siblings)
5 siblings, 1 reply; 21+ messages in thread
From: Alok Chauhan @ 2019-01-21 11:21 UTC (permalink / raw)
To: linux-arm-msm, devicetree, Andy Gross, David Brown, Rob Herring,
Mark Rutland, linux-kernel
Cc: georgi.djakov, dianders, swboyd, bjorn.andersson, Alok Chauhan
Add documentation for the interconnect and interconnect-names bindings
for the GENI QUP as detailed by bindings/interconnect/interconnect.txt.
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
---
Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
index dab7ca9..44d7e02 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
@@ -17,6 +17,12 @@ Required properties if child node exists:
- #address-cells: Must be <1> for Serial Engine Address
- #size-cells: Must be <1> for Serial Engine Address Size
- ranges: Must be present
+- interconnects: phandle to a interconnect provider. Please refer
+ ../interconnect/interconnect.txt for details.
+ Must be 2 paths corresponding to 2 AXI ports.
+- interconnect-names: Port names to differentiate between the
+ 2 interconnect paths defined with interconnect
+ specifier.
Properties for children:
@@ -67,6 +73,10 @@ Example:
#size-cells = <1>;
ranges;
+ interconnects = <&qnoc 11 &qnoc 512>,
+ <&qnoc 0 &qnoc 543>;
+ interconnect-names = "qup-memory", "qup-config";
+
i2c0: i2c@a94000 {
compatible = "qcom,geni-i2c";
reg = <0xa94000 0x4000>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 1/6] dt-bindings: soc: qcom: Add interconnect binding for GENI QUP
2019-01-21 11:21 ` [PATCH 1/6] dt-bindings: soc: qcom: Add interconnect binding for GENI QUP Alok Chauhan
@ 2019-01-22 6:43 ` alokc
0 siblings, 0 replies; 21+ messages in thread
From: alokc @ 2019-01-22 6:43 UTC (permalink / raw)
To: linux-arm-msm, devicetree, Andy Gross, David Brown, Rob Herring,
Mark Rutland, linux-kernel
Cc: georgi.djakov, dianders, swboyd, bjorn.andersson
Please don't review this patch. I've resend patches after adding all the
mailing list.
Sorry for inconvenience.
On 2019-01-21 16:51, Alok Chauhan wrote:
> Add documentation for the interconnect and interconnect-names bindings
> for the GENI QUP as detailed by bindings/interconnect/interconnect.txt.
>
> Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
> ---
> Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt | 10
> ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git
> a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
> b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
> index dab7ca9..44d7e02 100644
> --- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
> @@ -17,6 +17,12 @@ Required properties if child node exists:
> - #address-cells: Must be <1> for Serial Engine Address
> - #size-cells: Must be <1> for Serial Engine Address Size
> - ranges: Must be present
> +- interconnects: phandle to a interconnect provider. Please refer
> + ../interconnect/interconnect.txt for details.
> + Must be 2 paths corresponding to 2 AXI ports.
> +- interconnect-names: Port names to differentiate between the
> + 2 interconnect paths defined with interconnect
> + specifier.
>
> Properties for children:
>
> @@ -67,6 +73,10 @@ Example:
> #size-cells = <1>;
> ranges;
>
> + interconnects = <&qnoc 11 &qnoc 512>,
> + <&qnoc 0 &qnoc 543>;
> + interconnect-names = "qup-memory", "qup-config";
> +
> i2c0: i2c@a94000 {
> compatible = "qcom,geni-i2c";
> reg = <0xa94000 0x4000>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum,a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 2/6] soc: qcom: Add wrapper to support for Interconnect path
2019-01-21 11:21 [PATCH 0/6] Add interconnect support for GENI QUPs Alok Chauhan
2019-01-21 11:21 ` [PATCH 1/6] dt-bindings: soc: qcom: Add interconnect binding for GENI QUP Alok Chauhan
@ 2019-01-21 11:21 ` Alok Chauhan
2019-01-21 11:21 ` [PATCH 3/6] i2c: i2c-qcom-geni: Add interconnect support Alok Chauhan
` (3 subsequent siblings)
5 siblings, 0 replies; 21+ messages in thread
From: Alok Chauhan @ 2019-01-21 11:21 UTC (permalink / raw)
To: linux-arm-msm, devicetree, Andy Gross, David Brown, Stephen Boyd,
Bjorn Andersson, Douglas Anderson, Sagar Dharia,
Karthikeyan Ramasubramanian, Alok Chauhan, linux-kernel
Cc: georgi.djakov
Add the wrapper to support for interconnect path voting
from GENI QUP. This wrapper provides the functionalities
to individual Serial Engine device to get the interconnect
path and to vote for bandwidth based on their need.
This wrapper maintains bandwidth votes from each Serial Engine
and send the aggregated vote from GENI QUP to interconnect
framework.
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
---
drivers/soc/qcom/qcom-geni-se.c | 129 ++++++++++++++++++++++++++++++++++++++++
include/linux/qcom-geni-se.h | 11 ++++
2 files changed, 140 insertions(+)
diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c
index 6b8ef01..1d8dcb1 100644
--- a/drivers/soc/qcom/qcom-geni-se.c
+++ b/drivers/soc/qcom/qcom-geni-se.c
@@ -11,6 +11,7 @@
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/qcom-geni-se.h>
+#include <linux/interconnect.h>
/**
* DOC: Overview
@@ -84,11 +85,21 @@
* @dev: Device pointer of the QUP wrapper core
* @base: Base address of this instance of QUP wrapper core
* @ahb_clks: Handle to the primary & secondary AHB clocks
+ * @icc_path: Array of interconnect path handles
+ * @geni_wrapper_lock: Lock to protect the bus bandwidth request
+ * @cur_avg_bw: Current Bus Average BW request value from GENI QUP
+ * @cur_peak_bw: Current Bus Peak BW request value from GENI QUP
+ * @peak_bw_list_head: Sorted resource list based on peak bus BW
*/
struct geni_wrapper {
struct device *dev;
void __iomem *base;
struct clk_bulk_data ahb_clks[NUM_AHB_CLKS];
+ struct icc_path *icc_path[2];
+ struct mutex geni_wrapper_lock;
+ u32 cur_avg_bw;
+ u32 cur_peak_bw;
+ struct list_head peak_bw_list_head;
};
#define QUP_HW_VER_REG 0x4
@@ -440,6 +451,71 @@ static void geni_se_clks_off(struct geni_se *se)
}
/**
+ * geni_icc_update_bw() - Request to update bw vote on an interconnect path
+ * @se: Pointer to the concerned serial engine.
+ * @update: Flag to update bw vote.
+ *
+ * This function is used to request set bw vote on interconnect path handle.
+ */
+void geni_icc_update_bw(struct geni_se *se, bool update)
+{
+ struct geni_se *temp = NULL;
+ struct list_head *ins_list_head;
+ struct geni_wrapper *wrapper;
+
+ mutex_lock(&se->wrapper->geni_wrapper_lock);
+
+ wrapper = se->wrapper;
+
+ if (update) {
+ wrapper->cur_avg_bw += se->avg_bw;
+ ins_list_head = &wrapper->peak_bw_list_head;
+ list_for_each_entry(temp, &wrapper->peak_bw_list_head,
+ peak_bw_list) {
+ if (temp->peak_bw < se->peak_bw)
+ break;
+ ins_list_head = &temp->peak_bw_list;
+ }
+
+ list_add(&se->peak_bw_list, ins_list_head);
+
+ if (ins_list_head == &wrapper->peak_bw_list_head)
+ wrapper->cur_peak_bw = se->peak_bw;
+ } else {
+ if (unlikely(list_empty(&se->peak_bw_list))) {
+ mutex_unlock(&wrapper->geni_wrapper_lock);
+ return;
+ }
+
+ wrapper->cur_avg_bw -= se->avg_bw;
+
+ list_del_init(&se->peak_bw_list);
+ temp = list_first_entry_or_null(&wrapper->peak_bw_list_head,
+ struct geni_se, peak_bw_list);
+ if (temp && temp->peak_bw != wrapper->cur_peak_bw)
+ wrapper->cur_peak_bw = temp->peak_bw;
+ else if (!temp && wrapper->cur_peak_bw)
+ wrapper->cur_peak_bw = 0;
+ }
+
+ /*
+ * This bw vote is to enable internal QUP core clock as well as to
+ * enable path towards memory.
+ */
+ icc_set_bw(wrapper->icc_path[0], wrapper->cur_avg_bw,
+ wrapper->cur_peak_bw);
+
+ /*
+ * This is just register configuration path so doesn't need avg bw.
+ * Set only peak bw to enable this path.
+ */
+ icc_set_bw(wrapper->icc_path[1], 0, wrapper->cur_peak_bw);
+
+ mutex_unlock(&wrapper->geni_wrapper_lock);
+}
+EXPORT_SYMBOL(geni_icc_update_bw);
+
+/**
* geni_se_resources_off() - Turn off resources associated with the serial
* engine
* @se: Pointer to the concerned serial engine.
@@ -707,6 +783,47 @@ void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)
}
EXPORT_SYMBOL(geni_se_rx_dma_unprep);
+/**
+ * geni_interconnect_init() - Request to get interconnect path handle
+ * @se: Pointer to the concerned serial engine.
+ *
+ * This function is used to get interconnect path handle.
+ */
+int geni_interconnect_init(struct geni_se *se)
+{
+ struct geni_wrapper *wrapper_rsc;
+
+ if (unlikely(!se || !se->wrapper))
+ return -EINVAL;
+
+ wrapper_rsc = se->wrapper;
+
+ if ((IS_ERR_OR_NULL(wrapper_rsc->icc_path[0]) ||
+ IS_ERR_OR_NULL(wrapper_rsc->icc_path[1]))) {
+
+ wrapper_rsc->icc_path[0] = of_icc_get(wrapper_rsc->dev,
+ "qup-memory");
+ if (IS_ERR(wrapper_rsc->icc_path[0]))
+ return PTR_ERR(wrapper_rsc->icc_path[0]);
+
+ wrapper_rsc->icc_path[1] = of_icc_get(wrapper_rsc->dev,
+ "qup-config");
+ if (IS_ERR(wrapper_rsc->icc_path[1])) {
+ icc_put(wrapper_rsc->icc_path[0]);
+ wrapper_rsc->icc_path[0] = NULL;
+ return PTR_ERR(wrapper_rsc->icc_path[1]);
+ }
+
+ INIT_LIST_HEAD(&wrapper_rsc->peak_bw_list_head);
+ mutex_init(&wrapper_rsc->geni_wrapper_lock);
+ }
+
+ INIT_LIST_HEAD(&se->peak_bw_list);
+
+ return 0;
+}
+EXPORT_SYMBOL(geni_interconnect_init);
+
static int geni_se_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -737,6 +854,17 @@ static int geni_se_probe(struct platform_device *pdev)
return devm_of_platform_populate(dev);
}
+static int geni_se_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct geni_wrapper *wrapper = dev_get_drvdata(dev);
+
+ icc_put(wrapper->icc_path[0]);
+ icc_put(wrapper->icc_path[1]);
+
+ return 0;
+}
+
static const struct of_device_id geni_se_dt_match[] = {
{ .compatible = "qcom,geni-se-qup", },
{}
@@ -749,6 +877,7 @@ static int geni_se_probe(struct platform_device *pdev)
.of_match_table = geni_se_dt_match,
},
.probe = geni_se_probe,
+ .remove = geni_se_remove,
};
module_platform_driver(geni_se_driver);
diff --git a/include/linux/qcom-geni-se.h b/include/linux/qcom-geni-se.h
index 3bcd67f..9bf03e9 100644
--- a/include/linux/qcom-geni-se.h
+++ b/include/linux/qcom-geni-se.h
@@ -33,6 +33,10 @@ enum geni_se_protocol_type {
* @clk: Handle to the core serial engine clock
* @num_clk_levels: Number of valid clock levels in clk_perf_tbl
* @clk_perf_tbl: Table of clock frequency input to serial engine clock
+ * @avg_bw: Average bus bandwidth value for Serial Engine device
+ * @peak_bw: Peak bus bandwidth value for Serial Engine device
+ * @peak_bw_list: List Head of peak bus banwidth list for Serial Engine
+ * device
*/
struct geni_se {
void __iomem *base;
@@ -41,6 +45,9 @@ struct geni_se {
struct clk *clk;
unsigned int num_clk_levels;
unsigned long *clk_perf_tbl;
+ u32 avg_bw;
+ u32 peak_bw;
+ struct list_head peak_bw_list;
};
/* Common SE registers */
@@ -416,5 +423,9 @@ int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,
void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
+
+int geni_interconnect_init(struct geni_se *se);
+
+void geni_icc_update_bw(struct geni_se *se, bool update);
#endif
#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 3/6] i2c: i2c-qcom-geni: Add interconnect support
2019-01-21 11:21 [PATCH 0/6] Add interconnect support for GENI QUPs Alok Chauhan
2019-01-21 11:21 ` [PATCH 1/6] dt-bindings: soc: qcom: Add interconnect binding for GENI QUP Alok Chauhan
2019-01-21 11:21 ` [PATCH 2/6] soc: qcom: Add wrapper to support for Interconnect path Alok Chauhan
@ 2019-01-21 11:21 ` Alok Chauhan
2019-01-22 6:54 ` alokc
2019-01-21 11:21 ` [PATCH 4/6] spi: spi-geni-qcom: " Alok Chauhan
` (2 subsequent siblings)
5 siblings, 1 reply; 21+ messages in thread
From: Alok Chauhan @ 2019-01-21 11:21 UTC (permalink / raw)
To: linux-arm-msm, devicetree, Alok Chauhan,
Karthikeyan Ramasubramanian, linux-i2c, linux-kernel
Cc: andy.gross, david.brown, georgi.djakov, dianders, swboyd,
bjorn.andersson
Get the interconnect paths for I2C based Serial Engine device
and vote accordingly based on maximum supported I2C frequency.
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
---
drivers/i2c/busses/i2c-qcom-geni.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
index db075bc..e8fe63a 100644
--- a/drivers/i2c/busses/i2c-qcom-geni.c
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -14,6 +14,7 @@
#include <linux/pm_runtime.h>
#include <linux/qcom-geni-se.h>
#include <linux/spinlock.h>
+#include <linux/interconnect.h>
#define SE_I2C_TX_TRANS_LEN 0x26c
#define SE_I2C_RX_TRANS_LEN 0x270
@@ -508,6 +509,15 @@ static int geni_i2c_probe(struct platform_device *pdev)
return ret;
}
+ /* Set the bus quota to a reasonable value */
+ gi2c->se.avg_bw = Bps_to_icc(1000);
+ gi2c->se.peak_bw = Bps_to_icc(76800000);
+ ret = geni_interconnect_init(&gi2c->se);
+ if (ret) {
+ dev_err(&pdev->dev, "interconnect_init failed %d\n", ret);
+ return ret;
+ }
+
ret = device_property_read_u32(&pdev->dev, "clock-frequency",
&gi2c->clk_freq_out);
if (ret) {
@@ -611,6 +621,8 @@ static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev)
gi2c->suspended = 1;
}
+ geni_icc_update_bw(&gi2c->se, false);
+
return 0;
}
@@ -619,6 +631,7 @@ static int __maybe_unused geni_i2c_runtime_resume(struct device *dev)
int ret;
struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
+ geni_icc_update_bw(&gi2c->se, true);
ret = geni_se_resources_on(&gi2c->se);
if (ret)
return ret;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 3/6] i2c: i2c-qcom-geni: Add interconnect support
2019-01-21 11:21 ` [PATCH 3/6] i2c: i2c-qcom-geni: Add interconnect support Alok Chauhan
@ 2019-01-22 6:54 ` alokc
0 siblings, 0 replies; 21+ messages in thread
From: alokc @ 2019-01-22 6:54 UTC (permalink / raw)
To: linux-arm-msm, devicetree, Alok Chauhan,
Karthikeyan Ramasubramanian, linux-i2c, linux-kernel
Cc: andy.gross, david.brown, georgi.djakov, dianders, swboyd,
bjorn.andersson
Please don't review this patch. I've resend patches after adding all the
mailing list.
Sorry for inconvenience. Please review patches with spi/i2c/uart/kernel
mailing list added.
On 2019-01-21 16:51, Alok Chauhan wrote:
> Get the interconnect paths for I2C based Serial Engine device
> and vote accordingly based on maximum supported I2C frequency.
>
> Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
> ---
> drivers/i2c/busses/i2c-qcom-geni.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/i2c/busses/i2c-qcom-geni.c
> b/drivers/i2c/busses/i2c-qcom-geni.c
> index db075bc..e8fe63a 100644
> --- a/drivers/i2c/busses/i2c-qcom-geni.c
> +++ b/drivers/i2c/busses/i2c-qcom-geni.c
> @@ -14,6 +14,7 @@
> #include <linux/pm_runtime.h>
> #include <linux/qcom-geni-se.h>
> #include <linux/spinlock.h>
> +#include <linux/interconnect.h>
>
> #define SE_I2C_TX_TRANS_LEN 0x26c
> #define SE_I2C_RX_TRANS_LEN 0x270
> @@ -508,6 +509,15 @@ static int geni_i2c_probe(struct platform_device
> *pdev)
> return ret;
> }
>
> + /* Set the bus quota to a reasonable value */
> + gi2c->se.avg_bw = Bps_to_icc(1000);
> + gi2c->se.peak_bw = Bps_to_icc(76800000);
> + ret = geni_interconnect_init(&gi2c->se);
> + if (ret) {
> + dev_err(&pdev->dev, "interconnect_init failed %d\n", ret);
> + return ret;
> + }
> +
> ret = device_property_read_u32(&pdev->dev, "clock-frequency",
> &gi2c->clk_freq_out);
> if (ret) {
> @@ -611,6 +621,8 @@ static int __maybe_unused
> geni_i2c_runtime_suspend(struct device *dev)
> gi2c->suspended = 1;
> }
>
> + geni_icc_update_bw(&gi2c->se, false);
> +
> return 0;
> }
>
> @@ -619,6 +631,7 @@ static int __maybe_unused
> geni_i2c_runtime_resume(struct device *dev)
> int ret;
> struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
>
> + geni_icc_update_bw(&gi2c->se, true);
> ret = geni_se_resources_on(&gi2c->se);
> if (ret)
> return ret;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum,a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 4/6] spi: spi-geni-qcom: Add interconnect support
2019-01-21 11:21 [PATCH 0/6] Add interconnect support for GENI QUPs Alok Chauhan
` (2 preceding siblings ...)
2019-01-21 11:21 ` [PATCH 3/6] i2c: i2c-qcom-geni: Add interconnect support Alok Chauhan
@ 2019-01-21 11:21 ` Alok Chauhan
2019-01-21 12:43 ` Mark Brown
2019-01-21 11:21 ` [PATCH 5/6] tty: serial: qcom_geni_serial: " Alok Chauhan
2019-01-21 11:21 ` [PATCH 6/6] arm64: dts: sdm845: Add interconnect for GENI QUP Alok Chauhan
5 siblings, 1 reply; 21+ messages in thread
From: Alok Chauhan @ 2019-01-21 11:21 UTC (permalink / raw)
To: linux-arm-msm, devicetree, Mark Brown, linux-spi, linux-kernel
Cc: andy.gross, david.brown, georgi.djakov, dianders, swboyd,
bjorn.andersson, Alok Chauhan
Get the interconnect paths for SPI based Serial Engine device
and vote accordingly based on maximum supported SPI frequency.
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
---
drivers/spi/spi-geni-qcom.c | 20 +++++++++++++++++++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
index fdb7cb88..7bbbe9d 100644
--- a/drivers/spi/spi-geni-qcom.c
+++ b/drivers/spi/spi-geni-qcom.c
@@ -12,6 +12,7 @@
#include <linux/qcom-geni-se.h>
#include <linux/spi/spi.h>
#include <linux/spinlock.h>
+#include <linux/interconnect.h>
/* SPI SE specific registers and respective register fields */
#define SE_SPI_CPHA 0x224
@@ -589,6 +590,15 @@ static int spi_geni_probe(struct platform_device *pdev)
spin_lock_init(&mas->lock);
pm_runtime_enable(&pdev->dev);
+ /* Set the bus quota to a reasonable value */
+ mas->se.avg_bw = Bps_to_icc(2500);
+ mas->se.peak_bw = Bps_to_icc(200000000);
+ ret = geni_interconnect_init(&mas->se);
+ if (ret) {
+ dev_err(&pdev->dev, "interconnect_init failed %d\n", ret);
+ return ret;
+ }
+
ret = spi_geni_init(mas);
if (ret)
goto spi_geni_probe_runtime_disable;
@@ -628,8 +638,15 @@ static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
{
struct spi_master *spi = dev_get_drvdata(dev);
struct spi_geni_master *mas = spi_master_get_devdata(spi);
+ int ret;
- return geni_se_resources_off(&mas->se);
+ ret = geni_se_resources_off(&mas->se);
+ if (ret)
+ return ret;
+
+ geni_icc_update_bw(&mas->se, false);
+
+ return 0;
}
static int __maybe_unused spi_geni_runtime_resume(struct device *dev)
@@ -637,6 +654,7 @@ static int __maybe_unused spi_geni_runtime_resume(struct device *dev)
struct spi_master *spi = dev_get_drvdata(dev);
struct spi_geni_master *mas = spi_master_get_devdata(spi);
+ geni_icc_update_bw(&mas->se, true);
return geni_se_resources_on(&mas->se);
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 4/6] spi: spi-geni-qcom: Add interconnect support
2019-01-21 11:21 ` [PATCH 4/6] spi: spi-geni-qcom: " Alok Chauhan
@ 2019-01-21 12:43 ` Mark Brown
2019-01-22 6:21 ` alokc
0 siblings, 1 reply; 21+ messages in thread
From: Mark Brown @ 2019-01-21 12:43 UTC (permalink / raw)
To: Alok Chauhan
Cc: linux-arm-msm, devicetree, linux-spi, linux-kernel, andy.gross,
david.brown, georgi.djakov, dianders, swboyd, bjorn.andersson
[-- Attachment #1: Type: text/plain, Size: 305 bytes --]
On Mon, Jan 21, 2019 at 04:51:41PM +0530, Alok Chauhan wrote:
> Get the interconnect paths for SPI based Serial Engine device
> and vote accordingly based on maximum supported SPI frequency.
I don't have any of the other patches in this series or a cover letter -
what's going on with dependencies here?
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 4/6] spi: spi-geni-qcom: Add interconnect support
2019-01-21 12:43 ` Mark Brown
@ 2019-01-22 6:21 ` alokc
0 siblings, 0 replies; 21+ messages in thread
From: alokc @ 2019-01-22 6:21 UTC (permalink / raw)
To: Mark Brown
Cc: linux-arm-msm, devicetree, linux-spi, linux-kernel, andy.gross,
david.brown, georgi.djakov, dianders, swboyd, bjorn.andersson,
linux-spi-owner
On 2019-01-21 18:13, Mark Brown wrote:
> On Mon, Jan 21, 2019 at 04:51:41PM +0530, Alok Chauhan wrote:
>> Get the interconnect paths for SPI based Serial Engine device
>> and vote accordingly based on maximum supported SPI frequency.
>
> I don't have any of the other patches in this series or a cover letter
> -
> what's going on with dependencies here?
I am extremely sorry to waste your time. Looks like I missed some
mailing list while sending patches upstream. I will resend patches
today.
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
Forum,a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH 5/6] tty: serial: qcom_geni_serial: Add interconnect support
2019-01-21 11:21 [PATCH 0/6] Add interconnect support for GENI QUPs Alok Chauhan
` (3 preceding siblings ...)
2019-01-21 11:21 ` [PATCH 4/6] spi: spi-geni-qcom: " Alok Chauhan
@ 2019-01-21 11:21 ` Alok Chauhan
2019-01-21 11:21 ` [PATCH 6/6] arm64: dts: sdm845: Add interconnect for GENI QUP Alok Chauhan
5 siblings, 0 replies; 21+ messages in thread
From: Alok Chauhan @ 2019-01-21 11:21 UTC (permalink / raw)
To: linux-arm-msm, devicetree, Greg Kroah-Hartman, Jiri Slaby,
linux-serial, linux-kernel
Cc: andy.gross, david.brown, georgi.djakov, dianders, swboyd,
bjorn.andersson, Alok Chauhan
Get the interconnect paths for Uart based Serial Engine device
and vote accordingly based on maximum supported Uart frequency.
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
---
drivers/tty/serial/qcom_geni_serial.c | 27 ++++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c
index a72d6d9..e2ea499 100644
--- a/drivers/tty/serial/qcom_geni_serial.c
+++ b/drivers/tty/serial/qcom_geni_serial.c
@@ -19,6 +19,7 @@
#include <linux/slab.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
+#include <linux/interconnect.h>
/* UART specific GENI registers */
#define SE_UART_LOOPBACK_CFG 0x22c
@@ -1348,6 +1349,22 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
return ret;
}
+ /* Set the bus quota to a reasonable value */
+ port->se.avg_bw = console ? Bps_to_icc(1000) : Bps_to_icc(2500);
+ port->se.peak_bw = Bps_to_icc(76800000);
+ ret = geni_interconnect_init(&port->se);
+ if (ret) {
+ dev_err(&pdev->dev, "interconnect_init failed %d\n", ret);
+ return ret;
+ }
+
+ /*
+ * Vote for interconnect path early. This has to move as part of
+ * Runtime PM APIs when implemented for better control betwen
+ * console and non-console usecases
+ */
+ geni_icc_update_bw(&port->se, true);
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -EINVAL;
@@ -1385,8 +1402,15 @@ static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev)
{
struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
struct uart_port *uport = &port->uport;
+ int ret;
+
+ ret = uart_suspend_port(uport->private_data, uport);
+ if (ret)
+ return ret;
+
+ geni_icc_update_bw(&port->se, false);
- return uart_suspend_port(uport->private_data, uport);
+ return 0;
}
static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
@@ -1394,6 +1418,7 @@ static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
struct uart_port *uport = &port->uport;
+ geni_icc_update_bw(&port->se, true);
return uart_resume_port(uport->private_data, uport);
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 6/6] arm64: dts: sdm845: Add interconnect for GENI QUP
2019-01-21 11:21 [PATCH 0/6] Add interconnect support for GENI QUPs Alok Chauhan
` (4 preceding siblings ...)
2019-01-21 11:21 ` [PATCH 5/6] tty: serial: qcom_geni_serial: " Alok Chauhan
@ 2019-01-21 11:21 ` Alok Chauhan
5 siblings, 0 replies; 21+ messages in thread
From: Alok Chauhan @ 2019-01-21 11:21 UTC (permalink / raw)
To: linux-arm-msm, devicetree, Andy Gross, David Brown, Rob Herring,
Mark Rutland, linux-kernel
Cc: georgi.djakov, dianders, swboyd, bjorn.andersson, Alok Chauhan
Add interconnect ports for GENI QUPs to set bus
capabilities.
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index c27cbd3..fb0a8a7 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -374,6 +374,13 @@
#address-cells = <1>;
#size-cells = <1>;
ranges;
+
+ interconnects = <&rsc_hlos MASTER_BLSP_1
+ &rsc_hlos SLAVE_EBI1>,
+ <&rsc_hlos MASTER_APPSS_PROC
+ &rsc_hlos SLAVE_BLSP_1>;
+ interconnect-names = "qup-memory", "qup-config";
+
status = "disabled";
i2c0: i2c@880000 {
@@ -682,6 +689,13 @@
#address-cells = <1>;
#size-cells = <1>;
ranges;
+
+ interconnects = <&rsc_hlos MASTER_BLSP_2
+ &rsc_hlos SLAVE_EBI1>,
+ <&rsc_hlos MASTER_APPSS_PROC
+ &rsc_hlos SLAVE_BLSP_2>;
+ interconnect-names = "qup-memory", "qup-config";
+
status = "disabled";
i2c8: i2c@a80000 {
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH 4/6] spi: spi-geni-qcom: Add interconnect support
2020-02-17 13:29 [PATCH 0/6] Add interconnect support to UART, I2C, SPI and QSPI Akash Asthana
@ 2020-02-17 13:30 ` Akash Asthana
2020-02-17 16:31 ` Mark Brown
2020-02-19 18:09 ` Matthias Kaehlcke
0 siblings, 2 replies; 21+ messages in thread
From: Akash Asthana @ 2020-02-17 13:30 UTC (permalink / raw)
To: gregkh, agross, bjorn.andersson, wsa, broonie, mark.rutland, robh+dt
Cc: linux-i2c, linux-spi, devicetree, swboyd, mgautam, linux-arm-msm,
linux-serial, mka, dianders, Akash Asthana
Get the interconnect paths for SPI based Serial Engine device
and vote according to the current bus speed of the driver.
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
---
drivers/spi/spi-geni-qcom.c | 65 ++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 62 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
index c397242..a066ef26 100644
--- a/drivers/spi/spi-geni-qcom.c
+++ b/drivers/spi/spi-geni-qcom.c
@@ -118,6 +118,35 @@ static int get_spi_clk_cfg(unsigned int speed_hz,
return ret;
}
+static int geni_spi_icc_get(struct geni_se *se)
+{
+ if (!se)
+ return -EINVAL;
+
+ se->icc_path[GENI_TO_CORE] = of_icc_get(se->dev, "qup-core");
+ if (IS_ERR(se->icc_path[GENI_TO_CORE]))
+ return PTR_ERR(se->icc_path[GENI_TO_CORE]);
+
+ se->icc_path[CPU_TO_GENI] = of_icc_get(se->dev, "qup-config");
+ if (IS_ERR(se->icc_path[CPU_TO_GENI])) {
+ icc_put(se->icc_path[GENI_TO_CORE]);
+ se->icc_path[GENI_TO_CORE] = NULL;
+ return PTR_ERR(se->icc_path[CPU_TO_GENI]);
+ }
+
+ return 0;
+}
+
+void geni_spi_icc_put(struct geni_se *se)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(se->icc_path); i++) {
+ icc_put(se->icc_path[i]);
+ se->icc_path[i] = NULL;
+ }
+}
+
static void handle_fifo_timeout(struct spi_master *spi,
struct spi_message *msg)
{
@@ -234,6 +263,11 @@ static int setup_fifo_params(struct spi_device *spi_slv,
return ret;
}
+ /* Set BW quota for CPU as driver supports FIFO mode only */
+ se->avg_bw_cpu = Bps_to_icc(mas->cur_speed_hz);
+ se->peak_bw_cpu = Bps_to_icc(2 * mas->cur_speed_hz);
+ icc_set_bw(se->icc_path[CPU_TO_GENI], se->avg_bw_cpu, se->peak_bw_cpu);
+
clk_sel = idx & CLK_SEL_MSK;
m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN;
spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word);
@@ -578,13 +612,22 @@ static int spi_geni_probe(struct platform_device *pdev)
spin_lock_init(&mas->lock);
pm_runtime_enable(dev);
- ret = spi_geni_init(mas);
+ ret = geni_spi_icc_get(&mas->se);
if (ret)
goto spi_geni_probe_runtime_disable;
+ /* Set the bus quota to a reasonable value */
+ mas->se.avg_bw_core = Bps_to_icc(CORE_2X_50_MHZ);
+ mas->se.peak_bw_core = Bps_to_icc(CORE_2X_100_MHZ);
+ mas->se.avg_bw_cpu = Bps_to_icc(1000);
+ mas->se.peak_bw_cpu = Bps_to_icc(1000);
+
+ ret = spi_geni_init(mas);
+ if (ret)
+ goto spi_geni_icc_put;
ret = request_irq(mas->irq, geni_spi_isr, 0, dev_name(dev), spi);
if (ret)
- goto spi_geni_probe_runtime_disable;
+ goto spi_geni_icc_put;
ret = spi_register_master(spi);
if (ret)
@@ -593,6 +636,8 @@ static int spi_geni_probe(struct platform_device *pdev)
return 0;
spi_geni_probe_free_irq:
free_irq(mas->irq, spi);
+spi_geni_icc_put:
+ geni_spi_icc_put(&mas->se);
spi_geni_probe_runtime_disable:
pm_runtime_disable(dev);
spi_master_put(spi);
@@ -608,16 +653,25 @@ static int spi_geni_remove(struct platform_device *pdev)
spi_unregister_master(spi);
free_irq(mas->irq, spi);
+ geni_spi_icc_put(&mas->se);
pm_runtime_disable(&pdev->dev);
return 0;
}
static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
{
+ int ret;
struct spi_master *spi = dev_get_drvdata(dev);
struct spi_geni_master *mas = spi_master_get_devdata(spi);
- return geni_se_resources_off(&mas->se);
+ ret = geni_se_resources_off(&mas->se);
+ if (ret)
+ return ret;
+
+ icc_set_bw(mas->se.icc_path[GENI_TO_CORE], 0, 0);
+ icc_set_bw(mas->se.icc_path[CPU_TO_GENI], 0, 0);
+
+ return 0;
}
static int __maybe_unused spi_geni_runtime_resume(struct device *dev)
@@ -625,6 +679,11 @@ static int __maybe_unused spi_geni_runtime_resume(struct device *dev)
struct spi_master *spi = dev_get_drvdata(dev);
struct spi_geni_master *mas = spi_master_get_devdata(spi);
+ icc_set_bw(mas->se.icc_path[GENI_TO_CORE], mas->se.avg_bw_core,
+ mas->se.peak_bw_core);
+ icc_set_bw(mas->se.icc_path[CPU_TO_GENI], mas->se.avg_bw_cpu,
+ mas->se.peak_bw_cpu);
+
return geni_se_resources_on(&mas->se);
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 21+ messages in thread
* Re: [PATCH 4/6] spi: spi-geni-qcom: Add interconnect support
2020-02-17 13:30 ` [PATCH 4/6] spi: spi-geni-qcom: Add interconnect support Akash Asthana
@ 2020-02-17 16:31 ` Mark Brown
2020-02-19 18:09 ` Matthias Kaehlcke
1 sibling, 0 replies; 21+ messages in thread
From: Mark Brown @ 2020-02-17 16:31 UTC (permalink / raw)
To: Akash Asthana
Cc: gregkh, agross, bjorn.andersson, wsa, mark.rutland, robh+dt,
linux-i2c, linux-spi, devicetree, swboyd, mgautam, linux-arm-msm,
linux-serial, mka, dianders
[-- Attachment #1: Type: text/plain, Size: 231 bytes --]
On Mon, Feb 17, 2020 at 07:00:03PM +0530, Akash Asthana wrote:
> Get the interconnect paths for SPI based Serial Engine device
> and vote according to the current bus speed of the driver.
Acked-by: Mark Brown <broonie@kernel.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 4/6] spi: spi-geni-qcom: Add interconnect support
2020-02-17 13:30 ` [PATCH 4/6] spi: spi-geni-qcom: Add interconnect support Akash Asthana
2020-02-17 16:31 ` Mark Brown
@ 2020-02-19 18:09 ` Matthias Kaehlcke
2020-02-21 18:55 ` Matthias Kaehlcke
1 sibling, 1 reply; 21+ messages in thread
From: Matthias Kaehlcke @ 2020-02-19 18:09 UTC (permalink / raw)
To: Akash Asthana
Cc: gregkh, agross, bjorn.andersson, wsa, broonie, mark.rutland,
robh+dt, linux-i2c, linux-spi, devicetree, swboyd, mgautam,
linux-arm-msm, linux-serial, dianders
On Mon, Feb 17, 2020 at 07:00:03PM +0530, Akash Asthana wrote:
> Get the interconnect paths for SPI based Serial Engine device
> and vote according to the current bus speed of the driver.
>
> Signed-off-by: Akash Asthana <akashast@codeaurora.org>
> ---
> drivers/spi/spi-geni-qcom.c | 65 ++++++++++++++++++++++++++++++++++++++++++---
> 1 file changed, 62 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
> index c397242..a066ef26 100644
> --- a/drivers/spi/spi-geni-qcom.c
> +++ b/drivers/spi/spi-geni-qcom.c
> @@ -608,16 +653,25 @@ static int spi_geni_remove(struct platform_device *pdev)
> spi_unregister_master(spi);
>
> free_irq(mas->irq, spi);
> + geni_spi_icc_put(&mas->se);
> pm_runtime_disable(&pdev->dev);
> return 0;
> }
>
> static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
> {
> + int ret;
> struct spi_master *spi = dev_get_drvdata(dev);
> struct spi_geni_master *mas = spi_master_get_devdata(spi);
>
> - return geni_se_resources_off(&mas->se);
> + ret = geni_se_resources_off(&mas->se);
> + if (ret)
> + return ret;
> +
> + icc_set_bw(mas->se.icc_path[GENI_TO_CORE], 0, 0);
This causes my SC7180 system to reset at boot time:
[ 3.509652] qcom-qmp-phy 88e9000.phy-wrapper: Registered Qcom-QMP phy
[ 3.516956] qcom-qusb2-phy 88e3000.phy: Registered Qcom-QUSB2 phy
[ 3.524450] geni_se_qup 8c0000.geniqup: Adding to iommu group 4
[ 3.533896] spi_master spi0: will run message pump with realtime priority
<reset>
The system does not reset when passing 'Bps_to_icc(1000)' (=> 1) instead of 0.
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH 4/6] spi: spi-geni-qcom: Add interconnect support
2020-02-19 18:09 ` Matthias Kaehlcke
@ 2020-02-21 18:55 ` Matthias Kaehlcke
0 siblings, 0 replies; 21+ messages in thread
From: Matthias Kaehlcke @ 2020-02-21 18:55 UTC (permalink / raw)
To: Akash Asthana
Cc: gregkh, agross, bjorn.andersson, wsa, broonie, mark.rutland,
robh+dt, linux-i2c, linux-spi, devicetree, swboyd, mgautam,
linux-arm-msm, linux-serial, dianders
On Wed, Feb 19, 2020 at 10:09:50AM -0800, Matthias Kaehlcke wrote:
> On Mon, Feb 17, 2020 at 07:00:03PM +0530, Akash Asthana wrote:
> > Get the interconnect paths for SPI based Serial Engine device
> > and vote according to the current bus speed of the driver.
> >
> > Signed-off-by: Akash Asthana <akashast@codeaurora.org>
> > ---
> > drivers/spi/spi-geni-qcom.c | 65 ++++++++++++++++++++++++++++++++++++++++++---
> > 1 file changed, 62 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
> > index c397242..a066ef26 100644
> > --- a/drivers/spi/spi-geni-qcom.c
> > +++ b/drivers/spi/spi-geni-qcom.c
> > @@ -608,16 +653,25 @@ static int spi_geni_remove(struct platform_device *pdev)
> > spi_unregister_master(spi);
> >
> > free_irq(mas->irq, spi);
> > + geni_spi_icc_put(&mas->se);
> > pm_runtime_disable(&pdev->dev);
> > return 0;
> > }
> >
> > static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
> > {
> > + int ret;
> > struct spi_master *spi = dev_get_drvdata(dev);
> > struct spi_geni_master *mas = spi_master_get_devdata(spi);
> >
> > - return geni_se_resources_off(&mas->se);
> > + ret = geni_se_resources_off(&mas->se);
> > + if (ret)
> > + return ret;
> > +
> > + icc_set_bw(mas->se.icc_path[GENI_TO_CORE], 0, 0);
>
> This causes my SC7180 system to reset at boot time:
>
> [ 3.509652] qcom-qmp-phy 88e9000.phy-wrapper: Registered Qcom-QMP phy
> [ 3.516956] qcom-qusb2-phy 88e3000.phy: Registered Qcom-QUSB2 phy
> [ 3.524450] geni_se_qup 8c0000.geniqup: Adding to iommu group 4
> [ 3.533896] spi_master spi0: will run message pump with realtime priority
> <reset>
>
> The system does not reset when passing 'Bps_to_icc(1000)' (=> 1) instead of 0.
I found this is related with the use of 'earlycon'.
There is a short window where the early console and the 'real' console coexist:
[ 3.858122] printk: console [ttyMSM0] enabled
[ 3.875692] printk: bootconsole [qcom_geni0] disabled
The reset probably occurs when the early console tries to write, but the ICC is
effectively disabled because ttyMSM0 and the other geni ports are runtime
suspended.
In any case that's not an issue of the SPI driver, but needs to be addressed
somewhere in the console/UART code.
^ permalink raw reply [flat|nested] 21+ messages in thread