* [PATCH 0/4] Add GCC and RPMh clock support for SDX55
@ 2020-10-28 7:42 Manivannan Sadhasivam
2020-10-28 7:42 ` [PATCH 1/4] dt-bindings: clock: Add SDX55 GCC clock bindings Manivannan Sadhasivam
` (4 more replies)
0 siblings, 5 replies; 16+ messages in thread
From: Manivannan Sadhasivam @ 2020-10-28 7:42 UTC (permalink / raw)
To: sboyd, mturquette, robh+dt
Cc: bjorn.andersson, vkoul, linux-arm-msm, linux-clk, devicetree,
linux-kernel, Manivannan Sadhasivam
Hello,
This series adds Global Clock Controller (GCC) and RPMh clock support
for SDX55 SoC from Qualcomm with relevant DT bindings.
This series has been tested on SDX55 MTP board. The dts patches for this
SoC/board will be posted later.
Thanks,
Mani
Manivannan Sadhasivam (1):
clk: qcom: Add support for SDX55 RPMh clocks
Naveen Yadav (1):
clk: qcom: Add SDX55 GCC support
Vinod Koul (2):
dt-bindings: clock: Add SDX55 GCC clock bindings
dt-bindings: clock: Introduce RPMHCC bindings for SDX55
.../bindings/clock/qcom,gcc-sdx55.yaml | 71 +
.../bindings/clock/qcom,rpmhcc.yaml | 1 +
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-rpmh.c | 20 +
drivers/clk/qcom/gcc-sdx55.c | 1667 +++++++++++++++++
include/dt-bindings/clock/qcom,gcc-sdx55.h | 112 ++
include/dt-bindings/clock/qcom,rpmh.h | 1 +
8 files changed, 1881 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml
create mode 100644 drivers/clk/qcom/gcc-sdx55.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-sdx55.h
--
2.17.1
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 1/4] dt-bindings: clock: Add SDX55 GCC clock bindings 2020-10-28 7:42 [PATCH 0/4] Add GCC and RPMh clock support for SDX55 Manivannan Sadhasivam @ 2020-10-28 7:42 ` Manivannan Sadhasivam 2020-10-30 19:22 ` Rob Herring 2020-10-28 7:42 ` [PATCH 2/4] clk: qcom: Add SDX55 GCC support Manivannan Sadhasivam ` (3 subsequent siblings) 4 siblings, 1 reply; 16+ messages in thread From: Manivannan Sadhasivam @ 2020-10-28 7:42 UTC (permalink / raw) To: sboyd, mturquette, robh+dt Cc: bjorn.andersson, vkoul, linux-arm-msm, linux-clk, devicetree, linux-kernel From: Vinod Koul <vkoul@kernel.org> Add device tree bindings for global clock controller on SDX55 SoCs. Signed-off-by: Vinod Koul <vkoul@kernel.org> --- .../bindings/clock/qcom,gcc-sdx55.yaml | 71 +++++++++++ include/dt-bindings/clock/qcom,gcc-sdx55.h | 112 ++++++++++++++++++ 2 files changed, 183 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml create mode 100644 include/dt-bindings/clock/qcom,gcc-sdx55.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml new file mode 100644 index 000000000000..c24c9d9fb7dc --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx55.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for SDX55 + +maintainers: + - Vinod Koul <vkoul@kernel.org> + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on SDX55 + + See also: + - dt-bindings/clock/qcom,gcc-sdx55.h + +properties: + compatible: + const: qcom,gcc-sdx55 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + + clock-names: + items: + - const: bi_tcxo + - const: sleep_clk + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - reg + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + clock-controller@100000 { + compatible = "qcom,gcc-sdx55"; + reg = <0x00100000 0x1f0000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + +... diff --git a/include/dt-bindings/clock/qcom,gcc-sdx55.h b/include/dt-bindings/clock/qcom,gcc-sdx55.h new file mode 100644 index 000000000000..09ca45c6de73 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-sdx55.h @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2020, Linaro Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX55_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SDX55_H + +#define GPLL0 3 +#define GPLL0_OUT_EVEN 4 +#define GPLL4 5 +#define GPLL4_OUT_EVEN 6 +#define GPLL5 7 +#define GCC_AHB_PCIE_LINK_CLK 8 +#define GCC_BLSP1_AHB_CLK 9 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 10 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 11 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 12 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 13 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 14 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 15 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 16 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 17 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 18 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 19 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 20 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 21 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 22 +#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 23 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 24 +#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 25 +#define GCC_BLSP1_UART1_APPS_CLK 26 +#define GCC_BLSP1_UART1_APPS_CLK_SRC 27 +#define GCC_BLSP1_UART2_APPS_CLK 28 +#define GCC_BLSP1_UART2_APPS_CLK_SRC 29 +#define GCC_BLSP1_UART3_APPS_CLK 30 +#define GCC_BLSP1_UART3_APPS_CLK_SRC 31 +#define GCC_BLSP1_UART4_APPS_CLK 32 +#define GCC_BLSP1_UART4_APPS_CLK_SRC 33 +#define GCC_BOOT_ROM_AHB_CLK 34 +#define GCC_CE1_AHB_CLK 35 +#define GCC_CE1_AXI_CLK 36 +#define GCC_CE1_CLK 37 +#define GCC_CPUSS_AHB_CLK 38 +#define GCC_CPUSS_AHB_CLK_SRC 39 +#define GCC_CPUSS_GNOC_CLK 40 +#define GCC_CPUSS_RBCPR_CLK 41 +#define GCC_CPUSS_RBCPR_CLK_SRC 42 +#define GCC_EMAC_CLK_SRC 43 +#define GCC_EMAC_PTP_CLK_SRC 44 +#define GCC_ETH_AXI_CLK 45 +#define GCC_ETH_PTP_CLK 46 +#define GCC_ETH_RGMII_CLK 47 +#define GCC_ETH_SLAVE_AHB_CLK 48 +#define GCC_GP1_CLK 49 +#define GCC_GP1_CLK_SRC 50 +#define GCC_GP2_CLK 51 +#define GCC_GP2_CLK_SRC 52 +#define GCC_GP3_CLK 53 +#define GCC_GP3_CLK_SRC 54 +#define GCC_PCIE_0_CLKREF_CLK 55 +#define GCC_PCIE_AUX_CLK 56 +#define GCC_PCIE_AUX_PHY_CLK_SRC 57 +#define GCC_PCIE_CFG_AHB_CLK 58 +#define GCC_PCIE_MSTR_AXI_CLK 59 +#define GCC_PCIE_PIPE_CLK 60 +#define GCC_PCIE_RCHNG_PHY_CLK 61 +#define GCC_PCIE_RCHNG_PHY_CLK_SRC 62 +#define GCC_PCIE_SLEEP_CLK 63 +#define GCC_PCIE_SLV_AXI_CLK 64 +#define GCC_PCIE_SLV_Q2A_AXI_CLK 65 +#define GCC_PDM2_CLK 66 +#define GCC_PDM2_CLK_SRC 67 +#define GCC_PDM_AHB_CLK 68 +#define GCC_PDM_XO4_CLK 69 +#define GCC_SDCC1_AHB_CLK 70 +#define GCC_SDCC1_APPS_CLK 71 +#define GCC_SDCC1_APPS_CLK_SRC 72 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 73 +#define GCC_USB30_MASTER_CLK 74 +#define GCC_USB30_MASTER_CLK_SRC 75 +#define GCC_USB30_MOCK_UTMI_CLK 76 +#define GCC_USB30_MOCK_UTMI_CLK_SRC 77 +#define GCC_USB30_MSTR_AXI_CLK 78 +#define GCC_USB30_SLEEP_CLK 79 +#define GCC_USB30_SLV_AHB_CLK 80 +#define GCC_USB3_PHY_AUX_CLK 81 +#define GCC_USB3_PHY_AUX_CLK_SRC 82 +#define GCC_USB3_PHY_PIPE_CLK 83 +#define GCC_USB3_PRIM_CLKREF_CLK 84 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 85 +#define GCC_XO_DIV4_CLK 86 +#define GCC_XO_PCIE_LINK_CLK 87 + +#define GCC_EMAC_BCR 0 +#define GCC_PCIE_BCR 1 +#define GCC_PCIE_LINK_DOWN_BCR 2 +#define GCC_PCIE_NOCSR_COM_PHY_BCR 3 +#define GCC_PCIE_PHY_BCR 4 +#define GCC_PCIE_PHY_CFG_AHB_BCR 5 +#define GCC_PCIE_PHY_COM_BCR 6 +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 7 +#define GCC_PDM_BCR 8 +#define GCC_QUSB2PHY_BCR 9 +#define GCC_TCSR_PCIE_BCR 10 +#define GCC_USB30_BCR 11 +#define GCC_USB3_PHY_BCR 12 +#define GCC_USB3PHY_PHY_BCR 13 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 14 + +#endif -- 2.17.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 1/4] dt-bindings: clock: Add SDX55 GCC clock bindings 2020-10-28 7:42 ` [PATCH 1/4] dt-bindings: clock: Add SDX55 GCC clock bindings Manivannan Sadhasivam @ 2020-10-30 19:22 ` Rob Herring 2020-10-31 3:29 ` Manivannan Sadhasivam 0 siblings, 1 reply; 16+ messages in thread From: Rob Herring @ 2020-10-30 19:22 UTC (permalink / raw) To: Manivannan Sadhasivam Cc: sboyd, mturquette, bjorn.andersson, vkoul, linux-arm-msm, linux-clk, devicetree, linux-kernel On Wed, Oct 28, 2020 at 01:12:29PM +0530, Manivannan Sadhasivam wrote: > From: Vinod Koul <vkoul@kernel.org> > > Add device tree bindings for global clock controller on SDX55 SoCs. > > Signed-off-by: Vinod Koul <vkoul@kernel.org> This should carry your S-o-b too. > --- > .../bindings/clock/qcom,gcc-sdx55.yaml | 71 +++++++++++ > include/dt-bindings/clock/qcom,gcc-sdx55.h | 112 ++++++++++++++++++ > 2 files changed, 183 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml > create mode 100644 include/dt-bindings/clock/qcom,gcc-sdx55.h > > diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml > new file mode 100644 > index 000000000000..c24c9d9fb7dc > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml > @@ -0,0 +1,71 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,gcc-sdx55.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Global Clock & Reset Controller Binding for SDX55 > + > +maintainers: > + - Vinod Koul <vkoul@kernel.org> > + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > + > +description: | > + Qualcomm global clock control module which supports the clocks, resets and > + power domains on SDX55 > + > + See also: > + - dt-bindings/clock/qcom,gcc-sdx55.h > + > +properties: > + compatible: > + const: qcom,gcc-sdx55 > + > + clocks: > + items: > + - description: Board XO source > + - description: Sleep clock source > + > + clock-names: > + items: > + - const: bi_tcxo > + - const: sleep_clk > + > + '#clock-cells': > + const: 1 > + > + '#reset-cells': > + const: 1 > + > + '#power-domain-cells': > + const: 1 > + > + reg: > + maxItems: 1 > + > +required: > + - compatible > + - clocks > + - clock-names > + - reg > + - '#clock-cells' > + - '#reset-cells' > + - '#power-domain-cells' > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,rpmh.h> > + clock-controller@100000 { > + compatible = "qcom,gcc-sdx55"; > + reg = <0x00100000 0x1f0000>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&sleep_clk>; > + clock-names = "bi_tcxo", "sleep_clk"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > +... > diff --git a/include/dt-bindings/clock/qcom,gcc-sdx55.h b/include/dt-bindings/clock/qcom,gcc-sdx55.h > new file mode 100644 > index 000000000000..09ca45c6de73 > --- /dev/null > +++ b/include/dt-bindings/clock/qcom,gcc-sdx55.h > @@ -0,0 +1,112 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ Dual license? > +/* > + * Copyright (c) 2018, The Linux Foundation. All rights reserved. > + * Copyright (c) 2020, Linaro Ltd. > + */ > + > +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX55_H > +#define _DT_BINDINGS_CLK_QCOM_GCC_SDX55_H > + > +#define GPLL0 3 > +#define GPLL0_OUT_EVEN 4 > +#define GPLL4 5 > +#define GPLL4_OUT_EVEN 6 > +#define GPLL5 7 > +#define GCC_AHB_PCIE_LINK_CLK 8 > +#define GCC_BLSP1_AHB_CLK 9 > +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 10 > +#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 11 > +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 12 > +#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 13 > +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 14 > +#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 15 > +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 16 > +#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 17 > +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 18 > +#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 19 > +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 20 > +#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 21 > +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 22 > +#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 23 > +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 24 > +#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 25 > +#define GCC_BLSP1_UART1_APPS_CLK 26 > +#define GCC_BLSP1_UART1_APPS_CLK_SRC 27 > +#define GCC_BLSP1_UART2_APPS_CLK 28 > +#define GCC_BLSP1_UART2_APPS_CLK_SRC 29 > +#define GCC_BLSP1_UART3_APPS_CLK 30 > +#define GCC_BLSP1_UART3_APPS_CLK_SRC 31 > +#define GCC_BLSP1_UART4_APPS_CLK 32 > +#define GCC_BLSP1_UART4_APPS_CLK_SRC 33 > +#define GCC_BOOT_ROM_AHB_CLK 34 > +#define GCC_CE1_AHB_CLK 35 > +#define GCC_CE1_AXI_CLK 36 > +#define GCC_CE1_CLK 37 > +#define GCC_CPUSS_AHB_CLK 38 > +#define GCC_CPUSS_AHB_CLK_SRC 39 > +#define GCC_CPUSS_GNOC_CLK 40 > +#define GCC_CPUSS_RBCPR_CLK 41 > +#define GCC_CPUSS_RBCPR_CLK_SRC 42 > +#define GCC_EMAC_CLK_SRC 43 > +#define GCC_EMAC_PTP_CLK_SRC 44 > +#define GCC_ETH_AXI_CLK 45 > +#define GCC_ETH_PTP_CLK 46 > +#define GCC_ETH_RGMII_CLK 47 > +#define GCC_ETH_SLAVE_AHB_CLK 48 > +#define GCC_GP1_CLK 49 > +#define GCC_GP1_CLK_SRC 50 > +#define GCC_GP2_CLK 51 > +#define GCC_GP2_CLK_SRC 52 > +#define GCC_GP3_CLK 53 > +#define GCC_GP3_CLK_SRC 54 > +#define GCC_PCIE_0_CLKREF_CLK 55 > +#define GCC_PCIE_AUX_CLK 56 > +#define GCC_PCIE_AUX_PHY_CLK_SRC 57 > +#define GCC_PCIE_CFG_AHB_CLK 58 > +#define GCC_PCIE_MSTR_AXI_CLK 59 > +#define GCC_PCIE_PIPE_CLK 60 > +#define GCC_PCIE_RCHNG_PHY_CLK 61 > +#define GCC_PCIE_RCHNG_PHY_CLK_SRC 62 > +#define GCC_PCIE_SLEEP_CLK 63 > +#define GCC_PCIE_SLV_AXI_CLK 64 > +#define GCC_PCIE_SLV_Q2A_AXI_CLK 65 > +#define GCC_PDM2_CLK 66 > +#define GCC_PDM2_CLK_SRC 67 > +#define GCC_PDM_AHB_CLK 68 > +#define GCC_PDM_XO4_CLK 69 > +#define GCC_SDCC1_AHB_CLK 70 > +#define GCC_SDCC1_APPS_CLK 71 > +#define GCC_SDCC1_APPS_CLK_SRC 72 > +#define GCC_SYS_NOC_CPUSS_AHB_CLK 73 > +#define GCC_USB30_MASTER_CLK 74 > +#define GCC_USB30_MASTER_CLK_SRC 75 > +#define GCC_USB30_MOCK_UTMI_CLK 76 > +#define GCC_USB30_MOCK_UTMI_CLK_SRC 77 > +#define GCC_USB30_MSTR_AXI_CLK 78 > +#define GCC_USB30_SLEEP_CLK 79 > +#define GCC_USB30_SLV_AHB_CLK 80 > +#define GCC_USB3_PHY_AUX_CLK 81 > +#define GCC_USB3_PHY_AUX_CLK_SRC 82 > +#define GCC_USB3_PHY_PIPE_CLK 83 > +#define GCC_USB3_PRIM_CLKREF_CLK 84 > +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 85 > +#define GCC_XO_DIV4_CLK 86 > +#define GCC_XO_PCIE_LINK_CLK 87 > + > +#define GCC_EMAC_BCR 0 > +#define GCC_PCIE_BCR 1 > +#define GCC_PCIE_LINK_DOWN_BCR 2 > +#define GCC_PCIE_NOCSR_COM_PHY_BCR 3 > +#define GCC_PCIE_PHY_BCR 4 > +#define GCC_PCIE_PHY_CFG_AHB_BCR 5 > +#define GCC_PCIE_PHY_COM_BCR 6 > +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 7 > +#define GCC_PDM_BCR 8 > +#define GCC_QUSB2PHY_BCR 9 > +#define GCC_TCSR_PCIE_BCR 10 > +#define GCC_USB30_BCR 11 > +#define GCC_USB3_PHY_BCR 12 > +#define GCC_USB3PHY_PHY_BCR 13 > +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 14 > + > +#endif > -- > 2.17.1 > ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/4] dt-bindings: clock: Add SDX55 GCC clock bindings 2020-10-30 19:22 ` Rob Herring @ 2020-10-31 3:29 ` Manivannan Sadhasivam 2020-11-05 2:03 ` Stephen Boyd 0 siblings, 1 reply; 16+ messages in thread From: Manivannan Sadhasivam @ 2020-10-31 3:29 UTC (permalink / raw) To: Rob Herring Cc: sboyd, mturquette, bjorn.andersson, vkoul, linux-arm-msm, linux-clk, devicetree, linux-kernel Hi Rob, On Fri, Oct 30, 2020 at 02:22:25PM -0500, Rob Herring wrote: > On Wed, Oct 28, 2020 at 01:12:29PM +0530, Manivannan Sadhasivam wrote: > > From: Vinod Koul <vkoul@kernel.org> > > > > Add device tree bindings for global clock controller on SDX55 SoCs. > > > > Signed-off-by: Vinod Koul <vkoul@kernel.org> > > This should carry your S-o-b too. > Ah yes! > > --- > > .../bindings/clock/qcom,gcc-sdx55.yaml | 71 +++++++++++ > > include/dt-bindings/clock/qcom,gcc-sdx55.h | 112 ++++++++++++++++++ > > 2 files changed, 183 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml > > create mode 100644 include/dt-bindings/clock/qcom,gcc-sdx55.h > > [...] > > diff --git a/include/dt-bindings/clock/qcom,gcc-sdx55.h b/include/dt-bindings/clock/qcom,gcc-sdx55.h > > new file mode 100644 > > index 000000000000..09ca45c6de73 > > --- /dev/null > > +++ b/include/dt-bindings/clock/qcom,gcc-sdx55.h > > @@ -0,0 +1,112 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > Dual license? > The downstream code just lists the GPL2.0 and I'm not sure if I can make it as dual license. Whereas the binding we made it dual license since we authored it. Thanks, Mani > > +/* > > + * Copyright (c) 2018, The Linux Foundation. All rights reserved. > > + * Copyright (c) 2020, Linaro Ltd. > > + */ > > + > > +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX55_H > > +#define _DT_BINDINGS_CLK_QCOM_GCC_SDX55_H > > + > > +#define GPLL0 3 > > +#define GPLL0_OUT_EVEN 4 > > +#define GPLL4 5 > > +#define GPLL4_OUT_EVEN 6 > > +#define GPLL5 7 > > +#define GCC_AHB_PCIE_LINK_CLK 8 > > +#define GCC_BLSP1_AHB_CLK 9 > > +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 10 > > +#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC 11 > > +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 12 > > +#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC 13 > > +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 14 > > +#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC 15 > > +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 16 > > +#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC 17 > > +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 18 > > +#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC 19 > > +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 20 > > +#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC 21 > > +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 22 > > +#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC 23 > > +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 24 > > +#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC 25 > > +#define GCC_BLSP1_UART1_APPS_CLK 26 > > +#define GCC_BLSP1_UART1_APPS_CLK_SRC 27 > > +#define GCC_BLSP1_UART2_APPS_CLK 28 > > +#define GCC_BLSP1_UART2_APPS_CLK_SRC 29 > > +#define GCC_BLSP1_UART3_APPS_CLK 30 > > +#define GCC_BLSP1_UART3_APPS_CLK_SRC 31 > > +#define GCC_BLSP1_UART4_APPS_CLK 32 > > +#define GCC_BLSP1_UART4_APPS_CLK_SRC 33 > > +#define GCC_BOOT_ROM_AHB_CLK 34 > > +#define GCC_CE1_AHB_CLK 35 > > +#define GCC_CE1_AXI_CLK 36 > > +#define GCC_CE1_CLK 37 > > +#define GCC_CPUSS_AHB_CLK 38 > > +#define GCC_CPUSS_AHB_CLK_SRC 39 > > +#define GCC_CPUSS_GNOC_CLK 40 > > +#define GCC_CPUSS_RBCPR_CLK 41 > > +#define GCC_CPUSS_RBCPR_CLK_SRC 42 > > +#define GCC_EMAC_CLK_SRC 43 > > +#define GCC_EMAC_PTP_CLK_SRC 44 > > +#define GCC_ETH_AXI_CLK 45 > > +#define GCC_ETH_PTP_CLK 46 > > +#define GCC_ETH_RGMII_CLK 47 > > +#define GCC_ETH_SLAVE_AHB_CLK 48 > > +#define GCC_GP1_CLK 49 > > +#define GCC_GP1_CLK_SRC 50 > > +#define GCC_GP2_CLK 51 > > +#define GCC_GP2_CLK_SRC 52 > > +#define GCC_GP3_CLK 53 > > +#define GCC_GP3_CLK_SRC 54 > > +#define GCC_PCIE_0_CLKREF_CLK 55 > > +#define GCC_PCIE_AUX_CLK 56 > > +#define GCC_PCIE_AUX_PHY_CLK_SRC 57 > > +#define GCC_PCIE_CFG_AHB_CLK 58 > > +#define GCC_PCIE_MSTR_AXI_CLK 59 > > +#define GCC_PCIE_PIPE_CLK 60 > > +#define GCC_PCIE_RCHNG_PHY_CLK 61 > > +#define GCC_PCIE_RCHNG_PHY_CLK_SRC 62 > > +#define GCC_PCIE_SLEEP_CLK 63 > > +#define GCC_PCIE_SLV_AXI_CLK 64 > > +#define GCC_PCIE_SLV_Q2A_AXI_CLK 65 > > +#define GCC_PDM2_CLK 66 > > +#define GCC_PDM2_CLK_SRC 67 > > +#define GCC_PDM_AHB_CLK 68 > > +#define GCC_PDM_XO4_CLK 69 > > +#define GCC_SDCC1_AHB_CLK 70 > > +#define GCC_SDCC1_APPS_CLK 71 > > +#define GCC_SDCC1_APPS_CLK_SRC 72 > > +#define GCC_SYS_NOC_CPUSS_AHB_CLK 73 > > +#define GCC_USB30_MASTER_CLK 74 > > +#define GCC_USB30_MASTER_CLK_SRC 75 > > +#define GCC_USB30_MOCK_UTMI_CLK 76 > > +#define GCC_USB30_MOCK_UTMI_CLK_SRC 77 > > +#define GCC_USB30_MSTR_AXI_CLK 78 > > +#define GCC_USB30_SLEEP_CLK 79 > > +#define GCC_USB30_SLV_AHB_CLK 80 > > +#define GCC_USB3_PHY_AUX_CLK 81 > > +#define GCC_USB3_PHY_AUX_CLK_SRC 82 > > +#define GCC_USB3_PHY_PIPE_CLK 83 > > +#define GCC_USB3_PRIM_CLKREF_CLK 84 > > +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 85 > > +#define GCC_XO_DIV4_CLK 86 > > +#define GCC_XO_PCIE_LINK_CLK 87 > > + > > +#define GCC_EMAC_BCR 0 > > +#define GCC_PCIE_BCR 1 > > +#define GCC_PCIE_LINK_DOWN_BCR 2 > > +#define GCC_PCIE_NOCSR_COM_PHY_BCR 3 > > +#define GCC_PCIE_PHY_BCR 4 > > +#define GCC_PCIE_PHY_CFG_AHB_BCR 5 > > +#define GCC_PCIE_PHY_COM_BCR 6 > > +#define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR 7 > > +#define GCC_PDM_BCR 8 > > +#define GCC_QUSB2PHY_BCR 9 > > +#define GCC_TCSR_PCIE_BCR 10 > > +#define GCC_USB30_BCR 11 > > +#define GCC_USB3_PHY_BCR 12 > > +#define GCC_USB3PHY_PHY_BCR 13 > > +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 14 > > + > > +#endif > > -- > > 2.17.1 > > ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/4] dt-bindings: clock: Add SDX55 GCC clock bindings 2020-10-31 3:29 ` Manivannan Sadhasivam @ 2020-11-05 2:03 ` Stephen Boyd 0 siblings, 0 replies; 16+ messages in thread From: Stephen Boyd @ 2020-11-05 2:03 UTC (permalink / raw) To: Manivannan Sadhasivam, Rob Herring Cc: mturquette, bjorn.andersson, vkoul, linux-arm-msm, linux-clk, devicetree, linux-kernel Quoting Manivannan Sadhasivam (2020-10-30 20:29:44) > Hi Rob, > > On Fri, Oct 30, 2020 at 02:22:25PM -0500, Rob Herring wrote: > > On Wed, Oct 28, 2020 at 01:12:29PM +0530, Manivannan Sadhasivam wrote: > > > From: Vinod Koul <vkoul@kernel.org> > > > > > > Add device tree bindings for global clock controller on SDX55 SoCs. > > > > > > Signed-off-by: Vinod Koul <vkoul@kernel.org> > > > > This should carry your S-o-b too. > > > > Ah yes! > > > > --- > > > .../bindings/clock/qcom,gcc-sdx55.yaml | 71 +++++++++++ > > > include/dt-bindings/clock/qcom,gcc-sdx55.h | 112 ++++++++++++++++++ > > > 2 files changed, 183 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml > > > create mode 100644 include/dt-bindings/clock/qcom,gcc-sdx55.h > > > > > [...] > > > > diff --git a/include/dt-bindings/clock/qcom,gcc-sdx55.h b/include/dt-bindings/clock/qcom,gcc-sdx55.h > > > new file mode 100644 > > > index 000000000000..09ca45c6de73 > > > --- /dev/null > > > +++ b/include/dt-bindings/clock/qcom,gcc-sdx55.h > > > @@ -0,0 +1,112 @@ > > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > > > Dual license? > > > > The downstream code just lists the GPL2.0 and I'm not sure if I can make > it as dual license. Whereas the binding we made it dual license since we Can you check? qcom has been doing it so I suspect you should just ask. ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/4] clk: qcom: Add SDX55 GCC support 2020-10-28 7:42 [PATCH 0/4] Add GCC and RPMh clock support for SDX55 Manivannan Sadhasivam 2020-10-28 7:42 ` [PATCH 1/4] dt-bindings: clock: Add SDX55 GCC clock bindings Manivannan Sadhasivam @ 2020-10-28 7:42 ` Manivannan Sadhasivam 2020-11-05 2:23 ` Stephen Boyd 2020-10-28 7:42 ` [PATCH 3/4] dt-bindings: clock: Introduce RPMHCC bindings for SDX55 Manivannan Sadhasivam ` (2 subsequent siblings) 4 siblings, 1 reply; 16+ messages in thread From: Manivannan Sadhasivam @ 2020-10-28 7:42 UTC (permalink / raw) To: sboyd, mturquette, robh+dt Cc: bjorn.andersson, vkoul, linux-arm-msm, linux-clk, devicetree, linux-kernel, Naveen Yadav, Manivannan Sadhasivam From: Naveen Yadav <naveenky@codeaurora.org> Add Global Clock Controller (GCC) support for SDX55 SoCs from Qualcomm. Signed-off-by: Naveen Yadav <naveenky@codeaurora.org> [mani: converted to parent_data, commented critical clocks, cleanups] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-sdx55.c | 1667 ++++++++++++++++++++++++++++++++++ 3 files changed, 1676 insertions(+) create mode 100644 drivers/clk/qcom/gcc-sdx55.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 3a965bd326d5..dbca8debc06f 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -502,4 +502,12 @@ config KRAITCC Support for the Krait CPU clocks on Qualcomm devices. Say Y if you want to support CPU frequency scaling. +config GCC_SDX55 + tristate "SDX55 Global Clock Controller" + depends on ARM + help + Support for the global clock controller on SDX55 devices. + Say Y if you want to use peripheral devices such as UART, + SPI, I2C, USB, SD/UFS, PCIe etc. + endif diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 11ae86febe87..3e27d67f95aa 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -75,3 +75,4 @@ obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o obj-$(CONFIG_QCOM_HFPLL) += hfpll.o obj-$(CONFIG_KRAITCC) += krait-cc.o +obj-$(CONFIG_GCC_SDX55) += gcc-sdx55.o diff --git a/drivers/clk/qcom/gcc-sdx55.c b/drivers/clk/qcom/gcc-sdx55.c new file mode 100644 index 000000000000..75831c829202 --- /dev/null +++ b/drivers/clk/qcom/gcc-sdx55.c @@ -0,0 +1,1667 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020, Linaro Ltd. + */ + +#include <linux/clk-provider.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,gcc-sdx55.h> + +#include "common.h" +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "reset.h" + +enum { + P_BI_TCXO, + P_CORE_BI_PLL_TEST_SE, + P_GPLL0_OUT_EVEN, + P_GPLL0_OUT_MAIN, + P_GPLL4_OUT_EVEN, + P_GPLL5_OUT_MAIN, + P_SLEEP_CLK, +}; + +static struct pll_vco lucid_vco[] = { + { 249600000, 2000000000, 0 }, +}; + +static struct clk_alpha_pll gpll0 = { + .offset = 0x0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .vco_table = lucid_vco, + .num_vco = ARRAY_SIZE(lucid_vco), + .clkr = { + .enable_reg = 0x6d000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpll0", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_lucid_even[] = { + { 0x0, 1 }, + { 0x1, 2 }, + { 0x3, 4 }, + { 0x7, 8 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll0_out_even = { + .offset = 0x0, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .post_div_shift = 8, + .post_div_table = post_div_table_lucid_even, + .num_post_div = ARRAY_SIZE(post_div_table_lucid_even), + .width = 4, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll0_out_even", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "gpll0", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_lucid_ops, + }, +}; + +static struct clk_alpha_pll gpll4 = { + .offset = 0x76000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .vco_table = lucid_vco, + .num_vco = ARRAY_SIZE(lucid_vco), + .clkr = { + .enable_reg = 0x6d000, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gpll4", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ops, + }, + }, +}; + +static struct clk_alpha_pll_postdiv gpll4_out_even = { + .offset = 0x76000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .post_div_shift = 8, + .post_div_table = post_div_table_lucid_even, + .num_post_div = ARRAY_SIZE(post_div_table_lucid_even), + .width = 4, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll4_out_even", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "gpll4", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_lucid_ops, + }, +}; + +static struct clk_alpha_pll gpll5 = { + .offset = 0x74000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], + .vco_table = lucid_vco, + .num_vco = ARRAY_SIZE(lucid_vco), + .clkr = { + .enable_reg = 0x6d000, + .enable_mask = BIT(5), + .hw.init = &(struct clk_init_data){ + .name = "gpll5", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ops, + }, + }, +}; + +static const struct parent_map gcc_parent_map_0[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL0_OUT_EVEN, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const struct clk_parent_data gcc_parents_0[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_out_even.clkr.hw }, + { .fw_name = "core_bi_pll_test_se" }, +}; + +static const struct clk_parent_data gcc_parents_0_ao[] = { + { .fw_name = "bi_tcxo_ao" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_out_even.clkr.hw }, + { .fw_name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map gcc_parent_map_2[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL4_OUT_EVEN, 2 }, + { P_GPLL5_OUT_MAIN, 5 }, + { P_GPLL0_OUT_EVEN, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const struct clk_parent_data gcc_parents_2[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll4_out_even.clkr.hw }, + { .hw = &gpll5.clkr.hw }, + { .hw = &gpll0_out_even.clkr.hw }, + { .fw_name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map gcc_parent_map_3[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_SLEEP_CLK, 5 }, + { P_GPLL0_OUT_EVEN, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const struct clk_parent_data gcc_parents_3[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpll0.clkr.hw }, + { .fw_name = "sleep_clk", .name = "sleep_clk" }, + { .hw = &gpll0_out_even.clkr.hw }, + { .fw_name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map gcc_parent_map_4[] = { + { P_BI_TCXO, 0 }, + { P_SLEEP_CLK, 5 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const struct clk_parent_data gcc_parents_4[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "sleep_clk", .name = "sleep_clk" }, + { .fw_name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map gcc_parent_map_5[] = { + { P_BI_TCXO, 0 }, + { P_GPLL0_OUT_MAIN, 1 }, + { P_GPLL4_OUT_EVEN, 2 }, + { P_GPLL0_OUT_EVEN, 6 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const struct clk_parent_data gcc_parents_5[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll4_out_even.clkr.hw }, + { .hw = &gpll0_out_even.clkr.hw }, + { .fw_name = "core_bi_pll_test_se" }, +}; + +static const struct freq_tbl ftbl_gcc_blsp1_qup1_i2c_apps_clk_src[] = { + F(9600000, P_BI_TCXO, 2, 0, 0), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_blsp1_qup1_i2c_apps_clk_src = { + .cmd_rcgr = 0x11024, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup1_i2c_apps_clk_src", + .parent_data = gcc_parents_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk_src[] = { + F(960000, P_BI_TCXO, 10, 1, 2), + F(4800000, P_BI_TCXO, 4, 0, 0), + F(9600000, P_BI_TCXO, 2, 0, 0), + F(15000000, P_GPLL0_OUT_EVEN, 5, 1, 4), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(24000000, P_GPLL0_OUT_MAIN, 12.5, 1, 2), + F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), + F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_blsp1_qup1_spi_apps_clk_src = { + .cmd_rcgr = 0x1100c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup1_spi_apps_clk_src", + .parent_data = gcc_parents_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_blsp1_qup2_i2c_apps_clk_src = { + .cmd_rcgr = 0x13024, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup2_i2c_apps_clk_src", + .parent_data = gcc_parents_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_blsp1_qup2_spi_apps_clk_src = { + .cmd_rcgr = 0x1300c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup2_spi_apps_clk_src", + .parent_data = gcc_parents_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_blsp1_qup3_i2c_apps_clk_src = { + .cmd_rcgr = 0x15024, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup3_i2c_apps_clk_src", + .parent_data = gcc_parents_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_blsp1_qup3_spi_apps_clk_src = { + .cmd_rcgr = 0x1500c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup3_spi_apps_clk_src", + .parent_data = gcc_parents_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_blsp1_qup4_i2c_apps_clk_src = { + .cmd_rcgr = 0x17024, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup4_i2c_apps_clk_src", + .parent_data = gcc_parents_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_blsp1_qup4_spi_apps_clk_src = { + .cmd_rcgr = 0x1700c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup4_spi_apps_clk_src", + .parent_data = gcc_parents_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_blsp1_uart1_apps_clk_src[] = { + F(3686400, P_GPLL0_OUT_EVEN, 1, 192, 15625), + F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), + F(9600000, P_BI_TCXO, 2, 0, 0), + F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), + F(16000000, P_GPLL0_OUT_EVEN, 1, 4, 75), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(19354839, P_GPLL0_OUT_MAIN, 15.5, 1, 2), + F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2), + F(20689655, P_GPLL0_OUT_MAIN, 14.5, 1, 2), + F(21428571, P_GPLL0_OUT_MAIN, 14, 1, 2), + F(22222222, P_GPLL0_OUT_MAIN, 13.5, 1, 2), + F(23076923, P_GPLL0_OUT_MAIN, 13, 1, 2), + F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5), + F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), + F(26086957, P_GPLL0_OUT_MAIN, 11.5, 1, 2), + F(27272727, P_GPLL0_OUT_MAIN, 11, 1, 2), + F(28571429, P_GPLL0_OUT_MAIN, 10.5, 1, 2), + F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75), + F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0), + F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375), + F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), + F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375), + F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75), + F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625), + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_blsp1_uart1_apps_clk_src = { + .cmd_rcgr = 0x1200c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart1_apps_clk_src", + .parent_data = gcc_parents_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_blsp1_uart2_apps_clk_src = { + .cmd_rcgr = 0x1400c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart2_apps_clk_src", + .parent_data = gcc_parents_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_blsp1_uart3_apps_clk_src = { + .cmd_rcgr = 0x1600c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart3_apps_clk_src", + .parent_data = gcc_parents_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_blsp1_uart4_apps_clk_src = { + .cmd_rcgr = 0x1800c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart4_apps_clk_src", + .parent_data = gcc_parents_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { + .cmd_rcgr = 0x24010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_cpuss_ahb_clk_src", + .parent_data = gcc_parents_0_ao, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = { + .cmd_rcgr = 0x2402c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_cpuss_rbcpr_clk_src", + .parent_data = gcc_parents_0_ao, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_emac_clk_src[] = { + F(2500000, P_BI_TCXO, 1, 25, 192), + F(5000000, P_BI_TCXO, 1, 25, 96), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(250000000, P_GPLL4_OUT_EVEN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_emac_clk_src = { + .cmd_rcgr = 0x47020, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_5, + .freq_tbl = ftbl_gcc_emac_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_emac_clk_src", + .parent_data = gcc_parents_5, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(230400000, P_GPLL5_OUT_MAIN, 3.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_emac_ptp_clk_src = { + .cmd_rcgr = 0x47038, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_emac_ptp_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_emac_ptp_clk_src", + .parent_data = gcc_parents_2, + .num_parents = 6, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), + F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), + F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_gp1_clk_src = { + .cmd_rcgr = 0x2b004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_gp1_clk_src", + .parent_data = gcc_parents_3, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_gp2_clk_src = { + .cmd_rcgr = 0x2c004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_gp2_clk_src", + .parent_data = gcc_parents_3, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_gp3_clk_src = { + .cmd_rcgr = 0x2d004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_gp3_clk_src", + .parent_data = gcc_parents_3, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_aux_phy_clk_src = { + .cmd_rcgr = 0x37034, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_4, + .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_aux_phy_clk_src", + .parent_data = gcc_parents_4, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie_rchng_phy_clk_src[] = { + F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie_rchng_phy_clk_src = { + .cmd_rcgr = 0x37050, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_pcie_rchng_phy_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_rchng_phy_clk_src", + .parent_data = gcc_parents_3, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { + F(9600000, P_BI_TCXO, 2, 0, 0), + F(19200000, P_BI_TCXO, 1, 0, 0), + F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pdm2_clk_src = { + .cmd_rcgr = 0x19010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_pdm2_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_pdm2_clk_src", + .parent_data = gcc_parents_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { + .cmd_rcgr = 0xf00c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_apps_clk_src", + .parent_data = gcc_parents_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb30_master_clk_src[] = { + F(200000000, P_GPLL0_OUT_EVEN, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb30_master_clk_src = { + .cmd_rcgr = 0xb024, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_usb30_master_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_master_clk_src", + .parent_data = gcc_parents_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb30_mock_utmi_clk_src = { + .cmd_rcgr = 0xb03c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_mock_utmi_clk_src", + .parent_data = gcc_parents_0, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb3_phy_aux_clk_src[] = { + F(1000000, P_BI_TCXO, 1, 5, 96), + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb3_phy_aux_clk_src = { + .cmd_rcgr = 0xb064, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_4, + .freq_tbl = ftbl_gcc_usb3_phy_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_phy_aux_clk_src", + .parent_data = gcc_parents_4, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_ahb_pcie_link_clk = { + .halt_reg = 0x22004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x22004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ahb_pcie_link_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_ahb_clk = { + .halt_reg = 0x10004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x6d008, + .enable_mask = BIT(14), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { + .halt_reg = 0x11008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup1_i2c_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_blsp1_qup1_i2c_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { + .halt_reg = 0x11004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x11004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup1_spi_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { + .halt_reg = 0x13008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup2_i2c_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_blsp1_qup2_i2c_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { + .halt_reg = 0x13004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x13004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup2_spi_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { + .halt_reg = 0x15008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup3_i2c_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_blsp1_qup3_i2c_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { + .halt_reg = 0x15004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x15004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup3_spi_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { + .halt_reg = 0x17008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x17008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup4_i2c_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_blsp1_qup4_i2c_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { + .halt_reg = 0x17004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x17004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup4_spi_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_blsp1_qup4_spi_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart1_apps_clk = { + .halt_reg = 0x12004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x12004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart1_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_blsp1_uart1_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart2_apps_clk = { + .halt_reg = 0x14004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x14004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart2_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_blsp1_uart2_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart3_apps_clk = { + .halt_reg = 0x16004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x16004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart3_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_blsp1_uart3_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart4_apps_clk = { + .halt_reg = 0x18004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x18004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart4_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_blsp1_uart4_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk = { + .halt_reg = 0x1c004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x1c004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x6d008, + .enable_mask = BIT(10), + .hw.init = &(struct clk_init_data){ + .name = "gcc_boot_rom_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ce1_ahb_clk = { + .halt_reg = 0x2100c, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x2100c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x6d008, + .enable_mask = BIT(3), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ce1_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ce1_axi_clk = { + .halt_reg = 0x21008, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x6d008, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ce1_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ce1_clk = { + .halt_reg = 0x21004, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x6d008, + .enable_mask = BIT(5), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ce1_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +/* For CPUSS functionality the AHB clock needs to be left enabled */ +static struct clk_branch gcc_cpuss_ahb_clk = { + .halt_reg = 0x24000, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x6d008, + .enable_mask = BIT(21), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cpuss_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_cpuss_ahb_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +/* For CPUSS functionality the GNOC clock needs to be left enabled */ +static struct clk_branch gcc_cpuss_gnoc_clk = { + .halt_reg = 0x24004, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x24004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x6d008, + .enable_mask = BIT(22), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cpuss_gnoc_clk", + .flags = CLK_IS_CRITICAL, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cpuss_rbcpr_clk = { + .halt_reg = 0x24008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x24008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cpuss_rbcpr_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_cpuss_rbcpr_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_eth_axi_clk = { + .halt_reg = 0x4701c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4701c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_eth_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_eth_ptp_clk = { + .halt_reg = 0x47018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x47018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_eth_ptp_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_emac_ptp_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_eth_rgmii_clk = { + .halt_reg = 0x47010, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x47010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_eth_rgmii_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_emac_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_eth_slave_ahb_clk = { + .halt_reg = 0x47014, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x47014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_eth_slave_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk = { + .halt_reg = 0x2b000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2b000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp1_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_gp1_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk = { + .halt_reg = 0x2c000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2c000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp2_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_gp2_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk = { + .halt_reg = 0x2d000, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2d000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp3_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_gp3_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_clkref_clk = { + .halt_reg = 0x88004, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x88004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_0_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_aux_clk = { + .halt_reg = 0x37024, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x6d010, + .enable_mask = BIT(3), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_aux_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_cfg_ahb_clk = { + .halt_reg = 0x3701c, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x6d010, + .enable_mask = BIT(2), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_mstr_axi_clk = { + .halt_reg = 0x37018, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x6d010, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_mstr_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_pipe_clk = { + .halt_reg = 0x3702c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x6d010, + .enable_mask = BIT(4), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_pipe_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_rchng_phy_clk = { + .halt_reg = 0x37020, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x6d010, + .enable_mask = BIT(7), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_rchng_phy_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_pcie_rchng_phy_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_sleep_clk = { + .halt_reg = 0x37028, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x6d010, + .enable_mask = BIT(6), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_sleep_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_pcie_aux_phy_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_slv_axi_clk = { + .halt_reg = 0x37014, + .halt_check = BRANCH_HALT_VOTED, + .hwcg_reg = 0x37014, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x6d010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_slv_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_slv_q2a_axi_clk = { + .halt_reg = 0x37010, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x6d010, + .enable_mask = BIT(5), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_slv_q2a_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk = { + .halt_reg = 0x1900c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x1900c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm2_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_pdm2_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk = { + .halt_reg = 0x19004, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0x19004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x19004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_xo4_clk = { + .halt_reg = 0x19008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x19008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm_xo4_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk = { + .halt_reg = 0xf008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk = { + .halt_reg = 0xf004, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xf004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_sdcc1_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +/* For CPUSS functionality the SYS NOC clock needs to be left enabled */ +static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { + .halt_reg = 0x4010, + .halt_check = BRANCH_HALT_VOTED, + .clkr = { + .enable_reg = 0x6d008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sys_noc_cpuss_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_cpuss_ahb_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_master_clk = { + .halt_reg = 0xb010, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xb010, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_master_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_usb30_master_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_mock_utmi_clk = { + .halt_reg = 0xb020, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xb020, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_mock_utmi_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_usb30_mock_utmi_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_mstr_axi_clk = { + .halt_reg = 0xb014, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xb014, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_mstr_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_sleep_clk = { + .halt_reg = 0xb01c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xb01c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_slv_ahb_clk = { + .halt_reg = 0xb018, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xb018, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_slv_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_phy_aux_clk = { + .halt_reg = 0xb058, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0xb058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_phy_aux_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_usb3_phy_aux_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_phy_pipe_clk = { + .halt_reg = 0xb05c, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0xb05c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_phy_pipe_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_clkref_clk = { + .halt_reg = 0x88000, + .halt_check = BRANCH_HALT_DELAY, + .clkr = { + .enable_reg = 0x88000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_prim_clkref_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { + .halt_reg = 0xe004, + .halt_check = BRANCH_HALT, + .hwcg_reg = 0xe004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xe004, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb_phy_cfg_ahb2phy_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_xo_pcie_link_clk = { + .halt_reg = 0x22008, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x22008, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_xo_pcie_link_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *gcc_sdx55_clocks[] = { + [GCC_AHB_PCIE_LINK_CLK] = &gcc_ahb_pcie_link_clk.clkr, + [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, + [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC] = + &gcc_blsp1_qup1_i2c_apps_clk_src.clkr, + [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, + [GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = + &gcc_blsp1_qup1_spi_apps_clk_src.clkr, + [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC] = + &gcc_blsp1_qup2_i2c_apps_clk_src.clkr, + [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, + [GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = + &gcc_blsp1_qup2_spi_apps_clk_src.clkr, + [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC] = + &gcc_blsp1_qup3_i2c_apps_clk_src.clkr, + [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, + [GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = + &gcc_blsp1_qup3_spi_apps_clk_src.clkr, + [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, + [GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC] = + &gcc_blsp1_qup4_i2c_apps_clk_src.clkr, + [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, + [GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC] = + &gcc_blsp1_qup4_spi_apps_clk_src.clkr, + [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, + [GCC_BLSP1_UART1_APPS_CLK_SRC] = &gcc_blsp1_uart1_apps_clk_src.clkr, + [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, + [GCC_BLSP1_UART2_APPS_CLK_SRC] = &gcc_blsp1_uart2_apps_clk_src.clkr, + [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, + [GCC_BLSP1_UART3_APPS_CLK_SRC] = &gcc_blsp1_uart3_apps_clk_src.clkr, + [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, + [GCC_BLSP1_UART4_APPS_CLK_SRC] = &gcc_blsp1_uart4_apps_clk_src.clkr, + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, + [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, + [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, + [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, + [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, + [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, + [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, + [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, + [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr, + [GCC_EMAC_CLK_SRC] = &gcc_emac_clk_src.clkr, + [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr, + [GCC_ETH_AXI_CLK] = &gcc_eth_axi_clk.clkr, + [GCC_ETH_PTP_CLK] = &gcc_eth_ptp_clk.clkr, + [GCC_ETH_RGMII_CLK] = &gcc_eth_rgmii_clk.clkr, + [GCC_ETH_SLAVE_AHB_CLK] = &gcc_eth_slave_ahb_clk.clkr, + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, + [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, + [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, + [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, + [GCC_PCIE_0_CLKREF_CLK] = &gcc_pcie_0_clkref_clk.clkr, + [GCC_PCIE_AUX_CLK] = &gcc_pcie_aux_clk.clkr, + [GCC_PCIE_AUX_PHY_CLK_SRC] = &gcc_pcie_aux_phy_clk_src.clkr, + [GCC_PCIE_CFG_AHB_CLK] = &gcc_pcie_cfg_ahb_clk.clkr, + [GCC_PCIE_MSTR_AXI_CLK] = &gcc_pcie_mstr_axi_clk.clkr, + [GCC_PCIE_PIPE_CLK] = &gcc_pcie_pipe_clk.clkr, + [GCC_PCIE_RCHNG_PHY_CLK] = &gcc_pcie_rchng_phy_clk.clkr, + [GCC_PCIE_RCHNG_PHY_CLK_SRC] = &gcc_pcie_rchng_phy_clk_src.clkr, + [GCC_PCIE_SLEEP_CLK] = &gcc_pcie_sleep_clk.clkr, + [GCC_PCIE_SLV_AXI_CLK] = &gcc_pcie_slv_axi_clk.clkr, + [GCC_PCIE_SLV_Q2A_AXI_CLK] = &gcc_pcie_slv_q2a_axi_clk.clkr, + [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, + [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, + [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, + [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, + [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, + [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, + [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, + [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, + [GCC_USB30_MASTER_CLK_SRC] = &gcc_usb30_master_clk_src.clkr, + [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, + [GCC_USB30_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mock_utmi_clk_src.clkr, + [GCC_USB30_MSTR_AXI_CLK] = &gcc_usb30_mstr_axi_clk.clkr, + [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, + [GCC_USB30_SLV_AHB_CLK] = &gcc_usb30_slv_ahb_clk.clkr, + [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, + [GCC_USB3_PHY_AUX_CLK_SRC] = &gcc_usb3_phy_aux_clk_src.clkr, + [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, + [GCC_USB3_PRIM_CLKREF_CLK] = &gcc_usb3_prim_clkref_clk.clkr, + [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, + [GCC_XO_PCIE_LINK_CLK] = &gcc_xo_pcie_link_clk.clkr, + [GPLL0] = &gpll0.clkr, + [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, + [GPLL4] = &gpll4.clkr, + [GPLL4_OUT_EVEN] = &gpll4_out_even.clkr, + [GPLL5] = &gpll5.clkr, +}; + +static const struct qcom_reset_map gcc_sdx55_resets[] = { + [GCC_EMAC_BCR] = { 0x47000 }, + [GCC_PCIE_BCR] = { 0x37000 }, + [GCC_PCIE_LINK_DOWN_BCR] = { 0x77000 }, + [GCC_PCIE_PHY_BCR] = { 0x39000 }, + [GCC_PCIE_PHY_COM_BCR] = { 0x78004 }, + [GCC_QUSB2PHY_BCR] = { 0xd000 }, + [GCC_USB30_BCR] = { 0xb000 }, + [GCC_USB3_PHY_BCR] = { 0xc000 }, + [GCC_USB3PHY_PHY_BCR] = { 0xc004 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0xe000 }, +}; + +static const struct regmap_config gcc_sdx55_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9b040, + .fast_io = true, +}; + +static const struct qcom_cc_desc gcc_sdx55_desc = { + .config = &gcc_sdx55_regmap_config, + .clks = gcc_sdx55_clocks, + .num_clks = ARRAY_SIZE(gcc_sdx55_clocks), + .resets = gcc_sdx55_resets, + .num_resets = ARRAY_SIZE(gcc_sdx55_resets), +}; + +static const struct of_device_id gcc_sdx55_match_table[] = { + { .compatible = "qcom,gcc-sdx55" }, + { } +}; +MODULE_DEVICE_TABLE(of, gcc_sdx55_match_table); + +static int gcc_sdx55_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &gcc_sdx55_desc); +} + +static struct platform_driver gcc_sdx55_driver = { + .probe = gcc_sdx55_probe, + .driver = { + .name = "gcc-sdx55", + .of_match_table = gcc_sdx55_match_table, + }, +}; + +static int __init gcc_sdx55_init(void) +{ + return platform_driver_register(&gcc_sdx55_driver); +} +subsys_initcall(gcc_sdx55_init); + +static void __exit gcc_sdx55_exit(void) +{ + platform_driver_unregister(&gcc_sdx55_driver); +} +module_exit(gcc_sdx55_exit); + +MODULE_DESCRIPTION("QTI GCC SDX55 Driver"); +MODULE_LICENSE("GPL v2"); -- 2.17.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 2/4] clk: qcom: Add SDX55 GCC support 2020-10-28 7:42 ` [PATCH 2/4] clk: qcom: Add SDX55 GCC support Manivannan Sadhasivam @ 2020-11-05 2:23 ` Stephen Boyd 2020-11-05 8:51 ` Manivannan Sadhasivam 0 siblings, 1 reply; 16+ messages in thread From: Stephen Boyd @ 2020-11-05 2:23 UTC (permalink / raw) To: Manivannan Sadhasivam, mturquette, robh+dt Cc: bjorn.andersson, vkoul, linux-arm-msm, linux-clk, devicetree, linux-kernel, Naveen Yadav, Manivannan Sadhasivam Quoting Manivannan Sadhasivam (2020-10-28 00:42:30) > From: Naveen Yadav <naveenky@codeaurora.org> > > Add Global Clock Controller (GCC) support for SDX55 SoCs from Qualcomm. > > Signed-off-by: Naveen Yadav <naveenky@codeaurora.org> > [mani: converted to parent_data, commented critical clocks, cleanups] > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > drivers/clk/qcom/Kconfig | 8 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/gcc-sdx55.c | 1667 ++++++++++++++++++++++++++++++++++ > 3 files changed, 1676 insertions(+) > create mode 100644 drivers/clk/qcom/gcc-sdx55.c > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index 3a965bd326d5..dbca8debc06f 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -502,4 +502,12 @@ config KRAITCC > Support for the Krait CPU clocks on Qualcomm devices. > Say Y if you want to support CPU frequency scaling. > > +config GCC_SDX55 Please sort instead of add at end. > + tristate "SDX55 Global Clock Controller" > + depends on ARM Why? > + help > + Support for the global clock controller on SDX55 devices. > + Say Y if you want to use peripheral devices such as UART, > + SPI, I2C, USB, SD/UFS, PCIe etc. > + > endif > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > index 11ae86febe87..3e27d67f95aa 100644 > --- a/drivers/clk/qcom/Makefile > +++ b/drivers/clk/qcom/Makefile > @@ -75,3 +75,4 @@ obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o > obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o > obj-$(CONFIG_QCOM_HFPLL) += hfpll.o > obj-$(CONFIG_KRAITCC) += krait-cc.o > +obj-$(CONFIG_GCC_SDX55) += gcc-sdx55.o Please sort this instead of add at end. > diff --git a/drivers/clk/qcom/gcc-sdx55.c b/drivers/clk/qcom/gcc-sdx55.c > new file mode 100644 > index 000000000000..75831c829202 > --- /dev/null > +++ b/drivers/clk/qcom/gcc-sdx55.c > @@ -0,0 +1,1667 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. > + * Copyright (c) 2020, Linaro Ltd. > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/module.h> > +#include <linux/platform_device.h> > +#include <linux/regmap.h> > + > +#include <dt-bindings/clock/qcom,gcc-sdx55.h> > + > +#include "common.h" > +#include "clk-alpha-pll.h" > +#include "clk-branch.h" > +#include "clk-pll.h" > +#include "clk-rcg.h" > +#include "clk-regmap.h" > +#include "reset.h" > + > +enum { > + P_BI_TCXO, > + P_CORE_BI_PLL_TEST_SE, > + P_GPLL0_OUT_EVEN, > + P_GPLL0_OUT_MAIN, > + P_GPLL4_OUT_EVEN, > + P_GPLL5_OUT_MAIN, > + P_SLEEP_CLK, > +}; > + > +static struct pll_vco lucid_vco[] = { const > + { 249600000, 2000000000, 0 }, > +}; > + > +static struct clk_alpha_pll gpll0 = { > + .offset = 0x0, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], > + .vco_table = lucid_vco, > + .num_vco = ARRAY_SIZE(lucid_vco), > + .clkr = { > + .enable_reg = 0x6d000, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpll0", > + .parent_data = &(const struct clk_parent_data){ > + .fw_name = "bi_tcxo", > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_fixed_lucid_ops, > + }, > + }, > +}; > + > +static const struct clk_div_table post_div_table_lucid_even[] = { > + { 0x0, 1 }, > + { 0x1, 2 }, > + { 0x3, 4 }, > + { 0x7, 8 }, > + { } > +}; I think this table is common to all lucid plls? Maybe we can push it into the clk_ops somehow and stop duplicating it here? > + > +static struct clk_alpha_pll_postdiv gpll0_out_even = { > + .offset = 0x0, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], > + .post_div_shift = 8, > + .post_div_table = post_div_table_lucid_even, > + .num_post_div = ARRAY_SIZE(post_div_table_lucid_even), > + .width = 4, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "gpll0_out_even", > + .parent_data = &(const struct clk_parent_data){ > + .fw_name = "gpll0", > + }, If this is gpll0 in this file, then this should be a clk_hws pointer instead and directly pointing to the parent. > + .num_parents = 1, > + .ops = &clk_alpha_pll_postdiv_lucid_ops, > + }, > +}; > + > +static struct clk_alpha_pll gpll4 = { > + .offset = 0x76000, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], > + .vco_table = lucid_vco, > + .num_vco = ARRAY_SIZE(lucid_vco), > + .clkr = { > + .enable_reg = 0x6d000, > + .enable_mask = BIT(4), > + .hw.init = &(struct clk_init_data){ > + .name = "gpll4", > + .parent_data = &(const struct clk_parent_data){ > + .fw_name = "bi_tcxo", > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_fixed_lucid_ops, > + }, > + }, > +}; > + > +static struct clk_alpha_pll_postdiv gpll4_out_even = { > + .offset = 0x76000, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], > + .post_div_shift = 8, > + .post_div_table = post_div_table_lucid_even, > + .num_post_div = ARRAY_SIZE(post_div_table_lucid_even), > + .width = 4, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "gpll4_out_even", > + .parent_data = &(const struct clk_parent_data){ > + .fw_name = "gpll4", If this is gpll4 in this file, then this should be a clk_hws pointer instead and directly pointing to the parent. > + }, > + .num_parents = 1, > + .ops = &clk_alpha_pll_postdiv_lucid_ops, > + }, > +}; > + > +static struct clk_alpha_pll gpll5 = { > + .offset = 0x74000, > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], > + .vco_table = lucid_vco, > + .num_vco = ARRAY_SIZE(lucid_vco), [...] > + .name = "gcc_sdcc1_ahb_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gcc_sdcc1_apps_clk = { > + .halt_reg = 0xf004, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0xf004, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_sdcc1_apps_clk", > + .parent_hws = (const struct clk_hw *[]){ > + &gcc_sdcc1_apps_clk_src.clkr.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +/* For CPUSS functionality the SYS NOC clock needs to be left enabled */ > +static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { > + .halt_reg = 0x4010, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x6d008, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_sys_noc_cpuss_ahb_clk", > + .parent_hws = (const struct clk_hw *[]){ > + &gcc_cpuss_ahb_clk_src.clkr.hw }, > + .num_parents = 1, > + .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, These CLK_IS_CRITICAL clks can't be set once at driver probe time and forgotten about? It would be nice to not allocate memory for things that never matter. > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gcc_usb30_master_clk = { > + .halt_reg = 0xb010, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0xb010, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_usb30_master_clk", > + .parent_hws = (const struct clk_hw *[]){ > + &gcc_usb30_master_clk_src.clkr.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, [...] > + > +static const struct qcom_cc_desc gcc_sdx55_desc = { > + .config = &gcc_sdx55_regmap_config, > + .clks = gcc_sdx55_clocks, > + .num_clks = ARRAY_SIZE(gcc_sdx55_clocks), > + .resets = gcc_sdx55_resets, > + .num_resets = ARRAY_SIZE(gcc_sdx55_resets), No gdscs? > +}; > + > +static const struct of_device_id gcc_sdx55_match_table[] = { > + { .compatible = "qcom,gcc-sdx55" }, > + { } > +}; > +MODULE_DEVICE_TABLE(of, gcc_sdx55_match_table); > + > +static int gcc_sdx55_probe(struct platform_device *pdev) > +{ > + return qcom_cc_probe(pdev, &gcc_sdx55_desc); Wow haven't seen this in some time. There isn't some sort of PLL that needs configuring or some clks that need to be slammed on with a couple register writes? > +} > + ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/4] clk: qcom: Add SDX55 GCC support 2020-11-05 2:23 ` Stephen Boyd @ 2020-11-05 8:51 ` Manivannan Sadhasivam 2020-11-13 7:58 ` Stephen Boyd 0 siblings, 1 reply; 16+ messages in thread From: Manivannan Sadhasivam @ 2020-11-05 8:51 UTC (permalink / raw) To: Stephen Boyd Cc: mturquette, robh+dt, bjorn.andersson, vkoul, linux-arm-msm, linux-clk, devicetree, linux-kernel, Naveen Yadav On Wed, Nov 04, 2020 at 06:23:37PM -0800, Stephen Boyd wrote: > Quoting Manivannan Sadhasivam (2020-10-28 00:42:30) > > From: Naveen Yadav <naveenky@codeaurora.org> > > > > Add Global Clock Controller (GCC) support for SDX55 SoCs from Qualcomm. > > > > Signed-off-by: Naveen Yadav <naveenky@codeaurora.org> > > [mani: converted to parent_data, commented critical clocks, cleanups] > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > > --- > > drivers/clk/qcom/Kconfig | 8 + > > drivers/clk/qcom/Makefile | 1 + > > drivers/clk/qcom/gcc-sdx55.c | 1667 ++++++++++++++++++++++++++++++++++ > > 3 files changed, 1676 insertions(+) > > create mode 100644 drivers/clk/qcom/gcc-sdx55.c > > > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > > index 3a965bd326d5..dbca8debc06f 100644 > > --- a/drivers/clk/qcom/Kconfig > > +++ b/drivers/clk/qcom/Kconfig > > @@ -502,4 +502,12 @@ config KRAITCC > > Support for the Krait CPU clocks on Qualcomm devices. > > Say Y if you want to support CPU frequency scaling. > > > > +config GCC_SDX55 > > Please sort instead of add at end. > > > + tristate "SDX55 Global Clock Controller" > > + depends on ARM > > Why? > Not needed, will remove. > > + help > > + Support for the global clock controller on SDX55 devices. > > + Say Y if you want to use peripheral devices such as UART, > > + SPI, I2C, USB, SD/UFS, PCIe etc. > > + > > endif > > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > > index 11ae86febe87..3e27d67f95aa 100644 > > --- a/drivers/clk/qcom/Makefile > > +++ b/drivers/clk/qcom/Makefile > > @@ -75,3 +75,4 @@ obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o > > obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o > > obj-$(CONFIG_QCOM_HFPLL) += hfpll.o > > obj-$(CONFIG_KRAITCC) += krait-cc.o > > +obj-$(CONFIG_GCC_SDX55) += gcc-sdx55.o > > Please sort this instead of add at end. > > > diff --git a/drivers/clk/qcom/gcc-sdx55.c b/drivers/clk/qcom/gcc-sdx55.c > > new file mode 100644 > > index 000000000000..75831c829202 > > --- /dev/null > > +++ b/drivers/clk/qcom/gcc-sdx55.c > > @@ -0,0 +1,1667 @@ > > + [...] > > +static const struct clk_div_table post_div_table_lucid_even[] = { > > + { 0x0, 1 }, > > + { 0x1, 2 }, > > + { 0x3, 4 }, > > + { 0x7, 8 }, > > + { } > > +}; > > I think this table is common to all lucid plls? Maybe we can push it > into the clk_ops somehow and stop duplicating it here? > Are you referring to lucid plls in this driver? Because, this table is not common for other SoCs. And I don't think having this way introduces any overhead, so I'd prefer keeping it as it is. > > + > > +static struct clk_alpha_pll_postdiv gpll0_out_even = { > > + .offset = 0x0, > > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], > > + .post_div_shift = 8, > > + .post_div_table = post_div_table_lucid_even, > > + .num_post_div = ARRAY_SIZE(post_div_table_lucid_even), > > + .width = 4, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "gpll0_out_even", > > + .parent_data = &(const struct clk_parent_data){ > > + .fw_name = "gpll0", > > + }, > > If this is gpll0 in this file, then this should be a clk_hws pointer > instead and directly pointing to the parent. > Ack > > + .num_parents = 1, > > + .ops = &clk_alpha_pll_postdiv_lucid_ops, > > + }, > > +}; > > + > > +static struct clk_alpha_pll gpll4 = { > > + .offset = 0x76000, > > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], > > + .vco_table = lucid_vco, > > + .num_vco = ARRAY_SIZE(lucid_vco), > > + .clkr = { > > + .enable_reg = 0x6d000, > > + .enable_mask = BIT(4), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpll4", > > + .parent_data = &(const struct clk_parent_data){ > > + .fw_name = "bi_tcxo", > > + }, > > + .num_parents = 1, > > + .ops = &clk_alpha_pll_fixed_lucid_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_alpha_pll_postdiv gpll4_out_even = { > > + .offset = 0x76000, > > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], > > + .post_div_shift = 8, > > + .post_div_table = post_div_table_lucid_even, > > + .num_post_div = ARRAY_SIZE(post_div_table_lucid_even), > > + .width = 4, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "gpll4_out_even", > > + .parent_data = &(const struct clk_parent_data){ > > + .fw_name = "gpll4", > > If this is gpll4 in this file, then this should be a clk_hws pointer > instead and directly pointing to the parent. > Ack > > + }, > > + .num_parents = 1, > > + .ops = &clk_alpha_pll_postdiv_lucid_ops, > > + }, > > +}; > > + [...] > > +/* For CPUSS functionality the SYS NOC clock needs to be left enabled */ > > +static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { > > + .halt_reg = 0x4010, > > + .halt_check = BRANCH_HALT_VOTED, > > + .clkr = { > > + .enable_reg = 0x6d008, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gcc_sys_noc_cpuss_ahb_clk", > > + .parent_hws = (const struct clk_hw *[]){ > > + &gcc_cpuss_ahb_clk_src.clkr.hw }, > > + .num_parents = 1, > > + .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, > > These CLK_IS_CRITICAL clks can't be set once at driver probe time and > forgotten about? It would be nice to not allocate memory for things that > never matter. > Makes sense! But are we moving into the direction of deprecating the use of CLK_IS_CRITICAL? > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gcc_usb30_master_clk = { > > + .halt_reg = 0xb010, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0xb010, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gcc_usb30_master_clk", > > + .parent_hws = (const struct clk_hw *[]){ > > + &gcc_usb30_master_clk_src.clkr.hw }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > [...] > > + > > +static const struct qcom_cc_desc gcc_sdx55_desc = { > > + .config = &gcc_sdx55_regmap_config, > > + .clks = gcc_sdx55_clocks, > > + .num_clks = ARRAY_SIZE(gcc_sdx55_clocks), > > + .resets = gcc_sdx55_resets, > > + .num_resets = ARRAY_SIZE(gcc_sdx55_resets), > > No gdscs? > This will come at later point. > > +}; > > + > > +static const struct of_device_id gcc_sdx55_match_table[] = { > > + { .compatible = "qcom,gcc-sdx55" }, > > + { } > > +}; > > +MODULE_DEVICE_TABLE(of, gcc_sdx55_match_table); > > + > > +static int gcc_sdx55_probe(struct platform_device *pdev) > > +{ > > + return qcom_cc_probe(pdev, &gcc_sdx55_desc); > > Wow haven't seen this in some time. There isn't some sort of PLL that > needs configuring or some clks that need to be slammed on with a couple > register writes? > Nothing as per the downstream driver. Actually the downstream just sets the rate of few clocks but I don't find them useful at the moment. So, dropped the change. Thanks, Mani > > +} > > + ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/4] clk: qcom: Add SDX55 GCC support 2020-11-05 8:51 ` Manivannan Sadhasivam @ 2020-11-13 7:58 ` Stephen Boyd 0 siblings, 0 replies; 16+ messages in thread From: Stephen Boyd @ 2020-11-13 7:58 UTC (permalink / raw) To: Manivannan Sadhasivam Cc: mturquette, robh+dt, bjorn.andersson, vkoul, linux-arm-msm, linux-clk, devicetree, linux-kernel, Naveen Yadav Quoting Manivannan Sadhasivam (2020-11-05 00:51:48) > On Wed, Nov 04, 2020 at 06:23:37PM -0800, Stephen Boyd wrote: > > > diff --git a/drivers/clk/qcom/gcc-sdx55.c b/drivers/clk/qcom/gcc-sdx55.c > > > new file mode 100644 > > > index 000000000000..75831c829202 > > > --- /dev/null > > > +++ b/drivers/clk/qcom/gcc-sdx55.c > > > @@ -0,0 +1,1667 @@ > > > + > > [...] > > > > +static const struct clk_div_table post_div_table_lucid_even[] = { > > > + { 0x0, 1 }, > > > + { 0x1, 2 }, > > > + { 0x3, 4 }, > > > + { 0x7, 8 }, > > > + { } > > > +}; > > > > I think this table is common to all lucid plls? Maybe we can push it > > into the clk_ops somehow and stop duplicating it here? > > > > Are you referring to lucid plls in this driver? Because, this table is > not common for other SoCs. And I don't think having this way introduces > any overhead, so I'd prefer keeping it as it is. > Yes all lucid type PLLs probably have the same divider table. > > > > +/* For CPUSS functionality the SYS NOC clock needs to be left enabled */ > > > +static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { > > > + .halt_reg = 0x4010, > > > + .halt_check = BRANCH_HALT_VOTED, > > > + .clkr = { > > > + .enable_reg = 0x6d008, > > > + .enable_mask = BIT(0), > > > + .hw.init = &(struct clk_init_data){ > > > + .name = "gcc_sys_noc_cpuss_ahb_clk", > > > + .parent_hws = (const struct clk_hw *[]){ > > > + &gcc_cpuss_ahb_clk_src.clkr.hw }, > > > + .num_parents = 1, > > > + .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, > > > > These CLK_IS_CRITICAL clks can't be set once at driver probe time and > > forgotten about? It would be nice to not allocate memory for things that > > never matter. > > > > Makes sense! But are we moving into the direction of deprecating the use > of CLK_IS_CRITICAL? No? Just judiciously using it. ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 3/4] dt-bindings: clock: Introduce RPMHCC bindings for SDX55 2020-10-28 7:42 [PATCH 0/4] Add GCC and RPMh clock support for SDX55 Manivannan Sadhasivam 2020-10-28 7:42 ` [PATCH 1/4] dt-bindings: clock: Add SDX55 GCC clock bindings Manivannan Sadhasivam 2020-10-28 7:42 ` [PATCH 2/4] clk: qcom: Add SDX55 GCC support Manivannan Sadhasivam @ 2020-10-28 7:42 ` Manivannan Sadhasivam 2020-11-03 17:38 ` Bjorn Andersson 2020-10-28 7:42 ` [PATCH 4/4] clk: qcom: Add support for SDX55 RPMh clocks Manivannan Sadhasivam 2020-10-28 17:08 ` [PATCH 0/4] Add GCC and RPMh clock support for SDX55 Manivannan Sadhasivam 4 siblings, 1 reply; 16+ messages in thread From: Manivannan Sadhasivam @ 2020-10-28 7:42 UTC (permalink / raw) To: sboyd, mturquette, robh+dt Cc: bjorn.andersson, vkoul, linux-arm-msm, linux-clk, devicetree, linux-kernel From: Vinod Koul <vkoul@kernel.org> Add compatible for SDX55 RPMHCC and DT include. Signed-off-by: Vinod Koul <vkoul@kernel.org> --- Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + include/dt-bindings/clock/qcom,rpmh.h | 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index a46a3a799a70..a54930f111ba 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -19,6 +19,7 @@ properties: enum: - qcom,sc7180-rpmh-clk - qcom,sdm845-rpmh-clk + - qcom,sdx55-rpmh-clk - qcom,sm8150-rpmh-clk - qcom,sm8250-rpmh-clk diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h index 2e6c54e65455..cd806eccb7dd 100644 --- a/include/dt-bindings/clock/qcom,rpmh.h +++ b/include/dt-bindings/clock/qcom,rpmh.h @@ -21,5 +21,6 @@ #define RPMH_IPA_CLK 12 #define RPMH_LN_BB_CLK1 13 #define RPMH_LN_BB_CLK1_A 14 +#define RPMH_QPIC_CLK 15 #endif -- 2.17.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 3/4] dt-bindings: clock: Introduce RPMHCC bindings for SDX55 2020-10-28 7:42 ` [PATCH 3/4] dt-bindings: clock: Introduce RPMHCC bindings for SDX55 Manivannan Sadhasivam @ 2020-11-03 17:38 ` Bjorn Andersson 0 siblings, 0 replies; 16+ messages in thread From: Bjorn Andersson @ 2020-11-03 17:38 UTC (permalink / raw) To: Manivannan Sadhasivam Cc: sboyd, mturquette, robh+dt, vkoul, linux-arm-msm, linux-clk, devicetree, linux-kernel On Wed 28 Oct 02:42 CDT 2020, Manivannan Sadhasivam wrote: > From: Vinod Koul <vkoul@kernel.org> > > Add compatible for SDX55 RPMHCC and DT include. > > Signed-off-by: Vinod Koul <vkoul@kernel.org> Given that you handled the patch on its way here you should add your Signed-off-by. When doing so feel free to add my: Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Regards, Bjorn > --- > Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 + > include/dt-bindings/clock/qcom,rpmh.h | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml > index a46a3a799a70..a54930f111ba 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml > @@ -19,6 +19,7 @@ properties: > enum: > - qcom,sc7180-rpmh-clk > - qcom,sdm845-rpmh-clk > + - qcom,sdx55-rpmh-clk > - qcom,sm8150-rpmh-clk > - qcom,sm8250-rpmh-clk > > diff --git a/include/dt-bindings/clock/qcom,rpmh.h b/include/dt-bindings/clock/qcom,rpmh.h > index 2e6c54e65455..cd806eccb7dd 100644 > --- a/include/dt-bindings/clock/qcom,rpmh.h > +++ b/include/dt-bindings/clock/qcom,rpmh.h > @@ -21,5 +21,6 @@ > #define RPMH_IPA_CLK 12 > #define RPMH_LN_BB_CLK1 13 > #define RPMH_LN_BB_CLK1_A 14 > +#define RPMH_QPIC_CLK 15 > > #endif > -- > 2.17.1 > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 4/4] clk: qcom: Add support for SDX55 RPMh clocks 2020-10-28 7:42 [PATCH 0/4] Add GCC and RPMh clock support for SDX55 Manivannan Sadhasivam ` (2 preceding siblings ...) 2020-10-28 7:42 ` [PATCH 3/4] dt-bindings: clock: Introduce RPMHCC bindings for SDX55 Manivannan Sadhasivam @ 2020-10-28 7:42 ` Manivannan Sadhasivam 2020-11-03 17:53 ` Bjorn Andersson 2020-11-05 2:25 ` Stephen Boyd 2020-10-28 17:08 ` [PATCH 0/4] Add GCC and RPMh clock support for SDX55 Manivannan Sadhasivam 4 siblings, 2 replies; 16+ messages in thread From: Manivannan Sadhasivam @ 2020-10-28 7:42 UTC (permalink / raw) To: sboyd, mturquette, robh+dt Cc: bjorn.andersson, vkoul, linux-arm-msm, linux-clk, devicetree, linux-kernel, Manivannan Sadhasivam Add support for clocks maintained by RPMh in SDX55 SoCs. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- drivers/clk/qcom/clk-rpmh.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c index e2c669b08aff..88d010178b59 100644 --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c @@ -432,6 +432,25 @@ static const struct clk_rpmh_desc clk_rpmh_sm8250 = { .num_clks = ARRAY_SIZE(sm8250_rpmh_clocks), }; +DEFINE_CLK_RPMH_VRM(sdx55, rf_clk1, rf_clk1_ao, "rfclkd1", 1); +DEFINE_CLK_RPMH_VRM(sdx55, rf_clk2, rf_clk2_ao, "rfclkd2", 1); +DEFINE_CLK_RPMH_BCM(sdx55, qpic_clk, "QP0"); + +static struct clk_hw *sdx55_rpmh_clocks[] = { + [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, + [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, + [RPMH_RF_CLK1] = &sdx55_rf_clk1.hw, + [RPMH_RF_CLK1_A] = &sdx55_rf_clk1_ao.hw, + [RPMH_RF_CLK2] = &sdx55_rf_clk2.hw, + [RPMH_RF_CLK2_A] = &sdx55_rf_clk2_ao.hw, + [RPMH_QPIC_CLK] = &sdx55_qpic_clk.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_sdx55 = { + .clks = sdx55_rpmh_clocks, + .num_clks = ARRAY_SIZE(sdx55_rpmh_clocks), +}; + static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, void *data) { @@ -519,6 +538,7 @@ static const struct of_device_id clk_rpmh_match_table[] = { { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845}, { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150}, { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250}, + { .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55}, { } }; MODULE_DEVICE_TABLE(of, clk_rpmh_match_table); -- 2.17.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 4/4] clk: qcom: Add support for SDX55 RPMh clocks 2020-10-28 7:42 ` [PATCH 4/4] clk: qcom: Add support for SDX55 RPMh clocks Manivannan Sadhasivam @ 2020-11-03 17:53 ` Bjorn Andersson 2020-11-05 2:25 ` Stephen Boyd 1 sibling, 0 replies; 16+ messages in thread From: Bjorn Andersson @ 2020-11-03 17:53 UTC (permalink / raw) To: Manivannan Sadhasivam Cc: sboyd, mturquette, robh+dt, vkoul, linux-arm-msm, linux-clk, devicetree, linux-kernel On Wed 28 Oct 02:42 CDT 2020, Manivannan Sadhasivam wrote: > Add support for clocks maintained by RPMh in SDX55 SoCs. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > drivers/clk/qcom/clk-rpmh.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c > index e2c669b08aff..88d010178b59 100644 > --- a/drivers/clk/qcom/clk-rpmh.c > +++ b/drivers/clk/qcom/clk-rpmh.c > @@ -432,6 +432,25 @@ static const struct clk_rpmh_desc clk_rpmh_sm8250 = { > .num_clks = ARRAY_SIZE(sm8250_rpmh_clocks), > }; > > +DEFINE_CLK_RPMH_VRM(sdx55, rf_clk1, rf_clk1_ao, "rfclkd1", 1); > +DEFINE_CLK_RPMH_VRM(sdx55, rf_clk2, rf_clk2_ao, "rfclkd2", 1); > +DEFINE_CLK_RPMH_BCM(sdx55, qpic_clk, "QP0"); > + > +static struct clk_hw *sdx55_rpmh_clocks[] = { > + [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, > + [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, > + [RPMH_RF_CLK1] = &sdx55_rf_clk1.hw, > + [RPMH_RF_CLK1_A] = &sdx55_rf_clk1_ao.hw, > + [RPMH_RF_CLK2] = &sdx55_rf_clk2.hw, > + [RPMH_RF_CLK2_A] = &sdx55_rf_clk2_ao.hw, > + [RPMH_QPIC_CLK] = &sdx55_qpic_clk.hw, > +}; > + > +static const struct clk_rpmh_desc clk_rpmh_sdx55 = { > + .clks = sdx55_rpmh_clocks, > + .num_clks = ARRAY_SIZE(sdx55_rpmh_clocks), > +}; > + > static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec, > void *data) > { > @@ -519,6 +538,7 @@ static const struct of_device_id clk_rpmh_match_table[] = { > { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845}, > { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150}, > { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250}, > + { .compatible = "qcom,sdx55-rpmh-clk", .data = &clk_rpmh_sdx55}, The sort order is off here. Regards, Bjorn > { } > }; > MODULE_DEVICE_TABLE(of, clk_rpmh_match_table); > -- > 2.17.1 > ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 4/4] clk: qcom: Add support for SDX55 RPMh clocks 2020-10-28 7:42 ` [PATCH 4/4] clk: qcom: Add support for SDX55 RPMh clocks Manivannan Sadhasivam 2020-11-03 17:53 ` Bjorn Andersson @ 2020-11-05 2:25 ` Stephen Boyd 1 sibling, 0 replies; 16+ messages in thread From: Stephen Boyd @ 2020-11-05 2:25 UTC (permalink / raw) To: Manivannan Sadhasivam, mturquette, robh+dt Cc: bjorn.andersson, vkoul, linux-arm-msm, linux-clk, devicetree, linux-kernel, Manivannan Sadhasivam Quoting Manivannan Sadhasivam (2020-10-28 00:42:32) > Add support for clocks maintained by RPMh in SDX55 SoCs. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> > --- > drivers/clk/qcom/clk-rpmh.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c > index e2c669b08aff..88d010178b59 100644 > --- a/drivers/clk/qcom/clk-rpmh.c > +++ b/drivers/clk/qcom/clk-rpmh.c > @@ -432,6 +432,25 @@ static const struct clk_rpmh_desc clk_rpmh_sm8250 = { > .num_clks = ARRAY_SIZE(sm8250_rpmh_clocks), > }; > > +DEFINE_CLK_RPMH_VRM(sdx55, rf_clk1, rf_clk1_ao, "rfclkd1", 1); > +DEFINE_CLK_RPMH_VRM(sdx55, rf_clk2, rf_clk2_ao, "rfclkd2", 1); > +DEFINE_CLK_RPMH_BCM(sdx55, qpic_clk, "QP0"); > + > +static struct clk_hw *sdx55_rpmh_clocks[] = { > + [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw, > + [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw, > + [RPMH_RF_CLK1] = &sdx55_rf_clk1.hw, > + [RPMH_RF_CLK1_A] = &sdx55_rf_clk1_ao.hw, > + [RPMH_RF_CLK2] = &sdx55_rf_clk2.hw, > + [RPMH_RF_CLK2_A] = &sdx55_rf_clk2_ao.hw, > + [RPMH_QPIC_CLK] = &sdx55_qpic_clk.hw, What is QPIC? Some PMIC clk? Please mention it in the commit text. > +}; ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 0/4] Add GCC and RPMh clock support for SDX55 2020-10-28 7:42 [PATCH 0/4] Add GCC and RPMh clock support for SDX55 Manivannan Sadhasivam ` (3 preceding siblings ...) 2020-10-28 7:42 ` [PATCH 4/4] clk: qcom: Add support for SDX55 RPMh clocks Manivannan Sadhasivam @ 2020-10-28 17:08 ` Manivannan Sadhasivam 2020-11-03 17:34 ` Bjorn Andersson 4 siblings, 1 reply; 16+ messages in thread From: Manivannan Sadhasivam @ 2020-10-28 17:08 UTC (permalink / raw) To: bjorn.andersson Cc: sboyd, mturquette, robh+dt, vkoul, linux-arm-msm, linux-clk, devicetree, linux-kernel On Wed, Oct 28, 2020 at 01:12:28PM +0530, Manivannan Sadhasivam wrote: > Hello, > > This series adds Global Clock Controller (GCC) and RPMh clock support > for SDX55 SoC from Qualcomm with relevant DT bindings. > > This series has been tested on SDX55 MTP board. The dts patches for this > SoC/board will be posted later. > > Thanks, > Mani > > Manivannan Sadhasivam (1): > clk: qcom: Add support for SDX55 RPMh clocks > > Naveen Yadav (1): > clk: qcom: Add SDX55 GCC support Bjorn, I've inherited the gcc driver from downstream and did some modification. But I'm not sure if I can take the authorship of this patch hence kept it to the downstream author. In my point of view, the downstream author wrote the driver so I should keep the copyright and even list them as MODULE_AUTHOR. But I don't think I should give the patch authorship to them because I haven't received the patch anyhow. I usually keep the authorship if I take the patch from a source like LKML and repost it. But in this case, I authored the patch using someone's code! What is your view on this? Thanks, Mani > > Vinod Koul (2): > dt-bindings: clock: Add SDX55 GCC clock bindings > dt-bindings: clock: Introduce RPMHCC bindings for SDX55 > > .../bindings/clock/qcom,gcc-sdx55.yaml | 71 + > .../bindings/clock/qcom,rpmhcc.yaml | 1 + > drivers/clk/qcom/Kconfig | 8 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/clk-rpmh.c | 20 + > drivers/clk/qcom/gcc-sdx55.c | 1667 +++++++++++++++++ > include/dt-bindings/clock/qcom,gcc-sdx55.h | 112 ++ > include/dt-bindings/clock/qcom,rpmh.h | 1 + > 8 files changed, 1881 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml > create mode 100644 drivers/clk/qcom/gcc-sdx55.c > create mode 100644 include/dt-bindings/clock/qcom,gcc-sdx55.h > > -- > 2.17.1 > ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 0/4] Add GCC and RPMh clock support for SDX55 2020-10-28 17:08 ` [PATCH 0/4] Add GCC and RPMh clock support for SDX55 Manivannan Sadhasivam @ 2020-11-03 17:34 ` Bjorn Andersson 0 siblings, 0 replies; 16+ messages in thread From: Bjorn Andersson @ 2020-11-03 17:34 UTC (permalink / raw) To: Manivannan Sadhasivam Cc: sboyd, mturquette, robh+dt, vkoul, linux-arm-msm, linux-clk, devicetree, linux-kernel On Wed 28 Oct 12:08 CDT 2020, Manivannan Sadhasivam wrote: > On Wed, Oct 28, 2020 at 01:12:28PM +0530, Manivannan Sadhasivam wrote: > > Hello, > > > > This series adds Global Clock Controller (GCC) and RPMh clock support > > for SDX55 SoC from Qualcomm with relevant DT bindings. > > > > This series has been tested on SDX55 MTP board. The dts patches for this > > SoC/board will be posted later. > > > > Thanks, > > Mani > > > > Manivannan Sadhasivam (1): > > clk: qcom: Add support for SDX55 RPMh clocks > > > > Naveen Yadav (1): > > clk: qcom: Add SDX55 GCC support > > Bjorn, I've inherited the gcc driver from downstream and did some modification. > But I'm not sure if I can take the authorship of this patch hence kept it to the > downstream author. > > In my point of view, the downstream author wrote the driver so I should keep > the copyright and even list them as MODULE_AUTHOR. But I don't think I should > give the patch authorship to them because I haven't received the patch anyhow. > I usually keep the authorship if I take the patch from a source like LKML and > repost it. But in this case, I authored the patch using someone's code! > > What is your view on this? > I think the author should be the person whom prepared the patch. Given that the downstream driver is a series of patches from a single author it's not unreasonable to squash those and retain the author. But if your effort to prepare the patch for upstream was non-trivial I would consider it reasonable for you to claim authorship of the patch. If this is the case it's definitely preferable to give credit to the original author(s) by mentioning them in the commit message (e.g. "Based on downstream implementation by Jane Doe"). And the copyright for the work definitely needs to come along, possibly with the addition of yours, depending on your modifications. Thanks, Bjorn > Thanks, > Mani > > > > > Vinod Koul (2): > > dt-bindings: clock: Add SDX55 GCC clock bindings > > dt-bindings: clock: Introduce RPMHCC bindings for SDX55 > > > > .../bindings/clock/qcom,gcc-sdx55.yaml | 71 + > > .../bindings/clock/qcom,rpmhcc.yaml | 1 + > > drivers/clk/qcom/Kconfig | 8 + > > drivers/clk/qcom/Makefile | 1 + > > drivers/clk/qcom/clk-rpmh.c | 20 + > > drivers/clk/qcom/gcc-sdx55.c | 1667 +++++++++++++++++ > > include/dt-bindings/clock/qcom,gcc-sdx55.h | 112 ++ > > include/dt-bindings/clock/qcom,rpmh.h | 1 + > > 8 files changed, 1881 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml > > create mode 100644 drivers/clk/qcom/gcc-sdx55.c > > create mode 100644 include/dt-bindings/clock/qcom,gcc-sdx55.h > > > > -- > > 2.17.1 > > ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2020-11-13 7:58 UTC | newest] Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-10-28 7:42 [PATCH 0/4] Add GCC and RPMh clock support for SDX55 Manivannan Sadhasivam 2020-10-28 7:42 ` [PATCH 1/4] dt-bindings: clock: Add SDX55 GCC clock bindings Manivannan Sadhasivam 2020-10-30 19:22 ` Rob Herring 2020-10-31 3:29 ` Manivannan Sadhasivam 2020-11-05 2:03 ` Stephen Boyd 2020-10-28 7:42 ` [PATCH 2/4] clk: qcom: Add SDX55 GCC support Manivannan Sadhasivam 2020-11-05 2:23 ` Stephen Boyd 2020-11-05 8:51 ` Manivannan Sadhasivam 2020-11-13 7:58 ` Stephen Boyd 2020-10-28 7:42 ` [PATCH 3/4] dt-bindings: clock: Introduce RPMHCC bindings for SDX55 Manivannan Sadhasivam 2020-11-03 17:38 ` Bjorn Andersson 2020-10-28 7:42 ` [PATCH 4/4] clk: qcom: Add support for SDX55 RPMh clocks Manivannan Sadhasivam 2020-11-03 17:53 ` Bjorn Andersson 2020-11-05 2:25 ` Stephen Boyd 2020-10-28 17:08 ` [PATCH 0/4] Add GCC and RPMh clock support for SDX55 Manivannan Sadhasivam 2020-11-03 17:34 ` Bjorn Andersson
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