From: Bjorn Andersson <bjorn.andersson@linaro.org>
To: Douglas Anderson <dianders@chromium.org>
Cc: Andrzej Hajda <a.hajda@samsung.com>,
Neil Armstrong <narmstrong@baylibre.com>,
robdclark@chromium.org, linux-arm-msm@vger.kernel.org,
seanpaul@chromium.org, Jeffrey Hugo <jeffrey.l.hugo@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>, Rob Clark <robdclark@gmail.com>,
Jonas Karlman <jonas@kwiboo.se>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
David Airlie <airlied@linux.ie>,
Jernej Skrabec <jernej.skrabec@siol.net>,
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Subject: Re: [PATCH v3 3/9] drm/bridge: ti-sn65dsi86: Don't use MIPI variables for DP link
Date: Mon, 3 Feb 2020 15:33:11 -0800 [thread overview]
Message-ID: <20200203233311.GC311651@builder> (raw)
In-Reply-To: <20191218143416.v3.3.Ia6e05f4961adb0d4a0d32ba769dd7781ee8db431@changeid>
On Wed 18 Dec 14:35 PST 2019, Douglas Anderson wrote:
> The ti-sn65dsi86 is a bridge from MIPI to DP and thus has two links:
> the MIPI link and the DP link. The two links do not need to have the
> same format or number of lanes. Stop using MIPI variables when
> talking about the DP link.
>
> This has zero functional change because:
> * currently we are hardcoding the MIPI link as unpacked RGB888 which
> requires 24 bits and currently we are not changing the DP link rate
> from the bridge's default of 8 bits per pixel.
> * currently we are hardcoding both the MIPI and DP as being 4 lanes.
>
> This is all in prep for fixing some of the above.
>
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> Tested-by: Rob Clark <robdclark@gmail.com>
> Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> drivers/gpu/drm/bridge/ti-sn65dsi86.c | 18 ++++++++++++------
> 1 file changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> index 7b596af265e4..ab644baaf90c 100644
> --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> @@ -100,6 +100,7 @@ struct ti_sn_bridge {
> struct drm_panel *panel;
> struct gpio_desc *enable_gpio;
> struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM];
> + int dp_lanes;
> };
>
> static const struct regmap_range ti_sn_bridge_volatile_ranges[] = {
> @@ -313,6 +314,7 @@ static int ti_sn_bridge_attach(struct drm_bridge *bridge)
> }
>
> /* TODO: setting to 4 lanes always for now */
> + pdata->dp_lanes = 4;
> dsi->lanes = 4;
> dsi->format = MIPI_DSI_FMT_RGB888;
> dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
> @@ -451,13 +453,17 @@ static void ti_sn_bridge_set_dp_rate(struct ti_sn_bridge *pdata)
> struct drm_display_mode *mode =
> &pdata->bridge.encoder->crtc->state->adjusted_mode;
>
> - /* set DSIA clk frequency */
> - bit_rate_mhz = (mode->clock / 1000) *
> - mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
> + /*
> + * Calculate minimum bit rate based on our pixel clock. At
> + * the moment this driver never sets the DP_18BPP_EN bit in
> + * register 0x5b so we hardcode 24bpp.
> + */
> + bit_rate_mhz = (mode->clock / 1000) * 24;
>
> - /* set DP data rate */
> - dp_rate_mhz = ((bit_rate_mhz / pdata->dsi->lanes) * DP_CLK_FUDGE_NUM) /
> + /* Calculate minimum DP data rate, taking 80% as per DP spec */
> + dp_rate_mhz = ((bit_rate_mhz / pdata->dp_lanes) * DP_CLK_FUDGE_NUM) /
> DP_CLK_FUDGE_DEN;
> +
> for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
> if (ti_sn_bridge_dp_rate_lut[i] > dp_rate_mhz)
> break;
> @@ -517,7 +523,7 @@ static void ti_sn_bridge_enable(struct drm_bridge *bridge)
> CHA_DSI_LANES_MASK, val);
>
> /* DP lane config */
> - val = DP_NUM_LANES(pdata->dsi->lanes - 1);
> + val = DP_NUM_LANES(pdata->dp_lanes - 1);
> regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
> val);
>
> --
> 2.24.1.735.g03f4e72817-goog
>
next prev parent reply other threads:[~2020-02-03 23:33 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-18 22:35 [PATCH v3 0/9] drm/bridge: ti-sn65dsi86: Improve support for AUO B116XAK01 + other DP Douglas Anderson
2019-12-18 22:35 ` [PATCH v3 1/9] drm/bridge: ti-sn65dsi86: Split the setting of the dp and dsi rates Douglas Anderson
2020-02-03 23:31 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 2/9] drm/bridge: ti-sn65dsi86: zero is never greater than an unsigned int Douglas Anderson
2020-02-03 23:32 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 3/9] drm/bridge: ti-sn65dsi86: Don't use MIPI variables for DP link Douglas Anderson
2020-02-03 23:33 ` Bjorn Andersson [this message]
2019-12-18 22:35 ` [PATCH v3 4/9] drm/bridge: ti-sn65dsi86: Config number of DP lanes Mo' Betta Douglas Anderson
2020-02-03 23:34 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 5/9] drm/bridge: ti-sn65dsi86: Read num lanes from the DP sink Douglas Anderson
2020-02-03 23:35 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 6/9] drm/bridge: ti-sn65dsi86: Use 18-bit DP if we can Douglas Anderson
2020-02-03 23:37 ` Bjorn Andersson
2020-02-04 0:21 ` Doug Anderson
2020-02-12 23:04 ` Doug Anderson
2020-02-13 9:17 ` Neil Armstrong
[not found] ` <20200710011935.GA7056@gentoo.org>
2020-07-10 1:38 ` Doug Anderson
2020-07-10 2:14 ` Doug Anderson
2020-07-10 3:12 ` Steev Klimaszewski
2020-07-10 3:17 ` Steev Klimaszewski
2020-07-10 3:43 ` Steev Klimaszewski
2020-07-10 4:12 ` Doug Anderson
2020-07-10 6:15 ` Steev Klimaszewski
2020-07-10 14:16 ` Rob Clark
2020-07-10 14:47 ` Doug Anderson
2020-07-10 17:10 ` Steev Klimaszewski
2020-07-14 15:31 ` Doug Anderson
2020-09-02 14:37 ` Doug Anderson
2019-12-18 22:35 ` [PATCH v3 7/9] drm/bridge: ti-sn65dsi86: Group DP link training bits in a function Douglas Anderson
2020-02-03 23:39 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 8/9] drm/bridge: ti-sn65dsi86: Train at faster rates if slower ones fail Douglas Anderson
2020-02-03 23:41 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 9/9] drm/bridge: ti-sn65dsi86: Avoid invalid rates Douglas Anderson
2020-02-03 23:43 ` Bjorn Andersson
2020-01-06 22:47 ` [PATCH v3 0/9] drm/bridge: ti-sn65dsi86: Improve support for AUO B116XAK01 + other DP Doug Anderson
2020-02-03 23:45 ` Bjorn Andersson
2020-02-13 9:51 ` Neil Armstrong
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