From: Steev Klimaszewski <steev@kali.org>
To: Doug Anderson <dianders@chromium.org>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
Andrzej Hajda <a.hajda@samsung.com>,
David Airlie <airlied@linux.ie>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Daniel Vetter <daniel@ffwll.ch>,
dri-devel <dri-devel@lists.freedesktop.org>,
Jeffrey Hugo <jeffrey.l.hugo@gmail.com>,
Jernej Skrabec <jernej.skrabec@siol.net>,
Jonas Karlman <jonas@kwiboo.se>,
linux-arm-msm <linux-arm-msm@vger.kernel.org>,
LKML <linux-kernel@vger.kernel.org>,
Neil Armstrong <narmstrong@baylibre.com>,
Rob Clark <robdclark@chromium.org>,
Rob Clark <robdclark@gmail.com>,
Sean Paul <seanpaul@chromium.org>,
Steev Klimaszewski <steev@gentoo.org>
Subject: Re: [PATCH v3 6/9] drm/bridge: ti-sn65dsi86: Use 18-bit DP if we can
Date: Thu, 9 Jul 2020 22:17:14 -0500 [thread overview]
Message-ID: <e0702671-3bed-9e3d-c7f4-d050c617eb65@kali.org> (raw)
In-Reply-To: <dc786abb-4bc2-2416-7ee5-de408aceb8f1@kali.org>
On 7/9/20 10:12 PM, Steev Klimaszewski wrote:
>
> On 7/9/20 9:14 PM, Doug Anderson wrote:
>> Hi,
>>
>> On Thu, Jul 9, 2020 at 6:38 PM Doug Anderson <dianders@chromium.org>
>> wrote:
>>> Hi,
>>>
>>> On Thu, Jul 9, 2020 at 6:19 PM Steev Klimaszewski <steev@gentoo.org>
>>> wrote:
>>>> Hi Doug,
>>>>
>>>> I've been testing 5.8 and linux-next on the Lenovo Yoga C630, and
>>>> with this patch applied, there is really bad banding on the display.
>>>>
>>>> I'm really bad at explaining it, but you can see the differences in
>>>> the following:
>>>>
>>>> 24bit (pre-5.8) - https://dev.gentoo.org/~steev/files/image0.jpg
>>>>
>>>> 18bit (5.8/linux-next) -
>>>> https://dev.gentoo.org/~steev/files/image1.jpg
>>> Presumably this means that your panel is defined improperly? If the
>>> panel reports that it's a 6 bits per pixel panel but it's actually an
>>> 8 bits per pixel panel then you'll run into this problem.
>>>
>>> I would have to assume you have a bunch of out of tree patches to
>>> support your hardware since I don't see any device trees in linuxnext
>>> (other than cheza) that use this bridge chip. Otherwise I could try
>>> to check and confirm that was the problem.
>> Ah, interesting. Maybe you have the panel:
>>
>> boe,nv133fhm-n61
>>
>> As far as I can tell from the datasheet (I have the similar
>> boe,nv133fhm-n62) this is a 6bpp panel. ...but if you feed it 8bpp
>> the banding goes away! Maybe the panel itself knows how to dither???
>> ...or maybe the datasheet / edid are wrong and this is actually an
>> 8bpp panel. Seems unlikely...
>>
>> In any case, one fix is to pick
>> <https://lore.kernel.org/dri-devel/1593087419-903-1-git-send-email-kalyan_t@codeaurora.org/>,
>>
>> though right now that patch is only enabled for sc7180. Maybe you
>> could figure out how to apply it to your hardware?
>>
>> ...another fix would be to pretend that your panel is 8bpp even though
>> it's actually 6bpp. Ironically if anyone ever tried to configure BPP
>> from the EDID they'd go back to 6bpp. You can read the EDID of your
>> panel with this:
>>
>> bus=$(i2cdetect -l | grep sn65 | sed 's/i2c-\([0-9]*\).*$/\1/')
>> i2cdump ${bus} 0x50 i
>>
>> When I do that and then decode it on the "boe,nv133fhm-n62" panel, I
>> find:
>>
>> 6 bits per primary color channel
>>
>> -Doug
>
>
> Hi Doug,
>
> Decoding it does show be to boe,nv133fhm-n61 - and yeah it does say
> it's 6-bit according to panelook's specs for it.
>
>
> I'll take a look at the patch and see what I can come up with... at
> the moment, I'm forcing it to be 8bit and that does "work fine" but
> I'd like it to be fixed properly instead of my hack.
>
> Thanks for your time and work!
>
> -- Steev
>
For what it's worth - the 5.8 that I'm testing is at
https://github.com/steev/linux/commits/c630-5.8-rc4-inline-encryption
next prev parent reply other threads:[~2020-07-10 3:17 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-18 22:35 [PATCH v3 0/9] drm/bridge: ti-sn65dsi86: Improve support for AUO B116XAK01 + other DP Douglas Anderson
2019-12-18 22:35 ` [PATCH v3 1/9] drm/bridge: ti-sn65dsi86: Split the setting of the dp and dsi rates Douglas Anderson
2020-02-03 23:31 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 2/9] drm/bridge: ti-sn65dsi86: zero is never greater than an unsigned int Douglas Anderson
2020-02-03 23:32 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 3/9] drm/bridge: ti-sn65dsi86: Don't use MIPI variables for DP link Douglas Anderson
2020-02-03 23:33 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 4/9] drm/bridge: ti-sn65dsi86: Config number of DP lanes Mo' Betta Douglas Anderson
2020-02-03 23:34 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 5/9] drm/bridge: ti-sn65dsi86: Read num lanes from the DP sink Douglas Anderson
2020-02-03 23:35 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 6/9] drm/bridge: ti-sn65dsi86: Use 18-bit DP if we can Douglas Anderson
2020-02-03 23:37 ` Bjorn Andersson
2020-02-04 0:21 ` Doug Anderson
2020-02-12 23:04 ` Doug Anderson
2020-02-13 9:17 ` Neil Armstrong
[not found] ` <20200710011935.GA7056@gentoo.org>
2020-07-10 1:38 ` Doug Anderson
2020-07-10 2:14 ` Doug Anderson
2020-07-10 3:12 ` Steev Klimaszewski
2020-07-10 3:17 ` Steev Klimaszewski [this message]
2020-07-10 3:43 ` Steev Klimaszewski
2020-07-10 4:12 ` Doug Anderson
2020-07-10 6:15 ` Steev Klimaszewski
2020-07-10 14:16 ` Rob Clark
2020-07-10 14:47 ` Doug Anderson
2020-07-10 17:10 ` Steev Klimaszewski
2020-07-14 15:31 ` Doug Anderson
2020-09-02 14:37 ` Doug Anderson
2019-12-18 22:35 ` [PATCH v3 7/9] drm/bridge: ti-sn65dsi86: Group DP link training bits in a function Douglas Anderson
2020-02-03 23:39 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 8/9] drm/bridge: ti-sn65dsi86: Train at faster rates if slower ones fail Douglas Anderson
2020-02-03 23:41 ` Bjorn Andersson
2019-12-18 22:35 ` [PATCH v3 9/9] drm/bridge: ti-sn65dsi86: Avoid invalid rates Douglas Anderson
2020-02-03 23:43 ` Bjorn Andersson
2020-01-06 22:47 ` [PATCH v3 0/9] drm/bridge: ti-sn65dsi86: Improve support for AUO B116XAK01 + other DP Doug Anderson
2020-02-03 23:45 ` Bjorn Andersson
2020-02-13 9:51 ` Neil Armstrong
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