* [PATCH v4 0/2] Enable SS/HS USB support on SM8150 @ 2020-04-11 0:52 Wesley Cheng 2020-04-11 0:52 ` [PATCH v4 1/2] clk: qcom: gcc: Add USB3 PIPE clock and GDSC for SM8150 Wesley Cheng 2020-04-11 0:52 ` [PATCH v4 2/2] arm64: dts: qcom: sm8150: Add USB and PHY device nodes Wesley Cheng 0 siblings, 2 replies; 6+ messages in thread From: Wesley Cheng @ 2020-04-11 0:52 UTC (permalink / raw) To: agross, bjorn.andersson, mturquette, sboyd, robh+dt, mark.rutland Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, vinod.koul, Wesley Cheng Add required device tree nodes to enable the USB SS and HS paths on the primary USB controller on SM8150. In addition, implement missing resources from the SM8150 GCC driver, which includes the USB GDSC and the USB PIPE clocks. Changes in v4: - Re-ordered compatible cells for usb_1_hsphy and usb_1 to select by the platform first. Changes in v3: - Set dr_mode to "peripheral" on the SM8150 MTP DTSI file. Tested-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Changes in v2: - Combine GDSC and USB PIPE clock changes. - Re-order DTS nodes based on address Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Jack Pham (1): arm64: dts: qcom: sm8150: Add USB and PHY device nodes Wesley Cheng (1): clk: qcom: gcc: Add USB3 PIPE clock and GDSC for SM8150 arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 21 +++++++ arch/arm64/boot/dts/qcom/sm8150.dtsi | 92 +++++++++++++++++++++++++++++ drivers/clk/qcom/gcc-sm8150.c | 52 ++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sm8150.h | 4 ++ 4 files changed, 169 insertions(+) -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v4 1/2] clk: qcom: gcc: Add USB3 PIPE clock and GDSC for SM8150 2020-04-11 0:52 [PATCH v4 0/2] Enable SS/HS USB support on SM8150 Wesley Cheng @ 2020-04-11 0:52 ` Wesley Cheng 2020-04-11 1:01 ` Bjorn Andersson 2020-04-11 0:52 ` [PATCH v4 2/2] arm64: dts: qcom: sm8150: Add USB and PHY device nodes Wesley Cheng 1 sibling, 1 reply; 6+ messages in thread From: Wesley Cheng @ 2020-04-11 0:52 UTC (permalink / raw) To: agross, bjorn.andersson, mturquette, sboyd, robh+dt, mark.rutland Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, vinod.koul, Wesley Cheng This adds the USB3 PIPE clock and GDSC structures, so that the USB driver can vote for these resources to be enabled/disabled when required. Both are needed for SS and HS USB paths to operate properly. The GDSC will allow the USB system to be brought out of reset, while the PIPE clock is needed for data transactions between the PHY and controller. Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> --- drivers/clk/qcom/gcc-sm8150.c | 52 +++++++++++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sm8150.h | 4 +++ 2 files changed, 56 insertions(+) diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c index 2087721..ef98fdc 100644 --- a/drivers/clk/qcom/gcc-sm8150.c +++ b/drivers/clk/qcom/gcc-sm8150.c @@ -21,6 +21,7 @@ #include "clk-rcg.h" #include "clk-regmap.h" #include "reset.h" +#include "gdsc.h" enum { P_BI_TCXO, @@ -3171,6 +3172,18 @@ enum { }, }; +static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0xf058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_prim_phy_pipe_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_usb3_sec_clkref_clk = { .halt_reg = 0x8c028, .halt_check = BRANCH_HALT, @@ -3218,6 +3231,18 @@ enum { }, }; +static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x10058, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_sec_phy_pipe_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + /* * Clock ON depends on external parent 'config noc', so cant poll * delay and also mark as crtitical for video boot @@ -3292,6 +3317,24 @@ enum { }, }; +static struct gdsc usb30_prim_gdsc = { + .gdscr = 0xf004, + .pd = { + .name = "usb30_prim_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR, +}; + +static struct gdsc usb30_sec_gdsc = { + .gdscr = 0x10004, + .pd = { + .name = "usb30_sec_gdsc", + }, + .pwrsts = PWRSTS_OFF_ON, + .flags = POLL_CFG_GDSCR, +}; + static struct clk_regmap *gcc_sm8150_clocks[] = { [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, @@ -3480,10 +3523,12 @@ enum { [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, + [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr, [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, + [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, @@ -3527,6 +3572,11 @@ enum { [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, }; +static struct gdsc *gcc_sm8150_gdscs[] = { + [USB30_PRIM_GDSC] = &usb30_prim_gdsc, + [USB30_SEC_GDSC] = &usb30_sec_gdsc, +}; + static const struct regmap_config gcc_sm8150_regmap_config = { .reg_bits = 32, .reg_stride = 4, @@ -3541,6 +3591,8 @@ enum { .num_clks = ARRAY_SIZE(gcc_sm8150_clocks), .resets = gcc_sm8150_resets, .num_resets = ARRAY_SIZE(gcc_sm8150_resets), + .gdscs = gcc_sm8150_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_sm8150_gdscs), }; static const struct of_device_id gcc_sm8150_match_table[] = { diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h index 90d60ef..3e1a918 100644 --- a/include/dt-bindings/clock/qcom,gcc-sm8150.h +++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h @@ -240,4 +240,8 @@ #define GCC_USB30_SEC_BCR 27 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 28 +/* GCC GDSCRs */ +#define USB30_PRIM_GDSC 4 +#define USB30_SEC_GDSC 5 + #endif -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v4 1/2] clk: qcom: gcc: Add USB3 PIPE clock and GDSC for SM8150 2020-04-11 0:52 ` [PATCH v4 1/2] clk: qcom: gcc: Add USB3 PIPE clock and GDSC for SM8150 Wesley Cheng @ 2020-04-11 1:01 ` Bjorn Andersson 2020-04-22 9:23 ` Stephen Boyd 0 siblings, 1 reply; 6+ messages in thread From: Bjorn Andersson @ 2020-04-11 1:01 UTC (permalink / raw) To: Wesley Cheng Cc: agross, mturquette, sboyd, robh+dt, mark.rutland, linux-arm-msm, linux-clk, linux-kernel, devicetree, vinod.koul On Fri 10 Apr 17:52 PDT 2020, Wesley Cheng wrote: > This adds the USB3 PIPE clock and GDSC structures, so > that the USB driver can vote for these resources to be > enabled/disabled when required. Both are needed for SS > and HS USB paths to operate properly. The GDSC will > allow the USB system to be brought out of reset, while > the PIPE clock is needed for data transactions between > the PHY and controller. > > Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> > Reviewed-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Stephen, let me know when you take this patch and I'll take the dts one. Regards, Bjorn > --- > drivers/clk/qcom/gcc-sm8150.c | 52 +++++++++++++++++++++++++++++ > include/dt-bindings/clock/qcom,gcc-sm8150.h | 4 +++ > 2 files changed, 56 insertions(+) > > diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c > index 2087721..ef98fdc 100644 > --- a/drivers/clk/qcom/gcc-sm8150.c > +++ b/drivers/clk/qcom/gcc-sm8150.c > @@ -21,6 +21,7 @@ > #include "clk-rcg.h" > #include "clk-regmap.h" > #include "reset.h" > +#include "gdsc.h" > > enum { > P_BI_TCXO, > @@ -3171,6 +3172,18 @@ enum { > }, > }; > > +static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { > + .halt_check = BRANCH_HALT_SKIP, > + .clkr = { > + .enable_reg = 0xf058, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_usb3_prim_phy_pipe_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > static struct clk_branch gcc_usb3_sec_clkref_clk = { > .halt_reg = 0x8c028, > .halt_check = BRANCH_HALT, > @@ -3218,6 +3231,18 @@ enum { > }, > }; > > +static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { > + .halt_check = BRANCH_HALT_SKIP, > + .clkr = { > + .enable_reg = 0x10058, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_usb3_sec_phy_pipe_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > /* > * Clock ON depends on external parent 'config noc', so cant poll > * delay and also mark as crtitical for video boot > @@ -3292,6 +3317,24 @@ enum { > }, > }; > > +static struct gdsc usb30_prim_gdsc = { > + .gdscr = 0xf004, > + .pd = { > + .name = "usb30_prim_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .flags = POLL_CFG_GDSCR, > +}; > + > +static struct gdsc usb30_sec_gdsc = { > + .gdscr = 0x10004, > + .pd = { > + .name = "usb30_sec_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .flags = POLL_CFG_GDSCR, > +}; > + > static struct clk_regmap *gcc_sm8150_clocks[] = { > [GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr, > [GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr, > @@ -3480,10 +3523,12 @@ enum { > [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, > [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, > [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, > + [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, > [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr, > [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, > [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, > [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, > + [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, > [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, > [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, > [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr, > @@ -3527,6 +3572,11 @@ enum { > [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 }, > }; > > +static struct gdsc *gcc_sm8150_gdscs[] = { > + [USB30_PRIM_GDSC] = &usb30_prim_gdsc, > + [USB30_SEC_GDSC] = &usb30_sec_gdsc, > +}; > + > static const struct regmap_config gcc_sm8150_regmap_config = { > .reg_bits = 32, > .reg_stride = 4, > @@ -3541,6 +3591,8 @@ enum { > .num_clks = ARRAY_SIZE(gcc_sm8150_clocks), > .resets = gcc_sm8150_resets, > .num_resets = ARRAY_SIZE(gcc_sm8150_resets), > + .gdscs = gcc_sm8150_gdscs, > + .num_gdscs = ARRAY_SIZE(gcc_sm8150_gdscs), > }; > > static const struct of_device_id gcc_sm8150_match_table[] = { > diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h > index 90d60ef..3e1a918 100644 > --- a/include/dt-bindings/clock/qcom,gcc-sm8150.h > +++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h > @@ -240,4 +240,8 @@ > #define GCC_USB30_SEC_BCR 27 > #define GCC_USB_PHY_CFG_AHB2PHY_BCR 28 > > +/* GCC GDSCRs */ > +#define USB30_PRIM_GDSC 4 > +#define USB30_SEC_GDSC 5 > + > #endif > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v4 1/2] clk: qcom: gcc: Add USB3 PIPE clock and GDSC for SM8150 2020-04-11 1:01 ` Bjorn Andersson @ 2020-04-22 9:23 ` Stephen Boyd 0 siblings, 0 replies; 6+ messages in thread From: Stephen Boyd @ 2020-04-22 9:23 UTC (permalink / raw) To: Bjorn Andersson, Wesley Cheng Cc: agross, mturquette, robh+dt, mark.rutland, linux-arm-msm, linux-clk, linux-kernel, devicetree, vinod.koul Quoting Bjorn Andersson (2020-04-10 18:01:43) > On Fri 10 Apr 17:52 PDT 2020, Wesley Cheng wrote: > > > This adds the USB3 PIPE clock and GDSC structures, so > > that the USB driver can vote for these resources to be > > enabled/disabled when required. Both are needed for SS > > and HS USB paths to operate properly. The GDSC will > > allow the USB system to be brought out of reset, while > > the PIPE clock is needed for data transactions between > > the PHY and controller. > > > > Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> > > Reviewed-by: Stephen Boyd <sboyd@kernel.org> > > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > > > Stephen, let me know when you take this patch and I'll take the dts one. > Looks like I already applied it and it's merged in Linus' tree. ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v4 2/2] arm64: dts: qcom: sm8150: Add USB and PHY device nodes 2020-04-11 0:52 [PATCH v4 0/2] Enable SS/HS USB support on SM8150 Wesley Cheng 2020-04-11 0:52 ` [PATCH v4 1/2] clk: qcom: gcc: Add USB3 PIPE clock and GDSC for SM8150 Wesley Cheng @ 2020-04-11 0:52 ` Wesley Cheng 2020-06-16 6:36 ` Vinod Koul 1 sibling, 1 reply; 6+ messages in thread From: Wesley Cheng @ 2020-04-11 0:52 UTC (permalink / raw) To: agross, bjorn.andersson, mturquette, sboyd, robh+dt, mark.rutland Cc: linux-arm-msm, linux-clk, linux-kernel, devicetree, vinod.koul, Jack Pham, Wesley Cheng From: Jack Pham <jackp@codeaurora.org> Add device nodes for the USB3 controller, QMP SS PHY and SNPS HS PHY. Signed-off-by: Jack Pham <jackp@codeaurora.org> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Tested-by: Vinod Koul <vinod.koul@linaro.org> --- arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 21 ++++++++ arch/arm64/boot/dts/qcom/sm8150.dtsi | 92 +++++++++++++++++++++++++++++++++ 2 files changed, 113 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts index 8ab1661..6c6325c 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts @@ -408,3 +408,24 @@ vdda-pll-supply = <&vreg_l3c_1p2>; vdda-pll-max-microamp = <19000>; }; + +&usb_1_hsphy { + status = "okay"; + vdda-pll-supply = <&vdd_usb_hs_core>; + vdda33-supply = <&vdda_usb_hs_3p1>; + vdda18-supply = <&vdda_usb_hs_1p8>; +}; + +&usb_1_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l3c_1p2>; + vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 141c21d..a36512d 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -621,6 +621,98 @@ }; }; + usb_1_hsphy: phy@88e2000 { + compatible = "qcom,sm8150-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e2000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + }; + + usb_1_qmpphy: phy@88e9000 { + compatible = "qcom,sm8150-qmp-usb3-phy"; + reg = <0 0x088e9000 0 0x18c>, + <0 0x088e8000 0 0x10>; + reg-names = "reg-base", "dp_com"; + status = "disabled"; + #clock-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux", "ref_clk_src", "ref", "com_aux"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + + usb_1_ssphy: lanes@88e9200 { + reg = <0 0x088e9200 0 0x200>, + <0 0x088e9400 0 0x200>, + <0 0x088e9c00 0 0x218>, + <0 0x088e9600 0 0x200>, + <0 0x088e9800 0 0x200>, + <0 0x088e9a00 0 0x100>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_phy_pipe_clk_src"; + }; + }; + + usb_1: usb@a6f8800 { + compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB3_SEC_CLKREF_CLK>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep", "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <150000000>; + + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + usb_1_dwc3: dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + aoss_qmp: power-controller@c300000 { compatible = "qcom,sm8150-aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x100000>; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v4 2/2] arm64: dts: qcom: sm8150: Add USB and PHY device nodes 2020-04-11 0:52 ` [PATCH v4 2/2] arm64: dts: qcom: sm8150: Add USB and PHY device nodes Wesley Cheng @ 2020-06-16 6:36 ` Vinod Koul 0 siblings, 0 replies; 6+ messages in thread From: Vinod Koul @ 2020-06-16 6:36 UTC (permalink / raw) To: Wesley Cheng, Bjorn Andersson Cc: agross, mturquette, sboyd, robh+dt, mark.rutland, linux-arm-msm, linux-clk, linux-kernel, devicetree, Jack Pham On 10-04-20, 17:52, Wesley Cheng wrote: > From: Jack Pham <jackp@codeaurora.org> > > Add device nodes for the USB3 controller, QMP SS PHY and > SNPS HS PHY. Bjorn, can you please review/pick this.. I dont see this in -rc1 > > Signed-off-by: Jack Pham <jackp@codeaurora.org> > Signed-off-by: Wesley Cheng <wcheng@codeaurora.org> > Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > Reviewed-by: Vinod Koul <vkoul@kernel.org> > Tested-by: Vinod Koul <vinod.koul@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8150-mtp.dts | 21 ++++++++ > arch/arm64/boot/dts/qcom/sm8150.dtsi | 92 +++++++++++++++++++++++++++++++++ > 2 files changed, 113 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts > index 8ab1661..6c6325c 100644 > --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts > +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts > @@ -408,3 +408,24 @@ > vdda-pll-supply = <&vreg_l3c_1p2>; > vdda-pll-max-microamp = <19000>; > }; > + > +&usb_1_hsphy { > + status = "okay"; > + vdda-pll-supply = <&vdd_usb_hs_core>; > + vdda33-supply = <&vdda_usb_hs_3p1>; > + vdda18-supply = <&vdda_usb_hs_1p8>; > +}; > + > +&usb_1_qmpphy { > + status = "okay"; > + vdda-phy-supply = <&vreg_l3c_1p2>; > + vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; > +}; > + > +&usb_1 { > + status = "okay"; > +}; > + > +&usb_1_dwc3 { > + dr_mode = "peripheral"; > +}; > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi > index 141c21d..a36512d 100644 > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi > @@ -621,6 +621,98 @@ > }; > }; > > + usb_1_hsphy: phy@88e2000 { > + compatible = "qcom,sm8150-usb-hs-phy", > + "qcom,usb-snps-hs-7nm-phy"; > + reg = <0 0x088e2000 0 0x400>; > + status = "disabled"; > + #phy-cells = <0>; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "ref"; > + > + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; > + }; > + > + usb_1_qmpphy: phy@88e9000 { > + compatible = "qcom,sm8150-qmp-usb3-phy"; > + reg = <0 0x088e9000 0 0x18c>, > + <0 0x088e8000 0 0x10>; > + reg-names = "reg-base", "dp_com"; > + status = "disabled"; > + #clock-cells = <1>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, > + <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, > + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; > + clock-names = "aux", "ref_clk_src", "ref", "com_aux"; > + > + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, > + <&gcc GCC_USB3_PHY_PRIM_BCR>; > + reset-names = "phy", "common"; > + > + usb_1_ssphy: lanes@88e9200 { > + reg = <0 0x088e9200 0 0x200>, > + <0 0x088e9400 0 0x200>, > + <0 0x088e9c00 0 0x218>, > + <0 0x088e9600 0 0x200>, > + <0 0x088e9800 0 0x200>, > + <0 0x088e9a00 0 0x100>; > + #phy-cells = <0>; > + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; > + clock-names = "pipe0"; > + clock-output-names = "usb3_phy_pipe_clk_src"; > + }; > + }; > + > + usb_1: usb@a6f8800 { > + compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; > + reg = <0 0x0a6f8800 0 0x400>; > + status = "disabled"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + dma-ranges; > + > + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>, > + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, > + <&gcc GCC_USB3_SEC_CLKREF_CLK>; > + clock-names = "cfg_noc", "core", "iface", "mock_utmi", > + "sleep", "xo"; > + > + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>; > + assigned-clock-rates = <19200000>, <150000000>; > + > + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hs_phy_irq", "ss_phy_irq", > + "dm_hs_phy_irq", "dp_hs_phy_irq"; > + > + power-domains = <&gcc USB30_PRIM_GDSC>; > + > + resets = <&gcc GCC_USB30_PRIM_BCR>; > + > + usb_1_dwc3: dwc3@a600000 { > + compatible = "snps,dwc3"; > + reg = <0 0x0a600000 0 0xcd00>; > + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; > + snps,dis_u2_susphy_quirk; > + snps,dis_enblslpm_quirk; > + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; > + phy-names = "usb2-phy", "usb3-phy"; > + }; > + }; > + > aoss_qmp: power-controller@c300000 { > compatible = "qcom,sm8150-aoss-qmp"; > reg = <0x0 0x0c300000 0x0 0x100000>; > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project -- ~Vinod ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-06-16 6:36 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-04-11 0:52 [PATCH v4 0/2] Enable SS/HS USB support on SM8150 Wesley Cheng 2020-04-11 0:52 ` [PATCH v4 1/2] clk: qcom: gcc: Add USB3 PIPE clock and GDSC for SM8150 Wesley Cheng 2020-04-11 1:01 ` Bjorn Andersson 2020-04-22 9:23 ` Stephen Boyd 2020-04-11 0:52 ` [PATCH v4 2/2] arm64: dts: qcom: sm8150: Add USB and PHY device nodes Wesley Cheng 2020-06-16 6:36 ` Vinod Koul
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