* [PATCH v10 1/4] dt-bindings: mtd: Convert Qcom NANDc binding to YAML
2021-04-01 15:19 [PATCH v10 0/4] Add support for secure regions in NAND Manivannan Sadhasivam
@ 2021-04-01 15:19 ` Manivannan Sadhasivam
2021-04-01 15:19 ` [PATCH v10 2/4] dt-bindings: mtd: Add a property to declare secure regions in NAND chips Manivannan Sadhasivam
` (2 subsequent siblings)
3 siblings, 0 replies; 9+ messages in thread
From: Manivannan Sadhasivam @ 2021-04-01 15:19 UTC (permalink / raw)
To: miquel.raynal, richard, vigneshr, robh+dt
Cc: linux-arm-msm, devicetree, linux-mtd, linux-kernel,
boris.brezillon, Daniele.Palmas, bjorn.andersson,
Manivannan Sadhasivam, Rob Herring
Convert Qcom NANDc devicetree binding to YAML.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/mtd/qcom,nandc.yaml | 196 ++++++++++++++++++
.../devicetree/bindings/mtd/qcom_nandc.txt | 142 -------------
2 files changed, 196 insertions(+), 142 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mtd/qcom,nandc.yaml
delete mode 100644 Documentation/devicetree/bindings/mtd/qcom_nandc.txt
diff --git a/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml b/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml
new file mode 100644
index 000000000000..84ad7ff30121
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/qcom,nandc.yaml
@@ -0,0 +1,196 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/qcom,nandc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm NAND controller
+
+maintainers:
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq806x-nand
+ - qcom,ipq4019-nand
+ - qcom,ipq6018-nand
+ - qcom,ipq8074-nand
+ - qcom,sdx55-nand
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Core Clock
+ - description: Always ON Clock
+
+ clock-names:
+ items:
+ - const: core
+ - const: aon
+
+ "#address-cells": true
+ "#size-cells": true
+
+patternProperties:
+ "^nand@[a-f0-9]$":
+ type: object
+ properties:
+ nand-bus-width:
+ const: 8
+
+ nand-ecc-strength:
+ enum: [1, 4, 8]
+
+ nand-ecc-step-size:
+ enum:
+ - 512
+
+allOf:
+ - $ref: "nand-controller.yaml#"
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,ipq806x-nand
+ then:
+ properties:
+ dmas:
+ items:
+ - description: rxtx DMA channel
+
+ dma-names:
+ items:
+ - const: rxtx
+
+ qcom,cmd-crci:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Must contain the ADM command type CRCI block instance number
+ specified for the NAND controller on the given platform
+
+ qcom,data-crci:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Must contain the ADM data type CRCI block instance number
+ specified for the NAND controller on the given platform
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq4019-nand
+ - qcom,ipq6018-nand
+ - qcom,ipq8074-nand
+ - qcom,sdx55-nand
+
+ then:
+ properties:
+ dmas:
+ items:
+ - description: tx DMA channel
+ - description: rx DMA channel
+ - description: cmd DMA channel
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+ - const: cmd
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
+ nand-controller@1ac00000 {
+ compatible = "qcom,ipq806x-nand";
+ reg = <0x1ac00000 0x800>;
+
+ clocks = <&gcc EBI2_CLK>,
+ <&gcc EBI2_AON_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&adm_dma 3>;
+ dma-names = "rxtx";
+ qcom,cmd-crci = <15>;
+ qcom,data-crci = <3>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+
+ nand-ecc-strength = <4>;
+ nand-bus-width = <8>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "boot-nand";
+ reg = <0 0x58a0000>;
+ };
+
+ partition@58a0000 {
+ label = "fs-nand";
+ reg = <0x58a0000 0x4000000>;
+ };
+ };
+ };
+ };
+
+ #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
+ nand-controller@79b0000 {
+ compatible = "qcom,ipq4019-nand";
+ reg = <0x79b0000 0x1000>;
+
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&qpicbam 0>,
+ <&qpicbam 1>,
+ <&qpicbam 2>;
+ dma-names = "tx", "rx", "cmd";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-bus-width = <8>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "boot-nand";
+ reg = <0 0x58a0000>;
+ };
+
+ partition@58a0000 {
+ label = "fs-nand";
+ reg = <0x58a0000 0x4000000>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt b/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
deleted file mode 100644
index 5647913d8837..000000000000
--- a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
+++ /dev/null
@@ -1,142 +0,0 @@
-* Qualcomm NAND controller
-
-Required properties:
-- compatible: must be one of the following:
- * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
- SoC and it uses ADM DMA
- * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
- IPQ4019 SoC and it uses BAM DMA
- * "qcom,ipq6018-nand" - for QPIC NAND controller v1.5.0 being used in
- IPQ6018 SoC and it uses BAM DMA
- * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
- IPQ8074 SoC and it uses BAM DMA
- * "qcom,sdx55-nand" - for QPIC NAND controller v2.0.0 being used in
- SDX55 SoC and it uses BAM DMA
-
-- reg: MMIO address range
-- clocks: must contain core clock and always on clock
-- clock-names: must contain "core" for the core clock and "aon" for the
- always on clock
-
-EBI2 specific properties:
-- dmas: DMA specifier, consisting of a phandle to the ADM DMA
- controller node and the channel number to be used for
- NAND. Refer to dma.txt and qcom_adm.txt for more details
-- dma-names: must be "rxtx"
-- qcom,cmd-crci: must contain the ADM command type CRCI block instance
- number specified for the NAND controller on the given
- platform
-- qcom,data-crci: must contain the ADM data type CRCI block instance
- number specified for the NAND controller on the given
- platform
-
-QPIC specific properties:
-- dmas: DMA specifier, consisting of a phandle to the BAM DMA
- and the channel number to be used for NAND. Refer to
- dma.txt, qcom_bam_dma.txt for more details
-- dma-names: must contain all 3 channel names : "tx", "rx", "cmd"
-- #address-cells: <1> - subnodes give the chip-select number
-- #size-cells: <0>
-
-* NAND chip-select
-
-Each controller may contain one or more subnodes to represent enabled
-chip-selects which (may) contain NAND flash chips. Their properties are as
-follows.
-
-Required properties:
-- reg: a single integer representing the chip-select
- number (e.g., 0, 1, 2, etc.)
-- #address-cells: see partition.txt
-- #size-cells: see partition.txt
-
-Optional properties:
-- nand-bus-width: see nand-controller.yaml
-- nand-ecc-strength: see nand-controller.yaml. If not specified, then ECC strength will
- be used according to chip requirement and available
- OOB size.
-
-Each nandcs device node may optionally contain a 'partitions' sub-node, which
-further contains sub-nodes describing the flash partition mapping. See
-partition.txt for more detail.
-
-Example:
-
-nand-controller@1ac00000 {
- compatible = "qcom,ipq806x-nand";
- reg = <0x1ac00000 0x800>;
-
- clocks = <&gcc EBI2_CLK>,
- <&gcc EBI2_AON_CLK>;
- clock-names = "core", "aon";
-
- dmas = <&adm_dma 3>;
- dma-names = "rxtx";
- qcom,cmd-crci = <15>;
- qcom,data-crci = <3>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- nand@0 {
- reg = <0>;
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "boot-nand";
- reg = <0 0x58a0000>;
- };
-
- partition@58a0000 {
- label = "fs-nand";
- reg = <0x58a0000 0x4000000>;
- };
- };
- };
-};
-
-nand-controller@79b0000 {
- compatible = "qcom,ipq4019-nand";
- reg = <0x79b0000 0x1000>;
-
- clocks = <&gcc GCC_QPIC_CLK>,
- <&gcc GCC_QPIC_AHB_CLK>;
- clock-names = "core", "aon";
-
- dmas = <&qpicbam 0>,
- <&qpicbam 1>,
- <&qpicbam 2>;
- dma-names = "tx", "rx", "cmd";
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- nand@0 {
- reg = <0>;
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "boot-nand";
- reg = <0 0x58a0000>;
- };
-
- partition@58a0000 {
- label = "fs-nand";
- reg = <0x58a0000 0x4000000>;
- };
- };
- };
-};
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v10 2/4] dt-bindings: mtd: Add a property to declare secure regions in NAND chips
2021-04-01 15:19 [PATCH v10 0/4] Add support for secure regions in NAND Manivannan Sadhasivam
2021-04-01 15:19 ` [PATCH v10 1/4] dt-bindings: mtd: Convert Qcom NANDc binding to YAML Manivannan Sadhasivam
@ 2021-04-01 15:19 ` Manivannan Sadhasivam
2021-04-01 15:19 ` [PATCH v10 3/4] mtd: rawnand: Add support for secure regions in NAND memory Manivannan Sadhasivam
2021-04-01 15:19 ` [PATCH v10 4/4] mtd: rawnand: qcom: Add missing nand_cleanup() in error path Manivannan Sadhasivam
3 siblings, 0 replies; 9+ messages in thread
From: Manivannan Sadhasivam @ 2021-04-01 15:19 UTC (permalink / raw)
To: miquel.raynal, richard, vigneshr, robh+dt
Cc: linux-arm-msm, devicetree, linux-mtd, linux-kernel,
boris.brezillon, Daniele.Palmas, bjorn.andersson,
Manivannan Sadhasivam, Rob Herring
On a typical end product, a vendor may choose to secure some regions in
the NAND memory which are supposed to stay intact between FW upgrades.
The access to those regions will be blocked by a secure element like
Trustzone. So the normal world software like Linux kernel should not
touch these regions (including reading).
So let's add a property for declaring such secure regions so that the
drivers can skip touching them.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
Documentation/devicetree/bindings/mtd/nand-controller.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
index d0e422f4b3e0..678b39952502 100644
--- a/Documentation/devicetree/bindings/mtd/nand-controller.yaml
+++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
@@ -143,6 +143,13 @@ patternProperties:
Ready/Busy pins. Active state refers to the NAND ready state and
should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
+ secure-regions:
+ $ref: /schemas/types.yaml#/definitions/uint64-matrix
+ description:
+ Regions in the NAND chip which are protected using a secure element
+ like Trustzone. This property contains the start address and size of
+ the secure regions present.
+
required:
- reg
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v10 3/4] mtd: rawnand: Add support for secure regions in NAND memory
2021-04-01 15:19 [PATCH v10 0/4] Add support for secure regions in NAND Manivannan Sadhasivam
2021-04-01 15:19 ` [PATCH v10 1/4] dt-bindings: mtd: Convert Qcom NANDc binding to YAML Manivannan Sadhasivam
2021-04-01 15:19 ` [PATCH v10 2/4] dt-bindings: mtd: Add a property to declare secure regions in NAND chips Manivannan Sadhasivam
@ 2021-04-01 15:19 ` Manivannan Sadhasivam
2021-04-01 15:54 ` Boris Brezillon
2021-04-01 15:19 ` [PATCH v10 4/4] mtd: rawnand: qcom: Add missing nand_cleanup() in error path Manivannan Sadhasivam
3 siblings, 1 reply; 9+ messages in thread
From: Manivannan Sadhasivam @ 2021-04-01 15:19 UTC (permalink / raw)
To: miquel.raynal, richard, vigneshr, robh+dt
Cc: linux-arm-msm, devicetree, linux-mtd, linux-kernel,
boris.brezillon, Daniele.Palmas, bjorn.andersson,
Manivannan Sadhasivam
On a typical end product, a vendor may choose to secure some regions in
the NAND memory which are supposed to stay intact between FW upgrades.
The access to those regions will be blocked by a secure element like
Trustzone. So the normal world software like Linux kernel should not
touch these regions (including reading).
The regions are declared using a NAND chip DT property,
"secure-regions". So let's make use of this property in the raw NAND
core and skip access to the secure regions present in a system.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/mtd/nand/raw/nand_base.c | 107 ++++++++++++++++++++++++++++++-
include/linux/mtd/rawnand.h | 14 ++++
2 files changed, 120 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index c33fa1b1847f..c216d3eca915 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -278,11 +278,50 @@ static int nand_block_bad(struct nand_chip *chip, loff_t ofs)
return 0;
}
+/**
+ * nand_region_is_secured() - Check if the region is secured
+ * @chip: NAND chip object
+ * @offset: Offset of the region to check
+ * @size: Size of the region to check
+ *
+ * Checks if the region is secured by comparing the offset and size with the
+ * list of secure regions obtained from DT. Returns true if the region is
+ * secured else false.
+ */
+static bool nand_region_is_secured(struct nand_chip *chip, loff_t offset, u64 size)
+{
+ int i;
+
+ /* Skip touching the secure regions if present */
+ for (i = 0; i < chip->nr_secure_regions; i++) {
+ const struct nand_secure_region *region = &chip->secure_regions[i];
+
+ if (offset + size <= region->offset ||
+ offset >= region->offset + region->size)
+ continue;
+
+ pr_debug("%s: Region 0x%llx - 0x%llx is secured!",
+ __func__, offset, offset + size);
+
+ return true;
+ }
+
+ return false;
+}
+
static int nand_isbad_bbm(struct nand_chip *chip, loff_t ofs)
{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ int last_page = ((mtd->erasesize - mtd->writesize) >>
+ chip->page_shift) & chip->pagemask;
+
if (chip->options & NAND_NO_BBM_QUIRK)
return 0;
+ /* Check if the region is secured */
+ if (nand_region_is_secured(chip, ofs, last_page))
+ return -EIO;
+
if (chip->legacy.block_bad)
return chip->legacy.block_bad(chip, ofs);
@@ -397,6 +436,10 @@ static int nand_do_write_oob(struct nand_chip *chip, loff_t to,
return -EINVAL;
}
+ /* Check if the region is secured */
+ if (nand_region_is_secured(chip, to, ops->ooblen))
+ return -EIO;
+
chipnr = (int)(to >> chip->chip_shift);
/*
@@ -565,6 +608,11 @@ static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
if (!chip->bbt)
return 0;
+
+ /* Check if the region is secured */
+ if (nand_region_is_secured(chip, ofs, 0))
+ return -EIO;
+
/* Return info from the table */
return nand_isreserved_bbt(chip, ofs);
}
@@ -3127,6 +3175,10 @@ static int nand_do_read_ops(struct nand_chip *chip, loff_t from,
int retry_mode = 0;
bool ecc_fail = false;
+ /* Check if the region is secured */
+ if (nand_region_is_secured(chip, from, readlen))
+ return -EIO;
+
chipnr = (int)(from >> chip->chip_shift);
nand_select_target(chip, chipnr);
@@ -3458,6 +3510,10 @@ static int nand_do_read_oob(struct nand_chip *chip, loff_t from,
pr_debug("%s: from = 0x%08Lx, len = %i\n",
__func__, (unsigned long long)from, readlen);
+ /* Check if the region is secured */
+ if (nand_region_is_secured(chip, from, readlen))
+ return -EIO;
+
stats = mtd->ecc_stats;
len = mtd_oobavail(mtd, ops);
@@ -3979,6 +4035,10 @@ static int nand_do_write_ops(struct nand_chip *chip, loff_t to,
return -EINVAL;
}
+ /* Check if the region is secured */
+ if (nand_region_is_secured(chip, to, writelen))
+ return -EIO;
+
column = to & (mtd->writesize - 1);
chipnr = (int)(to >> chip->chip_shift);
@@ -4180,6 +4240,10 @@ int nand_erase_nand(struct nand_chip *chip, struct erase_info *instr,
if (check_offs_len(chip, instr->addr, instr->len))
return -EINVAL;
+ /* Check if the region is secured */
+ if (nand_region_is_secured(chip, instr->addr, instr->len))
+ return -EIO;
+
/* Grab the lock and see if the device is available */
ret = nand_get_device(chip);
if (ret)
@@ -4995,6 +5059,31 @@ static bool of_get_nand_on_flash_bbt(struct device_node *np)
return of_property_read_bool(np, "nand-on-flash-bbt");
}
+static int of_get_nand_secure_regions(struct nand_chip *chip)
+{
+ struct device_node *dn = nand_get_flash_node(chip);
+ int nr_elem, i, j;
+
+ nr_elem = of_property_count_elems_of_size(dn, "secure-regions", sizeof(u64));
+ if (!nr_elem)
+ return 0;
+
+ chip->nr_secure_regions = nr_elem / 2;
+ chip->secure_regions = kcalloc(chip->nr_secure_regions, sizeof(*chip->secure_regions),
+ GFP_KERNEL);
+ if (!chip->secure_regions)
+ return -ENOMEM;
+
+ for (i = 0, j = 0; i < chip->nr_secure_regions; i++, j += 2) {
+ of_property_read_u64_index(dn, "secure-regions", j,
+ &chip->secure_regions[i].offset);
+ of_property_read_u64_index(dn, "secure-regions", j + 1,
+ &chip->secure_regions[i].size);
+ }
+
+ return 0;
+}
+
static int rawnand_dt_init(struct nand_chip *chip)
{
struct nand_device *nand = mtd_to_nanddev(nand_to_mtd(chip));
@@ -5953,6 +6042,16 @@ static int nand_scan_tail(struct nand_chip *chip)
goto err_free_interface_config;
}
+ /*
+ * Look for secure regions in the NAND chip. These regions are supposed
+ * to be protected by a secure element like Trustzone. So the read/write
+ * accesses to these regions will be blocked in the runtime by this
+ * driver.
+ */
+ ret = of_get_nand_secure_regions(chip);
+ if (ret)
+ goto err_free_interface_config;
+
/* Check, if we should skip the bad block table scan */
if (chip->options & NAND_SKIP_BBTSCAN)
return 0;
@@ -5960,10 +6059,13 @@ static int nand_scan_tail(struct nand_chip *chip)
/* Build bad block table */
ret = nand_create_bbt(chip);
if (ret)
- goto err_free_interface_config;
+ goto err_free_secure_regions;
return 0;
+err_free_secure_regions:
+ kfree(chip->secure_regions);
+
err_free_interface_config:
kfree(chip->best_interface_config);
@@ -6051,6 +6153,9 @@ void nand_cleanup(struct nand_chip *chip)
nanddev_cleanup(&chip->base);
+ /* Free secure regions data */
+ kfree(chip->secure_regions);
+
/* Free bad block table memory */
kfree(chip->bbt);
kfree(chip->data_buf);
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 6b3240e44310..17ddc900a1dc 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -1036,6 +1036,16 @@ struct nand_manufacturer {
void *priv;
};
+/**
+ * struct nand_secure_region - NAND secure region structure
+ * @offset: Offset of the start of the secure region
+ * @size: Size of the secure region
+ */
+struct nand_secure_region {
+ u64 offset;
+ u64 size;
+};
+
/**
* struct nand_chip - NAND Private Flash Chip Data
* @base: Inherit from the generic NAND device
@@ -1086,6 +1096,8 @@ struct nand_manufacturer {
* NAND Controller drivers should not modify this value, but they're
* allowed to read it.
* @read_retries: The number of read retry modes supported
+ * @secure_regions: Structure containing the secure regions info
+ * @nr_secure_regions: Number of secure regions
* @controller: The hardware controller structure which is shared among multiple
* independent devices
* @ecc: The ECC controller structure
@@ -1135,6 +1147,8 @@ struct nand_chip {
unsigned int suspended : 1;
int cur_cs;
int read_retries;
+ struct nand_secure_region *secure_regions;
+ u8 nr_secure_regions;
/* Externals */
struct nand_controller *controller;
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v10 3/4] mtd: rawnand: Add support for secure regions in NAND memory
2021-04-01 15:19 ` [PATCH v10 3/4] mtd: rawnand: Add support for secure regions in NAND memory Manivannan Sadhasivam
@ 2021-04-01 15:54 ` Boris Brezillon
2021-04-01 16:16 ` Manivannan Sadhasivam
0 siblings, 1 reply; 9+ messages in thread
From: Boris Brezillon @ 2021-04-01 15:54 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: miquel.raynal, richard, vigneshr, robh+dt, linux-arm-msm,
devicetree, linux-mtd, linux-kernel, Daniele.Palmas,
bjorn.andersson
On Thu, 1 Apr 2021 20:49:54 +0530
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> wrote:
> @@ -565,6 +608,11 @@ static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
>
> if (!chip->bbt)
> return 0;
> +
> + /* Check if the region is secured */
> + if (nand_region_is_secured(chip, ofs, 0))
> + return -EIO;
That would is still wrong, you should never pass a 0 size to
nand_region_is_secured().
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v10 3/4] mtd: rawnand: Add support for secure regions in NAND memory
2021-04-01 15:54 ` Boris Brezillon
@ 2021-04-01 16:16 ` Manivannan Sadhasivam
2021-04-02 8:51 ` Boris Brezillon
0 siblings, 1 reply; 9+ messages in thread
From: Manivannan Sadhasivam @ 2021-04-01 16:16 UTC (permalink / raw)
To: Boris Brezillon
Cc: miquel.raynal, richard, vigneshr, robh+dt, linux-arm-msm,
devicetree, linux-mtd, linux-kernel, Daniele.Palmas,
bjorn.andersson
On Thu, Apr 01, 2021 at 05:54:21PM +0200, Boris Brezillon wrote:
> On Thu, 1 Apr 2021 20:49:54 +0530
> Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> wrote:
>
> > @@ -565,6 +608,11 @@ static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
> >
> > if (!chip->bbt)
> > return 0;
> > +
> > + /* Check if the region is secured */
> > + if (nand_region_is_secured(chip, ofs, 0))
> > + return -EIO;
>
> That would is still wrong, you should never pass a 0 size to
> nand_region_is_secured().
>
Size doesn't matter here, that's why I passed 0. Maybe 1 would be
appropriate?
Thanks,
Mani
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v10 3/4] mtd: rawnand: Add support for secure regions in NAND memory
2021-04-01 16:16 ` Manivannan Sadhasivam
@ 2021-04-02 8:51 ` Boris Brezillon
2021-04-02 14:27 ` Manivannan Sadhasivam
0 siblings, 1 reply; 9+ messages in thread
From: Boris Brezillon @ 2021-04-02 8:51 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: miquel.raynal, richard, vigneshr, robh+dt, linux-arm-msm,
devicetree, linux-mtd, linux-kernel, Daniele.Palmas,
bjorn.andersson
On Thu, 1 Apr 2021 21:46:22 +0530
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> wrote:
> On Thu, Apr 01, 2021 at 05:54:21PM +0200, Boris Brezillon wrote:
> > On Thu, 1 Apr 2021 20:49:54 +0530
> > Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> wrote:
> >
> > > @@ -565,6 +608,11 @@ static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
> > >
> > > if (!chip->bbt)
> > > return 0;
> > > +
> > > + /* Check if the region is secured */
> > > + if (nand_region_is_secured(chip, ofs, 0))
> > > + return -EIO;
> >
> > That would is still wrong, you should never pass a 0 size to
> > nand_region_is_secured().
> >
>
> Size doesn't matter here, that's why I passed 0. Maybe 1 would be
> appropriate?
You're checking if a block is reserved, so I think passing the
eraseblock size would make more sense, but I actually don't understand
why you need to check if the region is secure here (looks like
nand_block_isreserved() does not access the flash).
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v10 3/4] mtd: rawnand: Add support for secure regions in NAND memory
2021-04-02 8:51 ` Boris Brezillon
@ 2021-04-02 14:27 ` Manivannan Sadhasivam
0 siblings, 0 replies; 9+ messages in thread
From: Manivannan Sadhasivam @ 2021-04-02 14:27 UTC (permalink / raw)
To: Boris Brezillon
Cc: miquel.raynal, richard, vigneshr, robh+dt, linux-arm-msm,
devicetree, linux-mtd, linux-kernel, Daniele.Palmas,
bjorn.andersson
On Fri, Apr 02, 2021 at 10:51:54AM +0200, Boris Brezillon wrote:
> On Thu, 1 Apr 2021 21:46:22 +0530
> Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> wrote:
>
> > On Thu, Apr 01, 2021 at 05:54:21PM +0200, Boris Brezillon wrote:
> > > On Thu, 1 Apr 2021 20:49:54 +0530
> > > Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> wrote:
> > >
> > > > @@ -565,6 +608,11 @@ static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
> > > >
> > > > if (!chip->bbt)
> > > > return 0;
> > > > +
> > > > + /* Check if the region is secured */
> > > > + if (nand_region_is_secured(chip, ofs, 0))
> > > > + return -EIO;
> > >
> > > That would is still wrong, you should never pass a 0 size to
> > > nand_region_is_secured().
> > >
> >
> > Size doesn't matter here, that's why I passed 0. Maybe 1 would be
> > appropriate?
>
> You're checking if a block is reserved, so I think passing the
> eraseblock size would make more sense, but I actually don't understand
> why you need to check if the region is secure here (looks like
> nand_block_isreserved() does not access the flash).
>
Ah yes indeed, brain fade...
Thanks,
Mani
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v10 4/4] mtd: rawnand: qcom: Add missing nand_cleanup() in error path
2021-04-01 15:19 [PATCH v10 0/4] Add support for secure regions in NAND Manivannan Sadhasivam
` (2 preceding siblings ...)
2021-04-01 15:19 ` [PATCH v10 3/4] mtd: rawnand: Add support for secure regions in NAND memory Manivannan Sadhasivam
@ 2021-04-01 15:19 ` Manivannan Sadhasivam
3 siblings, 0 replies; 9+ messages in thread
From: Manivannan Sadhasivam @ 2021-04-01 15:19 UTC (permalink / raw)
To: miquel.raynal, richard, vigneshr, robh+dt
Cc: linux-arm-msm, devicetree, linux-mtd, linux-kernel,
boris.brezillon, Daniele.Palmas, bjorn.andersson,
Manivannan Sadhasivam
Add missing nand_cleanup() in the alloc_bam_transaction() error path
to cleanup the resources properly.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/mtd/nand/raw/qcom_nandc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index 87c23bb320bf..fe74cf3aece5 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -2882,6 +2882,7 @@ static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc,
if (!nandc->bam_txn) {
dev_err(nandc->dev,
"failed to allocate bam transaction\n");
+ nand_cleanup(chip);
return -ENOMEM;
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread