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* [PATCH 1/2] clk: qcom: add support for SM8350 DISPCC
@ 2021-05-13 19:56 Jonathan Marek
  2021-05-13 19:56 ` [PATCH 2/2] dt-bindings: clock: add QCOM SM8350 display clock bindings Jonathan Marek
  2021-05-18 11:53 ` [PATCH 1/2] clk: qcom: add support for SM8350 DISPCC Robert Foss
  0 siblings, 2 replies; 5+ messages in thread
From: Jonathan Marek @ 2021-05-13 19:56 UTC (permalink / raw)
  To: linux-arm-msm
  Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
	open list:COMMON CLK FRAMEWORK, open list

Add support to the SM8350 display clock controller by extending the SM8250
display clock controller, which is almost identical but has some minor
differences.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
 drivers/clk/qcom/Kconfig         |  4 +-
 drivers/clk/qcom/dispcc-sm8250.c | 84 +++++++++++++++++++++++++++-----
 2 files changed, 75 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 45646b867cdb..cc60e6ee1654 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -484,11 +484,11 @@ config SDX_GCC_55
 	  SPI, I2C, USB, SD/UFS, PCIe etc.
 
 config SM_DISPCC_8250
-	tristate "SM8150 and SM8250 Display Clock Controller"
+	tristate "SM8150/SM8250/SM8350 Display Clock Controller"
 	depends on SM_GCC_8150 || SM_GCC_8250
 	help
 	  Support for the display clock controller on Qualcomm Technologies, Inc
-	  SM8150 and SM8250 devices.
+	  SM8150/SM8250/SM8350 devices.
 	  Say Y if you want to support display devices and functionality such as
 	  splash screen.
 
diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
index de09cd5c209f..1fcf8085a109 100644
--- a/drivers/clk/qcom/dispcc-sm8250.c
+++ b/drivers/clk/qcom/dispcc-sm8250.c
@@ -36,6 +36,10 @@ static struct pll_vco vco_table[] = {
 	{ 249600000, 2000000000, 0 },
 };
 
+static struct pll_vco lucid_5lpe_vco[] = {
+	{ 249600000, 1750000000, 0 },
+};
+
 static struct alpha_pll_config disp_cc_pll0_config = {
 	.l = 0x47,
 	.alpha = 0xE000,
@@ -1039,6 +1043,7 @@ static const struct qcom_cc_desc disp_cc_sm8250_desc = {
 static const struct of_device_id disp_cc_sm8250_match_table[] = {
 	{ .compatible = "qcom,sm8150-dispcc" },
 	{ .compatible = "qcom,sm8250-dispcc" },
+	{ .compatible = "qcom,sm8350-dispcc" },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table);
@@ -1051,19 +1056,76 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
 
-	/* note: trion == lucid, except for the prepare() op */
-	BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID);
-	if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) {
-		disp_cc_pll0_config.config_ctl_hi_val = 0x00002267;
-		disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024;
-		disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0;
-		disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops;
-		disp_cc_pll1_config.config_ctl_hi_val = 0x00002267;
-		disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024;
-		disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0;
-		disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops;
+	/* SM8350 has _SRC clocks offset by 4, and some other differences */
+	if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) {
+		static struct clk_rcg2* const rcgs[] = {
+			&disp_cc_mdss_byte0_clk_src,
+			&disp_cc_mdss_byte1_clk_src,
+			&disp_cc_mdss_dp_aux1_clk_src,
+			&disp_cc_mdss_dp_aux_clk_src,
+			&disp_cc_mdss_dp_link1_clk_src,
+			&disp_cc_mdss_dp_link_clk_src,
+			&disp_cc_mdss_dp_pixel1_clk_src,
+			&disp_cc_mdss_dp_pixel2_clk_src,
+			&disp_cc_mdss_dp_pixel_clk_src,
+			&disp_cc_mdss_esc0_clk_src,
+			&disp_cc_mdss_mdp_clk_src,
+			&disp_cc_mdss_pclk0_clk_src,
+			&disp_cc_mdss_pclk1_clk_src,
+			&disp_cc_mdss_rot_clk_src,
+			&disp_cc_mdss_vsync_clk_src,
+		};
+		static struct clk_regmap_div* const divs[] = {
+			&disp_cc_mdss_byte0_div_clk_src,
+			&disp_cc_mdss_byte1_div_clk_src,
+			&disp_cc_mdss_dp_link1_div_clk_src,
+			&disp_cc_mdss_dp_link_div_clk_src,
+		};
+		unsigned i;
+		static bool offset_applied = false;
+
+		/* only apply the offsets once (in case of deferred probe) */
+		if (!offset_applied) {
+			for (i = 0; i < ARRAY_SIZE(rcgs); i++)
+				rcgs[i]->cmd_rcgr -= 4;
+
+			for (i = 0; i < ARRAY_SIZE(divs); i++) {
+				divs[i]->reg -= 4;
+				divs[i]->width = 4;
+			}
+
+			disp_cc_mdss_ahb_clk.halt_reg -= 4;
+			disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4;
+
+			offset_applied = true;
+		}
+
+		disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0;
+
+		disp_cc_pll0_config.config_ctl_hi1_val = 0x2A9A699C;
+		disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000;
+		disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
+		disp_cc_pll0.vco_table = lucid_5lpe_vco;
+		disp_cc_pll1_config.config_ctl_hi1_val = 0x2A9A699C;
+		disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000;
+		disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
+		disp_cc_pll1.vco_table = lucid_5lpe_vco;
+	} else {
+		/* note: trion == lucid, except for the prepare() op */
+		BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID);
+		if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) {
+			disp_cc_pll0_config.config_ctl_hi_val = 0x00002267;
+			disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024;
+			disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0;
+			disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops;
+			disp_cc_pll1_config.config_ctl_hi_val = 0x00002267;
+			disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024;
+			disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0;
+			disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops;
+		}
 	}
 
+	/* note for SM8350: downstream lucid_5lpe configure differs slightly */
 	clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
 	clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
 
-- 
2.26.1


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 2/2] dt-bindings: clock: add QCOM SM8350 display clock bindings
  2021-05-13 19:56 [PATCH 1/2] clk: qcom: add support for SM8350 DISPCC Jonathan Marek
@ 2021-05-13 19:56 ` Jonathan Marek
  2021-05-18  1:15   ` Rob Herring
  2021-05-18 11:53 ` [PATCH 1/2] clk: qcom: add support for SM8350 DISPCC Robert Foss
  1 sibling, 1 reply; 5+ messages in thread
From: Jonathan Marek @ 2021-05-13 19:56 UTC (permalink / raw)
  To: linux-arm-msm
  Cc: Andy Gross, Bjorn Andersson, Michael Turquette, Stephen Boyd,
	Rob Herring, open list:COMMON CLK FRAMEWORK,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list

Add sm8350 DISPCC bindings, which are simply a symlink to the sm8250
bindings. Update the documentation with add the new compatible.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
 .../devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml       | 6 ++++--
 include/dt-bindings/clock/qcom,dispcc-sm8350.h              | 1 +
 2 files changed, 5 insertions(+), 2 deletions(-)
 create mode 120000 include/dt-bindings/clock/qcom,dispcc-sm8350.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
index 0cdf53f41f84..8f414642445e 100644
--- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
@@ -4,24 +4,26 @@
 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
+title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350
 
 maintainers:
   - Jonathan Marek <jonathan@marek.ca>
 
 description: |
   Qualcomm display clock control module which supports the clocks, resets and
-  power domains on SM8150 and SM8250.
+  power domains on SM8150/SM8250/SM8350.
 
   See also:
     dt-bindings/clock/qcom,dispcc-sm8150.h
     dt-bindings/clock/qcom,dispcc-sm8250.h
+    dt-bindings/clock/qcom,dispcc-sm8350.h
 
 properties:
   compatible:
     enum:
       - qcom,sm8150-dispcc
       - qcom,sm8250-dispcc
+      - qcom,sm8350-dispcc
 
   clocks:
     items:
diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8350.h b/include/dt-bindings/clock/qcom,dispcc-sm8350.h
new file mode 120000
index 000000000000..0312b4544acb
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,dispcc-sm8350.h
@@ -0,0 +1 @@
+qcom,dispcc-sm8250.h
\ No newline at end of file
-- 
2.26.1


^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH 2/2] dt-bindings: clock: add QCOM SM8350 display clock bindings
  2021-05-13 19:56 ` [PATCH 2/2] dt-bindings: clock: add QCOM SM8350 display clock bindings Jonathan Marek
@ 2021-05-18  1:15   ` Rob Herring
  0 siblings, 0 replies; 5+ messages in thread
From: Rob Herring @ 2021-05-18  1:15 UTC (permalink / raw)
  To: Jonathan Marek
  Cc: Michael Turquette, linux-clk, Andy Gross, Rob Herring,
	linux-arm-msm, linux-kernel, devicetree, Stephen Boyd,
	Bjorn Andersson

On Thu, 13 May 2021 15:56:17 -0400, Jonathan Marek wrote:
> Add sm8350 DISPCC bindings, which are simply a symlink to the sm8250
> bindings. Update the documentation with add the new compatible.
> 
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
>  .../devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml       | 6 ++++--
>  include/dt-bindings/clock/qcom,dispcc-sm8350.h              | 1 +
>  2 files changed, 5 insertions(+), 2 deletions(-)
>  create mode 120000 include/dt-bindings/clock/qcom,dispcc-sm8350.h
> 

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH 1/2] clk: qcom: add support for SM8350 DISPCC
  2021-05-13 19:56 [PATCH 1/2] clk: qcom: add support for SM8350 DISPCC Jonathan Marek
  2021-05-13 19:56 ` [PATCH 2/2] dt-bindings: clock: add QCOM SM8350 display clock bindings Jonathan Marek
@ 2021-05-18 11:53 ` Robert Foss
  2021-05-18 12:30   ` Jonathan Marek
  1 sibling, 1 reply; 5+ messages in thread
From: Robert Foss @ 2021-05-18 11:53 UTC (permalink / raw)
  To: Jonathan Marek
  Cc: MSM, Andy Gross, Bjorn Andersson, Michael Turquette,
	Stephen Boyd, open list:COMMON CLK FRAMEWORK, open list

Hey Jonathan,

Thanks for submitting this.

On Thu, 13 May 2021 at 21:56, Jonathan Marek <jonathan@marek.ca> wrote:
>
> Add support to the SM8350 display clock controller by extending the SM8250
> display clock controller, which is almost identical but has some minor
> differences.
>
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
>  drivers/clk/qcom/Kconfig         |  4 +-
>  drivers/clk/qcom/dispcc-sm8250.c | 84 +++++++++++++++++++++++++++-----
>  2 files changed, 75 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 45646b867cdb..cc60e6ee1654 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -484,11 +484,11 @@ config SDX_GCC_55
>           SPI, I2C, USB, SD/UFS, PCIe etc.
>
>  config SM_DISPCC_8250
> -       tristate "SM8150 and SM8250 Display Clock Controller"
> +       tristate "SM8150/SM8250/SM8350 Display Clock Controller"
>         depends on SM_GCC_8150 || SM_GCC_8250
>         help
>           Support for the display clock controller on Qualcomm Technologies, Inc
> -         SM8150 and SM8250 devices.
> +         SM8150/SM8250/SM8350 devices.
>           Say Y if you want to support display devices and functionality such as
>           splash screen.
>
> diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
> index de09cd5c209f..1fcf8085a109 100644
> --- a/drivers/clk/qcom/dispcc-sm8250.c
> +++ b/drivers/clk/qcom/dispcc-sm8250.c
> @@ -36,6 +36,10 @@ static struct pll_vco vco_table[] = {
>         { 249600000, 2000000000, 0 },
>  };
>
> +static struct pll_vco lucid_5lpe_vco[] = {
> +       { 249600000, 1750000000, 0 },
> +};
> +
>  static struct alpha_pll_config disp_cc_pll0_config = {
>         .l = 0x47,
>         .alpha = 0xE000,
> @@ -1039,6 +1043,7 @@ static const struct qcom_cc_desc disp_cc_sm8250_desc = {
>  static const struct of_device_id disp_cc_sm8250_match_table[] = {
>         { .compatible = "qcom,sm8150-dispcc" },
>         { .compatible = "qcom,sm8250-dispcc" },
> +       { .compatible = "qcom,sm8350-dispcc" },
>         { }
>  };
>  MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table);
> @@ -1051,19 +1056,76 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
>         if (IS_ERR(regmap))
>                 return PTR_ERR(regmap);
>
> -       /* note: trion == lucid, except for the prepare() op */
> -       BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID);
> -       if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) {

I'm having a quick look at this patch, and of_device_is_compatible had
2 cases previously, sm8150 & sm8250. Now three cases (sm8150, sm8250 &
sm8350) are possible, but sm8150 & sm8250 have been lumped together.
Is this correct?

> -               disp_cc_pll0_config.config_ctl_hi_val = 0x00002267;
> -               disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024;
> -               disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0;
> -               disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops;
> -               disp_cc_pll1_config.config_ctl_hi_val = 0x00002267;
> -               disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024;
> -               disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0;
> -               disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops;
> +       /* SM8350 has _SRC clocks offset by 4, and some other differences */
> +       if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) {
> +               static struct clk_rcg2* const rcgs[] = {
> +                       &disp_cc_mdss_byte0_clk_src,
> +                       &disp_cc_mdss_byte1_clk_src,
> +                       &disp_cc_mdss_dp_aux1_clk_src,
> +                       &disp_cc_mdss_dp_aux_clk_src,
> +                       &disp_cc_mdss_dp_link1_clk_src,
> +                       &disp_cc_mdss_dp_link_clk_src,
> +                       &disp_cc_mdss_dp_pixel1_clk_src,
> +                       &disp_cc_mdss_dp_pixel2_clk_src,
> +                       &disp_cc_mdss_dp_pixel_clk_src,
> +                       &disp_cc_mdss_esc0_clk_src,
> +                       &disp_cc_mdss_mdp_clk_src,
> +                       &disp_cc_mdss_pclk0_clk_src,
> +                       &disp_cc_mdss_pclk1_clk_src,
> +                       &disp_cc_mdss_rot_clk_src,
> +                       &disp_cc_mdss_vsync_clk_src,
> +               };
> +               static struct clk_regmap_div* const divs[] = {
> +                       &disp_cc_mdss_byte0_div_clk_src,
> +                       &disp_cc_mdss_byte1_div_clk_src,
> +                       &disp_cc_mdss_dp_link1_div_clk_src,
> +                       &disp_cc_mdss_dp_link_div_clk_src,
> +               };
> +               unsigned i;
> +               static bool offset_applied = false;
> +
> +               /* only apply the offsets once (in case of deferred probe) */
> +               if (!offset_applied) {
> +                       for (i = 0; i < ARRAY_SIZE(rcgs); i++)
> +                               rcgs[i]->cmd_rcgr -= 4;
> +
> +                       for (i = 0; i < ARRAY_SIZE(divs); i++) {
> +                               divs[i]->reg -= 4;
> +                               divs[i]->width = 4;
> +                       }
> +
> +                       disp_cc_mdss_ahb_clk.halt_reg -= 4;
> +                       disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4;
> +
> +                       offset_applied = true;
> +               }
> +
> +               disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0;
> +
> +               disp_cc_pll0_config.config_ctl_hi1_val = 0x2A9A699C;
> +               disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000;
> +               disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
> +               disp_cc_pll0.vco_table = lucid_5lpe_vco;
> +               disp_cc_pll1_config.config_ctl_hi1_val = 0x2A9A699C;
> +               disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000;
> +               disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
> +               disp_cc_pll1.vco_table = lucid_5lpe_vco;
> +       } else {
> +               /* note: trion == lucid, except for the prepare() op */
> +               BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID);
> +               if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) {
> +                       disp_cc_pll0_config.config_ctl_hi_val = 0x00002267;
> +                       disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024;
> +                       disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0;
> +                       disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops;
> +                       disp_cc_pll1_config.config_ctl_hi_val = 0x00002267;
> +                       disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024;
> +                       disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0;
> +                       disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops;
> +               }
>         }
>
> +       /* note for SM8350: downstream lucid_5lpe configure differs slightly */
>         clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
>         clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
>
> --
> 2.26.1
>

^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH 1/2] clk: qcom: add support for SM8350 DISPCC
  2021-05-18 11:53 ` [PATCH 1/2] clk: qcom: add support for SM8350 DISPCC Robert Foss
@ 2021-05-18 12:30   ` Jonathan Marek
  0 siblings, 0 replies; 5+ messages in thread
From: Jonathan Marek @ 2021-05-18 12:30 UTC (permalink / raw)
  To: Robert Foss
  Cc: MSM, Andy Gross, Bjorn Andersson, Michael Turquette,
	Stephen Boyd, open list:COMMON CLK FRAMEWORK, open list

On 5/18/21 7:53 AM, Robert Foss wrote:
> Hey Jonathan,
> 
> Thanks for submitting this.
> 
> On Thu, 13 May 2021 at 21:56, Jonathan Marek <jonathan@marek.ca> wrote:
>>
>> Add support to the SM8350 display clock controller by extending the SM8250
>> display clock controller, which is almost identical but has some minor
>> differences.
>>
>> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
>> ---
>>   drivers/clk/qcom/Kconfig         |  4 +-
>>   drivers/clk/qcom/dispcc-sm8250.c | 84 +++++++++++++++++++++++++++-----
>>   2 files changed, 75 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index 45646b867cdb..cc60e6ee1654 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -484,11 +484,11 @@ config SDX_GCC_55
>>            SPI, I2C, USB, SD/UFS, PCIe etc.
>>
>>   config SM_DISPCC_8250
>> -       tristate "SM8150 and SM8250 Display Clock Controller"
>> +       tristate "SM8150/SM8250/SM8350 Display Clock Controller"
>>          depends on SM_GCC_8150 || SM_GCC_8250
>>          help
>>            Support for the display clock controller on Qualcomm Technologies, Inc
>> -         SM8150 and SM8250 devices.
>> +         SM8150/SM8250/SM8350 devices.
>>            Say Y if you want to support display devices and functionality such as
>>            splash screen.
>>
>> diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
>> index de09cd5c209f..1fcf8085a109 100644
>> --- a/drivers/clk/qcom/dispcc-sm8250.c
>> +++ b/drivers/clk/qcom/dispcc-sm8250.c
>> @@ -36,6 +36,10 @@ static struct pll_vco vco_table[] = {
>>          { 249600000, 2000000000, 0 },
>>   };
>>
>> +static struct pll_vco lucid_5lpe_vco[] = {
>> +       { 249600000, 1750000000, 0 },
>> +};
>> +
>>   static struct alpha_pll_config disp_cc_pll0_config = {
>>          .l = 0x47,
>>          .alpha = 0xE000,
>> @@ -1039,6 +1043,7 @@ static const struct qcom_cc_desc disp_cc_sm8250_desc = {
>>   static const struct of_device_id disp_cc_sm8250_match_table[] = {
>>          { .compatible = "qcom,sm8150-dispcc" },
>>          { .compatible = "qcom,sm8250-dispcc" },
>> +       { .compatible = "qcom,sm8350-dispcc" },
>>          { }
>>   };
>>   MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table);
>> @@ -1051,19 +1056,76 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev)
>>          if (IS_ERR(regmap))
>>                  return PTR_ERR(regmap);
>>
>> -       /* note: trion == lucid, except for the prepare() op */
>> -       BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID);
>> -       if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) {
> 
> I'm having a quick look at this patch, and of_device_is_compatible had
> 2 cases previously, sm8150 & sm8250. Now three cases (sm8150, sm8250 &
> sm8350) are possible, but sm8150 & sm8250 have been lumped together.
> Is this correct?
> 

This patch doesn't change the behavior for sm8150/sm8250, which are 
nearly identical. The check for qcom,sm8150-dispcc is just moved below.

(looking over it, I should've left it first and kept the diff smaller. I 
had "lumped" sm8150/sm8250 because initially I had separate 
"pll_configure" calls for sm8350 vs sm8150/sm8250).

>> -               disp_cc_pll0_config.config_ctl_hi_val = 0x00002267;
>> -               disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024;
>> -               disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0;
>> -               disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops;
>> -               disp_cc_pll1_config.config_ctl_hi_val = 0x00002267;
>> -               disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024;
>> -               disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0;
>> -               disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops;
>> +       /* SM8350 has _SRC clocks offset by 4, and some other differences */
>> +       if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) {
>> +               static struct clk_rcg2* const rcgs[] = {
>> +                       &disp_cc_mdss_byte0_clk_src,
>> +                       &disp_cc_mdss_byte1_clk_src,
>> +                       &disp_cc_mdss_dp_aux1_clk_src,
>> +                       &disp_cc_mdss_dp_aux_clk_src,
>> +                       &disp_cc_mdss_dp_link1_clk_src,
>> +                       &disp_cc_mdss_dp_link_clk_src,
>> +                       &disp_cc_mdss_dp_pixel1_clk_src,
>> +                       &disp_cc_mdss_dp_pixel2_clk_src,
>> +                       &disp_cc_mdss_dp_pixel_clk_src,
>> +                       &disp_cc_mdss_esc0_clk_src,
>> +                       &disp_cc_mdss_mdp_clk_src,
>> +                       &disp_cc_mdss_pclk0_clk_src,
>> +                       &disp_cc_mdss_pclk1_clk_src,
>> +                       &disp_cc_mdss_rot_clk_src,
>> +                       &disp_cc_mdss_vsync_clk_src,
>> +               };
>> +               static struct clk_regmap_div* const divs[] = {
>> +                       &disp_cc_mdss_byte0_div_clk_src,
>> +                       &disp_cc_mdss_byte1_div_clk_src,
>> +                       &disp_cc_mdss_dp_link1_div_clk_src,
>> +                       &disp_cc_mdss_dp_link_div_clk_src,
>> +               };
>> +               unsigned i;
>> +               static bool offset_applied = false;
>> +
>> +               /* only apply the offsets once (in case of deferred probe) */
>> +               if (!offset_applied) {
>> +                       for (i = 0; i < ARRAY_SIZE(rcgs); i++)
>> +                               rcgs[i]->cmd_rcgr -= 4;
>> +
>> +                       for (i = 0; i < ARRAY_SIZE(divs); i++) {
>> +                               divs[i]->reg -= 4;
>> +                               divs[i]->width = 4;
>> +                       }
>> +
>> +                       disp_cc_mdss_ahb_clk.halt_reg -= 4;
>> +                       disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4;
>> +
>> +                       offset_applied = true;
>> +               }
>> +
>> +               disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0;
>> +
>> +               disp_cc_pll0_config.config_ctl_hi1_val = 0x2A9A699C;
>> +               disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000;
>> +               disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
>> +               disp_cc_pll0.vco_table = lucid_5lpe_vco;
>> +               disp_cc_pll1_config.config_ctl_hi1_val = 0x2A9A699C;
>> +               disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000;
>> +               disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
>> +               disp_cc_pll1.vco_table = lucid_5lpe_vco;
>> +       } else {
>> +               /* note: trion == lucid, except for the prepare() op */
>> +               BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID);
>> +               if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) {
>> +                       disp_cc_pll0_config.config_ctl_hi_val = 0x00002267;
>> +                       disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024;
>> +                       disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0;
>> +                       disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops;
>> +                       disp_cc_pll1_config.config_ctl_hi_val = 0x00002267;
>> +                       disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024;
>> +                       disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0;
>> +                       disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops;
>> +               }
>>          }
>>
>> +       /* note for SM8350: downstream lucid_5lpe configure differs slightly */
>>          clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
>>          clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
>>
>> --
>> 2.26.1
>>

^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2021-05-18 12:31 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-13 19:56 [PATCH 1/2] clk: qcom: add support for SM8350 DISPCC Jonathan Marek
2021-05-13 19:56 ` [PATCH 2/2] dt-bindings: clock: add QCOM SM8350 display clock bindings Jonathan Marek
2021-05-18  1:15   ` Rob Herring
2021-05-18 11:53 ` [PATCH 1/2] clk: qcom: add support for SM8350 DISPCC Robert Foss
2021-05-18 12:30   ` Jonathan Marek

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