[PATCH 00/11] clk: qcom: another round of clock drivers cleanup

[PATCH 00/11] clk: qcom: another round of clock drivers cleanup

[Dmitry Baryshkov]

Another bunch of updates for Qualcomm clock controller driver, removing
unused enum values, test clock, using parent_data, parent_hws and
ARRAY_SIZE.

The following changes since commit fa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf:

  Linux 5.16-rc1 (2021-11-14 13:56:52 -0800)

are available in the Git repository at:

  https://git.linaro.org/people/dmitry.baryshkov/kernel.git msm-clocks-bulk-2

for you to fetch changes up to 7589a5b1bf85ad364815b238586d90e1d446f8d8:

  clk: qcom: gcc-msm8996: use ARRAY_SIZE instead of specifying num_parents (2021-12-08 20:52:09 +0300)

----------------------------------------------------------------
Dmitry Baryshkov (11):
      clk: qcom: gpucc-sdm660: get rid of the test clock
      clk: qcom: gpucc-sdm660: use parent_hws instead of parent_data
      clk: qcom: camcc-sc7180: get rid of the test clock
      clk: qcom: camcc-sdm845: get rid of the test clock
      clk: qcom: camcc-sdm845: convert to parent data
      clk: qcom: camcc-sc7180: use parent_hws instead of parent_data
      clk: qcom: videocc-sc7180: use parent_hws instead of parent_data
      clk: qcom: gcc-msm8996: drop unsupported clock sources
      clk: qcom: gcc-msm8996: move clock parent tables down
      clk: qcom: gcc-msm8996: use parent_hws/_data instead of parent_names
      clk: qcom: gcc-msm8996: use ARRAY_SIZE instead of specifying num_parents

 drivers/clk/qcom/camcc-sc7180.c   | 221 ++++-----
 drivers/clk/qcom/camcc-sdm845.c   | 323 +++++++------
 drivers/clk/qcom/gcc-msm8996.c    | 971 +++++++++++++++++++++++---------------
 drivers/clk/qcom/gpucc-sdm660.c   |  13 +-
 drivers/clk/qcom/videocc-sc7180.c |   8 +-
 5 files changed, 870 insertions(+), 666 deletions(-)

[PATCH 01/11] clk: qcom: gpucc-sdm660: get rid of the test clock

[Dmitry Baryshkov]

The test clock isn't in the bindings and apparently it's not used by
anyone upstream.  Remove it.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/gpucc-sdm660.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/clk/qcom/gpucc-sdm660.c b/drivers/clk/qcom/gpucc-sdm660.c
index 41bba96a08b3..26e17f349a77 100644
--- a/drivers/clk/qcom/gpucc-sdm660.c
+++ b/drivers/clk/qcom/gpucc-sdm660.c
@@ -29,7 +29,6 @@
 
 enum {
 	P_GPU_XO,
-	P_CORE_BI_PLL_TEST_SE,
 	P_GPLL0_OUT_MAIN,
 	P_GPLL0_OUT_MAIN_DIV,
 	P_GPU_PLL0_PLL_OUT_MAIN,
-- 
2.33.0

[PATCH 02/11] clk: qcom: gpucc-sdm660: use parent_hws instead of parent_data

[Dmitry Baryshkov]

If all parents are specified as clk_hw, we can use parent_hws instead of
parent_data.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/gpucc-sdm660.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/qcom/gpucc-sdm660.c b/drivers/clk/qcom/gpucc-sdm660.c
index 26e17f349a77..27a506a78a25 100644
--- a/drivers/clk/qcom/gpucc-sdm660.c
+++ b/drivers/clk/qcom/gpucc-sdm660.c
@@ -65,8 +65,8 @@ static struct clk_alpha_pll gpu_pll0_pll_out_main = {
 	.num_vco = ARRAY_SIZE(gpu_vco),
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gpu_pll0_pll_out_main",
-		.parent_data =  &(const struct clk_parent_data){
-			.hw = &gpucc_cxo_clk.clkr.hw,
+		.parent_hws = (const struct clk_hw*[]){
+			&gpucc_cxo_clk.clkr.hw,
 		},
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_ops,
@@ -80,8 +80,8 @@ static struct clk_alpha_pll gpu_pll1_pll_out_main = {
 	.num_vco = ARRAY_SIZE(gpu_vco),
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gpu_pll1_pll_out_main",
-		.parent_data = &(const struct clk_parent_data){
-			.hw = &gpucc_cxo_clk.clkr.hw,
+		.parent_hws = (const struct clk_hw*[]){
+			&gpucc_cxo_clk.clkr.hw,
 		},
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_ops,
@@ -134,8 +134,8 @@ static struct clk_branch gpucc_gfx3d_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gpucc_gfx3d_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &gfx3d_clk_src.rcg.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&gfx3d_clk_src.rcg.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
-- 
2.33.0

[PATCH 03/11] clk: qcom: camcc-sc7180: get rid of the test clock

[Dmitry Baryshkov]

The test clock isn't in the bindings and apparently it's not used by
anyone upstream.  Remove it.

Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/camcc-sc7180.c | 65 +++++++++++++--------------------
 1 file changed, 25 insertions(+), 40 deletions(-)

diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c
index ce73ee9037cb..3c15e551419f 100644
--- a/drivers/clk/qcom/camcc-sc7180.c
+++ b/drivers/clk/qcom/camcc-sc7180.c
@@ -29,7 +29,6 @@ enum {
 	P_CAM_CC_PLL2_OUT_AUX,
 	P_CAM_CC_PLL2_OUT_EARLY,
 	P_CAM_CC_PLL3_OUT_MAIN,
-	P_CORE_BI_PLL_TEST_SE,
 };
 
 static const struct pll_vco agera_vco[] = {
@@ -187,26 +186,22 @@ static const struct parent_map cam_cc_parent_map_0[] = {
 	{ P_BI_TCXO, 0 },
 	{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
 	{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
-	{ P_CORE_BI_PLL_TEST_SE, 7 },
 };
 
 static const struct clk_parent_data cam_cc_parent_data_0[] = {
 	{ .fw_name = "bi_tcxo" },
 	{ .hw = &cam_cc_pll1.clkr.hw },
 	{ .hw = &cam_cc_pll0.clkr.hw },
-	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 };
 
 static const struct parent_map cam_cc_parent_map_1[] = {
 	{ P_BI_TCXO, 0 },
 	{ P_CAM_CC_PLL2_OUT_AUX, 1 },
-	{ P_CORE_BI_PLL_TEST_SE, 7 },
 };
 
 static const struct clk_parent_data cam_cc_parent_data_1[] = {
 	{ .fw_name = "bi_tcxo" },
 	{ .hw = &cam_cc_pll2_out_aux.clkr.hw },
-	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 };
 
 static const struct parent_map cam_cc_parent_map_2[] = {
@@ -214,7 +209,6 @@ static const struct parent_map cam_cc_parent_map_2[] = {
 	{ P_CAM_CC_PLL2_OUT_EARLY, 4 },
 	{ P_CAM_CC_PLL3_OUT_MAIN, 5 },
 	{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
-	{ P_CORE_BI_PLL_TEST_SE, 7 },
 };
 
 static const struct clk_parent_data cam_cc_parent_data_2[] = {
@@ -222,7 +216,6 @@ static const struct clk_parent_data cam_cc_parent_data_2[] = {
 	{ .hw = &cam_cc_pll2_out_early.hw },
 	{ .hw = &cam_cc_pll3.clkr.hw },
 	{ .hw = &cam_cc_pll0.clkr.hw },
-	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 };
 
 static const struct parent_map cam_cc_parent_map_3[] = {
@@ -231,7 +224,6 @@ static const struct parent_map cam_cc_parent_map_3[] = {
 	{ P_CAM_CC_PLL2_OUT_EARLY, 4 },
 	{ P_CAM_CC_PLL3_OUT_MAIN, 5 },
 	{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
-	{ P_CORE_BI_PLL_TEST_SE, 7 },
 };
 
 static const struct clk_parent_data cam_cc_parent_data_3[] = {
@@ -240,33 +232,28 @@ static const struct clk_parent_data cam_cc_parent_data_3[] = {
 	{ .hw = &cam_cc_pll2_out_early.hw },
 	{ .hw = &cam_cc_pll3.clkr.hw },
 	{ .hw = &cam_cc_pll0.clkr.hw },
-	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 };
 
 static const struct parent_map cam_cc_parent_map_4[] = {
 	{ P_BI_TCXO, 0 },
 	{ P_CAM_CC_PLL3_OUT_MAIN, 5 },
 	{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
-	{ P_CORE_BI_PLL_TEST_SE, 7 },
 };
 
 static const struct clk_parent_data cam_cc_parent_data_4[] = {
 	{ .fw_name = "bi_tcxo" },
 	{ .hw = &cam_cc_pll3.clkr.hw },
 	{ .hw = &cam_cc_pll0.clkr.hw },
-	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 };
 
 static const struct parent_map cam_cc_parent_map_5[] = {
 	{ P_BI_TCXO, 0 },
 	{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
-	{ P_CORE_BI_PLL_TEST_SE, 7 },
 };
 
 static const struct clk_parent_data cam_cc_parent_data_5[] = {
 	{ .fw_name = "bi_tcxo" },
 	{ .hw = &cam_cc_pll0.clkr.hw },
-	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 };
 
 static const struct parent_map cam_cc_parent_map_6[] = {
@@ -274,7 +261,6 @@ static const struct parent_map cam_cc_parent_map_6[] = {
 	{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
 	{ P_CAM_CC_PLL3_OUT_MAIN, 5 },
 	{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
-	{ P_CORE_BI_PLL_TEST_SE, 7 },
 };
 
 static const struct clk_parent_data cam_cc_parent_data_6[] = {
@@ -282,7 +268,6 @@ static const struct clk_parent_data cam_cc_parent_data_6[] = {
 	{ .hw = &cam_cc_pll1.clkr.hw },
 	{ .hw = &cam_cc_pll3.clkr.hw },
 	{ .hw = &cam_cc_pll0.clkr.hw },
-	{ .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" },
 };
 
 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
@@ -303,7 +288,7 @@ static struct clk_rcg2 cam_cc_bps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_bps_clk_src",
 		.parent_data = cam_cc_parent_data_2,
-		.num_parents = 5,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -324,7 +309,7 @@ static struct clk_rcg2 cam_cc_cci_0_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_cci_0_clk_src",
 		.parent_data = cam_cc_parent_data_5,
-		.num_parents = 3,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -338,7 +323,7 @@ static struct clk_rcg2 cam_cc_cci_1_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_cci_1_clk_src",
 		.parent_data = cam_cc_parent_data_5,
-		.num_parents = 3,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -359,7 +344,7 @@ static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_cphy_rx_clk_src",
 		.parent_data = cam_cc_parent_data_3,
-		.num_parents = 6,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -378,7 +363,7 @@ static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_csi0phytimer_clk_src",
 		.parent_data = cam_cc_parent_data_0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -392,7 +377,7 @@ static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_csi1phytimer_clk_src",
 		.parent_data = cam_cc_parent_data_0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -406,7 +391,7 @@ static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_csi2phytimer_clk_src",
 		.parent_data = cam_cc_parent_data_0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -420,7 +405,7 @@ static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_csi3phytimer_clk_src",
 		.parent_data = cam_cc_parent_data_0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -442,7 +427,7 @@ static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_fast_ahb_clk_src",
 		.parent_data = cam_cc_parent_data_0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -465,7 +450,7 @@ static struct clk_rcg2 cam_cc_icp_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_icp_clk_src",
 		.parent_data = cam_cc_parent_data_2,
-		.num_parents = 5,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -487,7 +472,7 @@ static struct clk_rcg2 cam_cc_ife_0_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_ife_0_clk_src",
 		.parent_data = cam_cc_parent_data_4,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -509,7 +494,7 @@ static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_ife_0_csid_clk_src",
 		.parent_data = cam_cc_parent_data_3,
-		.num_parents = 6,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -523,7 +508,7 @@ static struct clk_rcg2 cam_cc_ife_1_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_ife_1_clk_src",
 		.parent_data = cam_cc_parent_data_4,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -537,7 +522,7 @@ static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_ife_1_csid_clk_src",
 		.parent_data = cam_cc_parent_data_3,
-		.num_parents = 6,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -551,7 +536,7 @@ static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_ife_lite_clk_src",
 		.parent_data = cam_cc_parent_data_4,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_rcg2_shared_ops,
 	},
@@ -566,7 +551,7 @@ static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_ife_lite_csid_clk_src",
 		.parent_data = cam_cc_parent_data_3,
-		.num_parents = 6,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -589,7 +574,7 @@ static struct clk_rcg2 cam_cc_ipe_0_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_ipe_0_clk_src",
 		.parent_data = cam_cc_parent_data_2,
-		.num_parents = 5,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -612,7 +597,7 @@ static struct clk_rcg2 cam_cc_jpeg_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_jpeg_clk_src",
 		.parent_data = cam_cc_parent_data_2,
-		.num_parents = 5,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -634,7 +619,7 @@ static struct clk_rcg2 cam_cc_lrme_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_lrme_clk_src",
 		.parent_data = cam_cc_parent_data_6,
-		.num_parents = 5,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -655,7 +640,7 @@ static struct clk_rcg2 cam_cc_mclk0_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_mclk0_clk_src",
 		.parent_data = cam_cc_parent_data_1,
-		.num_parents = 3,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -669,7 +654,7 @@ static struct clk_rcg2 cam_cc_mclk1_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_mclk1_clk_src",
 		.parent_data = cam_cc_parent_data_1,
-		.num_parents = 3,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -683,7 +668,7 @@ static struct clk_rcg2 cam_cc_mclk2_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_mclk2_clk_src",
 		.parent_data = cam_cc_parent_data_1,
-		.num_parents = 3,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -697,7 +682,7 @@ static struct clk_rcg2 cam_cc_mclk3_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_mclk3_clk_src",
 		.parent_data = cam_cc_parent_data_1,
-		.num_parents = 3,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -711,7 +696,7 @@ static struct clk_rcg2 cam_cc_mclk4_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_mclk4_clk_src",
 		.parent_data = cam_cc_parent_data_1,
-		.num_parents = 3,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -730,7 +715,7 @@ static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_slow_ahb_clk_src",
 		.parent_data = cam_cc_parent_data_0,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 		.ops = &clk_rcg2_shared_ops,
 	},
-- 
2.33.0

[PATCH 04/11] clk: qcom: camcc-sdm845: get rid of the test clock

[Dmitry Baryshkov]

The test clock isn't in the bindings and apparently it's not used by
anyone upstream.  Remove it.

Suggested-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/camcc-sdm845.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/clk/qcom/camcc-sdm845.c b/drivers/clk/qcom/camcc-sdm845.c
index 1b2cefef7431..545c288a7f98 100644
--- a/drivers/clk/qcom/camcc-sdm845.c
+++ b/drivers/clk/qcom/camcc-sdm845.c
@@ -23,7 +23,6 @@ enum {
 	P_CAM_CC_PLL1_OUT_EVEN,
 	P_CAM_CC_PLL2_OUT_EVEN,
 	P_CAM_CC_PLL3_OUT_EVEN,
-	P_CORE_BI_PLL_TEST_SE,
 };
 
 static const struct parent_map cam_cc_parent_map_0[] = {
@@ -32,7 +31,6 @@ static const struct parent_map cam_cc_parent_map_0[] = {
 	{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
 	{ P_CAM_CC_PLL3_OUT_EVEN, 5 },
 	{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
-	{ P_CORE_BI_PLL_TEST_SE, 7 },
 };
 
 static const char * const cam_cc_parent_names_0[] = {
@@ -41,7 +39,6 @@ static const char * const cam_cc_parent_names_0[] = {
 	"cam_cc_pll1_out_even",
 	"cam_cc_pll3_out_even",
 	"cam_cc_pll0_out_even",
-	"core_bi_pll_test_se",
 };
 
 static struct clk_alpha_pll cam_cc_pll0 = {
-- 
2.33.0

[PATCH 05/11] clk: qcom: camcc-sdm845: convert to parent data

[Dmitry Baryshkov]

Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/camcc-sdm845.c | 320 +++++++++++++++++---------------
 1 file changed, 168 insertions(+), 152 deletions(-)

diff --git a/drivers/clk/qcom/camcc-sdm845.c b/drivers/clk/qcom/camcc-sdm845.c
index 545c288a7f98..be3f95326965 100644
--- a/drivers/clk/qcom/camcc-sdm845.c
+++ b/drivers/clk/qcom/camcc-sdm845.c
@@ -25,29 +25,15 @@ enum {
 	P_CAM_CC_PLL3_OUT_EVEN,
 };
 
-static const struct parent_map cam_cc_parent_map_0[] = {
-	{ P_BI_TCXO, 0 },
-	{ P_CAM_CC_PLL2_OUT_EVEN, 1 },
-	{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
-	{ P_CAM_CC_PLL3_OUT_EVEN, 5 },
-	{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
-};
-
-static const char * const cam_cc_parent_names_0[] = {
-	"bi_tcxo",
-	"cam_cc_pll2_out_even",
-	"cam_cc_pll1_out_even",
-	"cam_cc_pll3_out_even",
-	"cam_cc_pll0_out_even",
-};
-
 static struct clk_alpha_pll cam_cc_pll0 = {
 	.offset = 0x0,
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 	.clkr = {
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_pll0",
-			.parent_names = (const char *[]){ "bi_tcxo" },
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "bi_tcxo", .name = "bi_tcxo",
+			},
 			.num_parents = 1,
 			.ops = &clk_alpha_pll_fabia_ops,
 		},
@@ -69,7 +55,9 @@ static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_pll0_out_even",
-		.parent_names = (const char *[]){ "cam_cc_pll0" },
+		.parent_hws = (const struct clk_hw*[]){
+			&cam_cc_pll0.clkr.hw,
+		},
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_fabia_ops,
 	},
@@ -81,7 +69,9 @@ static struct clk_alpha_pll cam_cc_pll1 = {
 	.clkr = {
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_pll1",
-			.parent_names = (const char *[]){ "bi_tcxo" },
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "bi_tcxo", .name = "bi_tcxo",
+			},
 			.num_parents = 1,
 			.ops = &clk_alpha_pll_fabia_ops,
 		},
@@ -97,7 +87,9 @@ static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_pll1_out_even",
-		.parent_names = (const char *[]){ "cam_cc_pll1" },
+		.parent_hws = (const struct clk_hw*[]){
+			&cam_cc_pll1.clkr.hw,
+		},
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_fabia_ops,
 	},
@@ -109,7 +101,9 @@ static struct clk_alpha_pll cam_cc_pll2 = {
 	.clkr = {
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_pll2",
-			.parent_names = (const char *[]){ "bi_tcxo" },
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "bi_tcxo", .name = "bi_tcxo",
+			},
 			.num_parents = 1,
 			.ops = &clk_alpha_pll_fabia_ops,
 		},
@@ -125,7 +119,9 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even = {
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_pll2_out_even",
-		.parent_names = (const char *[]){ "cam_cc_pll2" },
+		.parent_hws = (const struct clk_hw*[]){
+			&cam_cc_pll2.clkr.hw,
+		},
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_fabia_ops,
 	},
@@ -137,7 +133,9 @@ static struct clk_alpha_pll cam_cc_pll3 = {
 	.clkr = {
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_pll3",
-			.parent_names = (const char *[]){ "bi_tcxo" },
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "bi_tcxo", .name = "bi_tcxo",
+			},
 			.num_parents = 1,
 			.ops = &clk_alpha_pll_fabia_ops,
 		},
@@ -153,12 +151,30 @@ static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_pll3_out_even",
-		.parent_names = (const char *[]){ "cam_cc_pll3" },
+		.parent_hws = (const struct clk_hw*[]){
+			&cam_cc_pll3.clkr.hw,
+		},
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_fabia_ops,
 	},
 };
 
+static const struct parent_map cam_cc_parent_map_0[] = {
+	{ P_BI_TCXO, 0 },
+	{ P_CAM_CC_PLL2_OUT_EVEN, 1 },
+	{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
+	{ P_CAM_CC_PLL3_OUT_EVEN, 5 },
+	{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data cam_cc_parent_data_0[] = {
+	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
+	{ .hw = &cam_cc_pll2_out_even.clkr.hw },
+	{ .hw = &cam_cc_pll1_out_even.clkr.hw },
+	{ .hw = &cam_cc_pll3_out_even.clkr.hw },
+	{ .hw = &cam_cc_pll0_out_even.clkr.hw },
+};
+
 static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
 	F(19200000, P_BI_TCXO, 1, 0, 0),
 	F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
@@ -186,8 +202,8 @@ static struct clk_rcg2 cam_cc_bps_clk_src = {
 	.freq_tbl = ftbl_cam_cc_bps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_bps_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_rcg2_shared_ops,
 	},
@@ -209,8 +225,8 @@ static struct clk_rcg2 cam_cc_cci_clk_src = {
 	.freq_tbl = ftbl_cam_cc_cci_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_cci_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -229,8 +245,8 @@ static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
 	.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_cphy_rx_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -250,8 +266,8 @@ static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
 	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_csi0phytimer_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_rcg2_ops,
 	},
@@ -265,8 +281,8 @@ static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
 	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_csi1phytimer_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_rcg2_ops,
 	},
@@ -280,8 +296,8 @@ static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
 	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_csi2phytimer_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_rcg2_ops,
 	},
@@ -295,8 +311,8 @@ static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
 	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_csi3phytimer_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_rcg2_ops,
 	},
@@ -320,8 +336,8 @@ static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
 	.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_fast_ahb_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -343,8 +359,8 @@ static struct clk_rcg2 cam_cc_fd_core_clk_src = {
 	.freq_tbl = ftbl_cam_cc_fd_core_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_fd_core_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -366,8 +382,8 @@ static struct clk_rcg2 cam_cc_icp_clk_src = {
 	.freq_tbl = ftbl_cam_cc_icp_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_icp_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -390,8 +406,8 @@ static struct clk_rcg2 cam_cc_ife_0_clk_src = {
 	.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_ife_0_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_rcg2_shared_ops,
 	},
@@ -413,8 +429,8 @@ static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
 	.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_ife_0_csid_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -427,8 +443,8 @@ static struct clk_rcg2 cam_cc_ife_1_clk_src = {
 	.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_ife_1_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_rcg2_shared_ops,
 	},
@@ -442,8 +458,8 @@ static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
 	.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_ife_1_csid_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -456,8 +472,8 @@ static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
 	.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_ife_lite_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_rcg2_shared_ops,
 	},
@@ -471,8 +487,8 @@ static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
 	.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_ife_lite_csid_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.ops = &clk_rcg2_shared_ops,
 	},
 };
@@ -496,8 +512,8 @@ static struct clk_rcg2 cam_cc_ipe_0_clk_src = {
 	.freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_ipe_0_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_rcg2_shared_ops,
 	},
@@ -511,8 +527,8 @@ static struct clk_rcg2 cam_cc_ipe_1_clk_src = {
 	.freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_ipe_1_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_rcg2_shared_ops,
 	},
@@ -526,8 +542,8 @@ static struct clk_rcg2 cam_cc_jpeg_clk_src = {
 	.freq_tbl = ftbl_cam_cc_bps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_jpeg_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_rcg2_shared_ops,
 	},
@@ -551,8 +567,8 @@ static struct clk_rcg2 cam_cc_lrme_clk_src = {
 	.freq_tbl = ftbl_cam_cc_lrme_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_lrme_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_rcg2_shared_ops,
 	},
@@ -574,8 +590,8 @@ static struct clk_rcg2 cam_cc_mclk0_clk_src = {
 	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_mclk0_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_rcg2_ops,
 	},
@@ -589,8 +605,8 @@ static struct clk_rcg2 cam_cc_mclk1_clk_src = {
 	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_mclk1_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_rcg2_ops,
 	},
@@ -604,8 +620,8 @@ static struct clk_rcg2 cam_cc_mclk2_clk_src = {
 	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_mclk2_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_rcg2_ops,
 	},
@@ -619,8 +635,8 @@ static struct clk_rcg2 cam_cc_mclk3_clk_src = {
 	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_mclk3_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_rcg2_ops,
 	},
@@ -643,8 +659,8 @@ static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
 	.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_slow_ahb_clk_src",
-		.parent_names = cam_cc_parent_names_0,
-		.num_parents = 6,
+		.parent_data = cam_cc_parent_data_0,
+		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_rcg2_ops,
 	},
@@ -658,8 +674,8 @@ static struct clk_branch cam_cc_bps_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_bps_ahb_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_slow_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_slow_ahb_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -676,8 +692,8 @@ static struct clk_branch cam_cc_bps_areg_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_bps_areg_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_fast_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_fast_ahb_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -707,8 +723,8 @@ static struct clk_branch cam_cc_bps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_bps_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_bps_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_bps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -751,8 +767,8 @@ static struct clk_branch cam_cc_cci_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_cci_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_cci_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_cci_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -769,8 +785,8 @@ static struct clk_branch cam_cc_cpas_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_cpas_ahb_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_slow_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_slow_ahb_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -787,8 +803,8 @@ static struct clk_branch cam_cc_csi0phytimer_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_csi0phytimer_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_csi0phytimer_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_csi0phytimer_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -805,8 +821,8 @@ static struct clk_branch cam_cc_csi1phytimer_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_csi1phytimer_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_csi1phytimer_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_csi1phytimer_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -823,8 +839,8 @@ static struct clk_branch cam_cc_csi2phytimer_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_csi2phytimer_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_csi2phytimer_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_csi2phytimer_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -841,8 +857,8 @@ static struct clk_branch cam_cc_csi3phytimer_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_csi3phytimer_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_csi3phytimer_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_csi3phytimer_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -859,8 +875,8 @@ static struct clk_branch cam_cc_csiphy0_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_csiphy0_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_cphy_rx_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_cphy_rx_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -877,8 +893,8 @@ static struct clk_branch cam_cc_csiphy1_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_csiphy1_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_cphy_rx_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_cphy_rx_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -895,8 +911,8 @@ static struct clk_branch cam_cc_csiphy2_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_csiphy2_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_cphy_rx_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_cphy_rx_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -913,8 +929,8 @@ static struct clk_branch cam_cc_csiphy3_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_csiphy3_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_cphy_rx_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_cphy_rx_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -931,8 +947,8 @@ static struct clk_branch cam_cc_fd_core_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_fd_core_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_fd_core_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_fd_core_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -949,8 +965,8 @@ static struct clk_branch cam_cc_fd_core_uar_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_fd_core_uar_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_fd_core_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_fd_core_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -992,8 +1008,8 @@ static struct clk_branch cam_cc_icp_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_icp_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_icp_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_icp_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1049,8 +1065,8 @@ static struct clk_branch cam_cc_ife_0_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ife_0_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_ife_0_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_ife_0_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1067,8 +1083,8 @@ static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ife_0_cphy_rx_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_cphy_rx_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_cphy_rx_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1085,8 +1101,8 @@ static struct clk_branch cam_cc_ife_0_csid_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ife_0_csid_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_ife_0_csid_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_ife_0_csid_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1103,8 +1119,8 @@ static struct clk_branch cam_cc_ife_0_dsp_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ife_0_dsp_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_ife_0_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_ife_0_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1133,8 +1149,8 @@ static struct clk_branch cam_cc_ife_1_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ife_1_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_ife_1_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_ife_1_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1151,8 +1167,8 @@ static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ife_1_cphy_rx_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_cphy_rx_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_cphy_rx_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1169,8 +1185,8 @@ static struct clk_branch cam_cc_ife_1_csid_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ife_1_csid_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_ife_1_csid_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_ife_1_csid_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1187,8 +1203,8 @@ static struct clk_branch cam_cc_ife_1_dsp_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ife_1_dsp_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_ife_1_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_ife_1_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
@@ -1204,8 +1220,8 @@ static struct clk_branch cam_cc_ife_lite_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ife_lite_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_ife_lite_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_ife_lite_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1222,8 +1238,8 @@ static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ife_lite_cphy_rx_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_cphy_rx_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_cphy_rx_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1240,8 +1256,8 @@ static struct clk_branch cam_cc_ife_lite_csid_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ife_lite_csid_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_ife_lite_csid_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_ife_lite_csid_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1258,8 +1274,8 @@ static struct clk_branch cam_cc_ipe_0_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ipe_0_ahb_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_slow_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_slow_ahb_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1276,8 +1292,8 @@ static struct clk_branch cam_cc_ipe_0_areg_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ipe_0_areg_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_fast_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_fast_ahb_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1307,8 +1323,8 @@ static struct clk_branch cam_cc_ipe_0_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ipe_0_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_ipe_0_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_ipe_0_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1325,8 +1341,8 @@ static struct clk_branch cam_cc_ipe_1_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ipe_1_ahb_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_slow_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_slow_ahb_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1343,8 +1359,8 @@ static struct clk_branch cam_cc_ipe_1_areg_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ipe_1_areg_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_fast_ahb_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_fast_ahb_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1374,8 +1390,8 @@ static struct clk_branch cam_cc_ipe_1_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ipe_1_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_ipe_1_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_ipe_1_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1392,8 +1408,8 @@ static struct clk_branch cam_cc_jpeg_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_jpeg_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_jpeg_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_jpeg_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1410,8 +1426,8 @@ static struct clk_branch cam_cc_lrme_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_lrme_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_lrme_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_lrme_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1428,8 +1444,8 @@ static struct clk_branch cam_cc_mclk0_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_mclk0_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_mclk0_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_mclk0_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1446,8 +1462,8 @@ static struct clk_branch cam_cc_mclk1_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_mclk1_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_mclk1_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_mclk1_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1464,8 +1480,8 @@ static struct clk_branch cam_cc_mclk2_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_mclk2_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_mclk2_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_mclk2_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1482,8 +1498,8 @@ static struct clk_branch cam_cc_mclk3_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_mclk3_clk",
-			.parent_names = (const char *[]){
-				"cam_cc_mclk3_clk_src",
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_mclk3_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
-- 
2.33.0

[PATCH 06/11] clk: qcom: camcc-sc7180: use parent_hws instead of parent_data

[Dmitry Baryshkov]

If all parents are specified as clk_hw, we can use parent_hws instead of
parent_data.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/camcc-sc7180.c | 156 ++++++++++++++++----------------
 1 file changed, 79 insertions(+), 77 deletions(-)

diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c
index 3c15e551419f..e2b4804695f3 100644
--- a/drivers/clk/qcom/camcc-sc7180.c
+++ b/drivers/clk/qcom/camcc-sc7180.c
@@ -126,7 +126,9 @@ static struct clk_fixed_factor cam_cc_pll2_out_early = {
 	.div = 2,
 	.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_pll2_out_early",
-		.parent_names = (const char *[]){ "cam_cc_pll2" },
+		.parent_hws = (const struct clk_hw*[]){
+			&cam_cc_pll2.clkr.hw,
+		},
 		.num_parents = 1,
 		.ops = &clk_fixed_factor_ops,
 	},
@@ -146,8 +148,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux = {
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA],
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "cam_cc_pll2_out_aux",
-		.parent_data = &(const struct clk_parent_data){
-			.hw = &cam_cc_pll2.clkr.hw,
+		.parent_hws = (const struct clk_hw*[]){
+			&cam_cc_pll2.clkr.hw,
 		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
@@ -729,8 +731,8 @@ static struct clk_branch cam_cc_bps_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_bps_ahb_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_slow_ahb_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -747,8 +749,8 @@ static struct clk_branch cam_cc_bps_areg_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_bps_areg_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_fast_ahb_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -778,8 +780,8 @@ static struct clk_branch cam_cc_bps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_bps_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_bps_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_bps_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -809,8 +811,8 @@ static struct clk_branch cam_cc_cci_0_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_cci_0_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_cci_0_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_cci_0_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -827,8 +829,8 @@ static struct clk_branch cam_cc_cci_1_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_cci_1_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_cci_1_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_cci_1_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -845,8 +847,8 @@ static struct clk_branch cam_cc_core_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_core_ahb_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_slow_ahb_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -863,8 +865,8 @@ static struct clk_branch cam_cc_cpas_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_cpas_ahb_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_slow_ahb_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -881,8 +883,8 @@ static struct clk_branch cam_cc_csi0phytimer_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_csi0phytimer_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_csi0phytimer_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_csi0phytimer_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -899,8 +901,8 @@ static struct clk_branch cam_cc_csi1phytimer_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_csi1phytimer_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_csi1phytimer_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_csi1phytimer_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -917,8 +919,8 @@ static struct clk_branch cam_cc_csi2phytimer_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_csi2phytimer_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_csi2phytimer_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_csi2phytimer_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -935,8 +937,8 @@ static struct clk_branch cam_cc_csi3phytimer_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_csi3phytimer_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_csi3phytimer_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_csi3phytimer_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -953,8 +955,8 @@ static struct clk_branch cam_cc_csiphy0_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_csiphy0_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_cphy_rx_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -971,8 +973,8 @@ static struct clk_branch cam_cc_csiphy1_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_csiphy1_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_cphy_rx_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -989,8 +991,8 @@ static struct clk_branch cam_cc_csiphy2_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_csiphy2_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_cphy_rx_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1007,8 +1009,8 @@ static struct clk_branch cam_cc_csiphy3_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_csiphy3_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_cphy_rx_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1025,8 +1027,8 @@ static struct clk_branch cam_cc_icp_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_icp_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_icp_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_icp_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1056,8 +1058,8 @@ static struct clk_branch cam_cc_ife_0_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ife_0_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_ife_0_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_ife_0_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1074,8 +1076,8 @@ static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ife_0_cphy_rx_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_cphy_rx_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1092,8 +1094,8 @@ static struct clk_branch cam_cc_ife_0_csid_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ife_0_csid_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_ife_0_csid_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_ife_0_csid_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1110,8 +1112,8 @@ static struct clk_branch cam_cc_ife_0_dsp_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ife_0_dsp_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_ife_0_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_ife_0_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1141,8 +1143,8 @@ static struct clk_branch cam_cc_ife_1_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ife_1_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_ife_1_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_ife_1_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1159,8 +1161,8 @@ static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ife_1_cphy_rx_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_cphy_rx_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1177,8 +1179,8 @@ static struct clk_branch cam_cc_ife_1_csid_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ife_1_csid_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_ife_1_csid_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_ife_1_csid_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1195,8 +1197,8 @@ static struct clk_branch cam_cc_ife_1_dsp_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ife_1_dsp_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_ife_1_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_ife_1_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1213,8 +1215,8 @@ static struct clk_branch cam_cc_ife_lite_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ife_lite_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_ife_lite_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_ife_lite_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1231,8 +1233,8 @@ static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ife_lite_cphy_rx_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_cphy_rx_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1249,8 +1251,8 @@ static struct clk_branch cam_cc_ife_lite_csid_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ife_lite_csid_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_ife_lite_csid_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_ife_lite_csid_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1267,8 +1269,8 @@ static struct clk_branch cam_cc_ipe_0_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ipe_0_ahb_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_slow_ahb_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1285,8 +1287,8 @@ static struct clk_branch cam_cc_ipe_0_areg_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ipe_0_areg_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_fast_ahb_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1316,8 +1318,8 @@ static struct clk_branch cam_cc_ipe_0_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_ipe_0_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_ipe_0_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_ipe_0_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1334,8 +1336,8 @@ static struct clk_branch cam_cc_jpeg_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_jpeg_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_jpeg_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_jpeg_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1352,8 +1354,8 @@ static struct clk_branch cam_cc_lrme_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_lrme_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_lrme_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_lrme_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1370,8 +1372,8 @@ static struct clk_branch cam_cc_mclk0_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_mclk0_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_mclk0_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_mclk0_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1388,8 +1390,8 @@ static struct clk_branch cam_cc_mclk1_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_mclk1_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_mclk1_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_mclk1_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1406,8 +1408,8 @@ static struct clk_branch cam_cc_mclk2_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_mclk2_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_mclk2_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_mclk2_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1424,8 +1426,8 @@ static struct clk_branch cam_cc_mclk3_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_mclk3_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_mclk3_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_mclk3_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -1442,8 +1444,8 @@ static struct clk_branch cam_cc_mclk4_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "cam_cc_mclk4_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &cam_cc_mclk4_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&cam_cc_mclk4_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
-- 
2.33.0

[PATCH 07/11] clk: qcom: videocc-sc7180: use parent_hws instead of parent_data

[Dmitry Baryshkov]

If all parents are specified as clk_hw, we can use parent_hws instead of
parent_data.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/videocc-sc7180.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/qcom/videocc-sc7180.c b/drivers/clk/qcom/videocc-sc7180.c
index ed57bbb19f88..5b9b54f616b8 100644
--- a/drivers/clk/qcom/videocc-sc7180.c
+++ b/drivers/clk/qcom/videocc-sc7180.c
@@ -99,8 +99,8 @@ static struct clk_branch video_cc_vcodec0_core_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "video_cc_vcodec0_core_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &video_cc_venus_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&video_cc_venus_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
@@ -143,8 +143,8 @@ static struct clk_branch video_cc_venus_ctl_core_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "video_cc_venus_ctl_core_clk",
-			.parent_data = &(const struct clk_parent_data){
-				.hw = &video_cc_venus_clk_src.clkr.hw,
+			.parent_hws = (const struct clk_hw*[]){
+				&video_cc_venus_clk_src.clkr.hw,
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
-- 
2.33.0

[PATCH 08/11] clk: qcom: gcc-msm8996: drop unsupported clock sources

[Dmitry Baryshkov]

In preparation of updating the msm8996 gcc driver, drop all unsupported
GPLL sources (gpll1/gpll1_early_div, gpll2/gpll2_early and gpll3).
Downstream kernel also does not provide support for these GPLL sources,
so it is safe to drop them.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/gcc-msm8996.c | 55 ++++------------------------------
 1 file changed, 6 insertions(+), 49 deletions(-)

diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index 9b1674b28d45..3acefe16355c 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -27,15 +27,10 @@
 enum {
 	P_XO,
 	P_GPLL0,
-	P_GPLL2,
-	P_GPLL3,
-	P_GPLL1,
-	P_GPLL2_EARLY,
 	P_GPLL0_EARLY_DIV,
 	P_SLEEP_CLK,
 	P_GPLL4,
 	P_AUD_REF_CLK,
-	P_GPLL1_EARLY_DIV
 };
 
 static const struct parent_map gcc_sleep_clk_map[] = {
@@ -130,44 +125,6 @@ static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
 	"gpll0_early_div"
 };
 
-static const struct parent_map gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map[] = {
-	{ P_XO, 0 },
-	{ P_GPLL0, 1 },
-	{ P_GPLL1_EARLY_DIV, 3 },
-	{ P_GPLL1, 4 },
-	{ P_GPLL4, 5 },
-	{ P_GPLL0_EARLY_DIV, 6 }
-};
-
-static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div[] = {
-	"xo",
-	"gpll0",
-	"gpll1_early_div",
-	"gpll1",
-	"gpll4",
-	"gpll0_early_div"
-};
-
-static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map[] = {
-	{ P_XO, 0 },
-	{ P_GPLL0, 1 },
-	{ P_GPLL2, 2 },
-	{ P_GPLL3, 3 },
-	{ P_GPLL1, 4 },
-	{ P_GPLL2_EARLY, 5 },
-	{ P_GPLL0_EARLY_DIV, 6 }
-};
-
-static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div[] = {
-	"xo",
-	"gpll0",
-	"gpll2",
-	"gpll3",
-	"gpll1",
-	"gpll2_early",
-	"gpll0_early_div"
-};
-
 static struct clk_fixed_factor xo = {
 	.mult = 1,
 	.div = 1,
@@ -285,12 +242,12 @@ static const struct freq_tbl ftbl_system_noc_clk_src[] = {
 static struct clk_rcg2 system_noc_clk_src = {
 	.cmd_rcgr = 0x0401c,
 	.hid_width = 5,
-	.parent_map = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map,
+	.parent_map = gcc_xo_gpll0_gpll0_early_div_map,
 	.freq_tbl = ftbl_system_noc_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "system_noc_clk_src",
-		.parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div,
-		.num_parents = 7,
+		.parent_names = gcc_xo_gpll0_gpll0_early_div,
+		.num_parents = 3,
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -1257,12 +1214,12 @@ static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
 static struct clk_rcg2 qspi_ser_clk_src = {
 	.cmd_rcgr = 0x8b00c,
 	.hid_width = 5,
-	.parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map,
+	.parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
 	.freq_tbl = ftbl_qspi_ser_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "qspi_ser_clk_src",
-		.parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
-		.num_parents = 6,
+		.parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
+		.num_parents = 4,
 		.ops = &clk_rcg2_ops,
 	},
 };
-- 
2.33.0

[PATCH 09/11] clk: qcom: gcc-msm8996: move clock parent tables down

[Dmitry Baryshkov]

Move clock parent tables down, after the GPLL declrataions, so that we
can use gpll hw clock fields in the next commit.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/gcc-msm8996.c | 184 ++++++++++++++++-----------------
 1 file changed, 92 insertions(+), 92 deletions(-)

diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index 3acefe16355c..c2f9ae729d1e 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -33,98 +33,6 @@ enum {
 	P_AUD_REF_CLK,
 };
 
-static const struct parent_map gcc_sleep_clk_map[] = {
-	{ P_SLEEP_CLK, 5 }
-};
-
-static const char * const gcc_sleep_clk[] = {
-	"sleep_clk"
-};
-
-static const struct parent_map gcc_xo_gpll0_map[] = {
-	{ P_XO, 0 },
-	{ P_GPLL0, 1 }
-};
-
-static const char * const gcc_xo_gpll0[] = {
-	"xo",
-	"gpll0"
-};
-
-static const struct parent_map gcc_xo_sleep_clk_map[] = {
-	{ P_XO, 0 },
-	{ P_SLEEP_CLK, 5 }
-};
-
-static const char * const gcc_xo_sleep_clk[] = {
-	"xo",
-	"sleep_clk"
-};
-
-static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
-	{ P_XO, 0 },
-	{ P_GPLL0, 1 },
-	{ P_GPLL0_EARLY_DIV, 6 }
-};
-
-static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
-	"xo",
-	"gpll0",
-	"gpll0_early_div"
-};
-
-static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
-	{ P_XO, 0 },
-	{ P_GPLL0, 1 },
-	{ P_GPLL4, 5 }
-};
-
-static const char * const gcc_xo_gpll0_gpll4[] = {
-	"xo",
-	"gpll0",
-	"gpll4"
-};
-
-static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
-	{ P_XO, 0 },
-	{ P_GPLL0, 1 },
-	{ P_AUD_REF_CLK, 2 }
-};
-
-static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
-	"xo",
-	"gpll0",
-	"aud_ref_clk"
-};
-
-static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
-	{ P_XO, 0 },
-	{ P_GPLL0, 1 },
-	{ P_SLEEP_CLK, 5 },
-	{ P_GPLL0_EARLY_DIV, 6 }
-};
-
-static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
-	"xo",
-	"gpll0",
-	"sleep_clk",
-	"gpll0_early_div"
-};
-
-static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
-	{ P_XO, 0 },
-	{ P_GPLL0, 1 },
-	{ P_GPLL4, 5 },
-	{ P_GPLL0_EARLY_DIV, 6 }
-};
-
-static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
-	"xo",
-	"gpll0",
-	"gpll4",
-	"gpll0_early_div"
-};
-
 static struct clk_fixed_factor xo = {
 	.mult = 1,
 	.div = 1,
@@ -229,6 +137,98 @@ static struct clk_alpha_pll_postdiv gpll4 = {
 	},
 };
 
+static const struct parent_map gcc_sleep_clk_map[] = {
+	{ P_SLEEP_CLK, 5 }
+};
+
+static const char * const gcc_sleep_clk[] = {
+	"sleep_clk"
+};
+
+static const struct parent_map gcc_xo_gpll0_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL0, 1 }
+};
+
+static const char * const gcc_xo_gpll0[] = {
+	"xo",
+	"gpll0"
+};
+
+static const struct parent_map gcc_xo_sleep_clk_map[] = {
+	{ P_XO, 0 },
+	{ P_SLEEP_CLK, 5 }
+};
+
+static const char * const gcc_xo_sleep_clk[] = {
+	"xo",
+	"sleep_clk"
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL0, 1 },
+	{ P_GPLL0_EARLY_DIV, 6 }
+};
+
+static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
+	"xo",
+	"gpll0",
+	"gpll0_early_div"
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL0, 1 },
+	{ P_GPLL4, 5 }
+};
+
+static const char * const gcc_xo_gpll0_gpll4[] = {
+	"xo",
+	"gpll0",
+	"gpll4"
+};
+
+static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL0, 1 },
+	{ P_AUD_REF_CLK, 2 }
+};
+
+static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
+	"xo",
+	"gpll0",
+	"aud_ref_clk"
+};
+
+static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL0, 1 },
+	{ P_SLEEP_CLK, 5 },
+	{ P_GPLL0_EARLY_DIV, 6 }
+};
+
+static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
+	"xo",
+	"gpll0",
+	"sleep_clk",
+	"gpll0_early_div"
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL0, 1 },
+	{ P_GPLL4, 5 },
+	{ P_GPLL0_EARLY_DIV, 6 }
+};
+
+static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
+	"xo",
+	"gpll0",
+	"gpll4",
+	"gpll0_early_div"
+};
+
 static const struct freq_tbl ftbl_system_noc_clk_src[] = {
 	F(19200000, P_XO, 1, 0, 0),
 	F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
-- 
2.33.0

[PATCH 10/11] clk: qcom: gcc-msm8996: use parent_hws/_data instead of parent_names

[Dmitry Baryshkov]

Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/gcc-msm8996.c | 678 ++++++++++++++++++++++-----------
 1 file changed, 463 insertions(+), 215 deletions(-)

diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index c2f9ae729d1e..186e682e730f 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -38,7 +38,9 @@ static struct clk_fixed_factor xo = {
 	.div = 1,
 	.hw.init = &(struct clk_init_data){
 		.name = "xo",
-		.parent_names = (const char *[]){ "xo_board" },
+		.parent_data = &(const struct clk_parent_data){
+			.fw_name = "cxo", .name = "xo_board",
+		},
 		.num_parents = 1,
 		.ops = &clk_fixed_factor_ops,
 	},
@@ -52,7 +54,9 @@ static struct clk_alpha_pll gpll0_early = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gpll0_early",
-			.parent_names = (const char *[]){ "xo" },
+			.parent_hws = (const struct clk_hw*[]){
+				&xo.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_alpha_pll_ops,
 		},
@@ -64,7 +68,9 @@ static struct clk_fixed_factor gpll0_early_div = {
 	.div = 2,
 	.hw.init = &(struct clk_init_data){
 		.name = "gpll0_early_div",
-		.parent_names = (const char *[]){ "gpll0_early" },
+		.parent_hws = (const struct clk_hw*[]){
+			&gpll0_early.clkr.hw,
+		},
 		.num_parents = 1,
 		.ops = &clk_fixed_factor_ops,
 	},
@@ -75,7 +81,9 @@ static struct clk_alpha_pll_postdiv gpll0 = {
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gpll0",
-		.parent_names = (const char *[]){ "gpll0_early" },
+		.parent_hws = (const struct clk_hw*[]){
+			&gpll0_early.clkr.hw,
+		},
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_ops,
 	},
@@ -88,7 +96,9 @@ static struct clk_branch gcc_mmss_gpll0_div_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_mmss_gpll0_div_clk",
-			.parent_names = (const char *[]){ "gpll0" },
+			.parent_hws = (const struct clk_hw*[]){
+				&gpll0.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -103,7 +113,9 @@ static struct clk_branch gcc_mss_gpll0_div_clk = {
 		.enable_mask = BIT(2),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_mss_gpll0_div_clk",
-			.parent_names = (const char *[]){ "gpll0" },
+			.parent_hws = (const struct clk_hw*[]){
+				&gpll0.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops
@@ -119,7 +131,9 @@ static struct clk_alpha_pll gpll4_early = {
 		.enable_mask = BIT(4),
 		.hw.init = &(struct clk_init_data){
 			.name = "gpll4_early",
-			.parent_names = (const char *[]){ "xo" },
+			.parent_hws = (const struct clk_hw*[]){
+				&xo.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_alpha_pll_ops,
 		},
@@ -131,7 +145,9 @@ static struct clk_alpha_pll_postdiv gpll4 = {
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gpll4",
-		.parent_names = (const char *[]){ "gpll4_early" },
+		.parent_hws = (const struct clk_hw*[]){
+			&gpll4_early.clkr.hw,
+		},
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_ops,
 	},
@@ -141,8 +157,8 @@ static const struct parent_map gcc_sleep_clk_map[] = {
 	{ P_SLEEP_CLK, 5 }
 };
 
-static const char * const gcc_sleep_clk[] = {
-	"sleep_clk"
+static const struct clk_parent_data gcc_sleep_clk[] = {
+	{ .fw_name = "sleep_clk", .name = "sleep_clk" }
 };
 
 static const struct parent_map gcc_xo_gpll0_map[] = {
@@ -150,9 +166,9 @@ static const struct parent_map gcc_xo_gpll0_map[] = {
 	{ P_GPLL0, 1 }
 };
 
-static const char * const gcc_xo_gpll0[] = {
-	"xo",
-	"gpll0"
+static const struct clk_parent_data gcc_xo_gpll0[] = {
+	{ .hw = &xo.hw },
+	{ .hw = &gpll0.clkr.hw }
 };
 
 static const struct parent_map gcc_xo_sleep_clk_map[] = {
@@ -160,9 +176,9 @@ static const struct parent_map gcc_xo_sleep_clk_map[] = {
 	{ P_SLEEP_CLK, 5 }
 };
 
-static const char * const gcc_xo_sleep_clk[] = {
-	"xo",
-	"sleep_clk"
+static const struct clk_parent_data gcc_xo_sleep_clk[] = {
+	{ .hw = &xo.hw },
+	{ .fw_name = "sleep_clk", .name = "sleep_clk" }
 };
 
 static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
@@ -171,10 +187,10 @@ static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
 	{ P_GPLL0_EARLY_DIV, 6 }
 };
 
-static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
-	"xo",
-	"gpll0",
-	"gpll0_early_div"
+static const struct clk_parent_data gcc_xo_gpll0_gpll0_early_div[] = {
+	{ .hw = &xo.hw },
+	{ .hw = &gpll0.clkr.hw },
+	{ .hw = &gpll0_early_div.hw }
 };
 
 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
@@ -183,10 +199,10 @@ static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
 	{ P_GPLL4, 5 }
 };
 
-static const char * const gcc_xo_gpll0_gpll4[] = {
-	"xo",
-	"gpll0",
-	"gpll4"
+static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
+	{ .hw = &xo.hw },
+	{ .hw = &gpll0.clkr.hw },
+	{ .hw = &gpll4.clkr.hw }
 };
 
 static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
@@ -195,10 +211,10 @@ static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
 	{ P_AUD_REF_CLK, 2 }
 };
 
-static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
-	"xo",
-	"gpll0",
-	"aud_ref_clk"
+static const struct clk_parent_data gcc_xo_gpll0_aud_ref_clk[] = {
+	{ .hw = &xo.hw },
+	{ .hw = &gpll0.clkr.hw },
+	{ .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }
 };
 
 static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
@@ -208,11 +224,11 @@ static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
 	{ P_GPLL0_EARLY_DIV, 6 }
 };
 
-static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
-	"xo",
-	"gpll0",
-	"sleep_clk",
-	"gpll0_early_div"
+static const struct clk_parent_data gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
+	{ .hw = &xo.hw },
+	{ .hw = &gpll0.clkr.hw },
+	{ .fw_name = "sleep_clk", .name = "sleep_clk" },
+	{ .hw = &gpll0_early_div.hw }
 };
 
 static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
@@ -222,11 +238,11 @@ static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
 	{ P_GPLL0_EARLY_DIV, 6 }
 };
 
-static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
-	"xo",
-	"gpll0",
-	"gpll4",
-	"gpll0_early_div"
+static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
+	{ .hw = &xo.hw },
+	{ .hw = &gpll0.clkr.hw },
+	{ .hw = &gpll4.clkr.hw },
+	{ .hw = &gpll0_early_div.hw }
 };
 
 static const struct freq_tbl ftbl_system_noc_clk_src[] = {
@@ -246,7 +262,7 @@ static struct clk_rcg2 system_noc_clk_src = {
 	.freq_tbl = ftbl_system_noc_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "system_noc_clk_src",
-		.parent_names = gcc_xo_gpll0_gpll0_early_div,
+		.parent_data = gcc_xo_gpll0_gpll0_early_div,
 		.num_parents = 3,
 		.ops = &clk_rcg2_ops,
 	},
@@ -266,7 +282,7 @@ static struct clk_rcg2 config_noc_clk_src = {
 	.freq_tbl = ftbl_config_noc_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "config_noc_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -288,7 +304,7 @@ static struct clk_rcg2 periph_noc_clk_src = {
 	.freq_tbl = ftbl_periph_noc_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "periph_noc_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -309,7 +325,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
 	.freq_tbl = ftbl_usb30_master_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "usb30_master_clk_src",
-		.parent_names = gcc_xo_gpll0_gpll0_early_div,
+		.parent_data = gcc_xo_gpll0_gpll0_early_div,
 		.num_parents = 3,
 		.ops = &clk_rcg2_ops,
 	},
@@ -327,7 +343,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
 	.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "usb30_mock_utmi_clk_src",
-		.parent_names = gcc_xo_gpll0_gpll0_early_div,
+		.parent_data = gcc_xo_gpll0_gpll0_early_div,
 		.num_parents = 3,
 		.ops = &clk_rcg2_ops,
 	},
@@ -345,7 +361,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = {
 	.freq_tbl = ftbl_usb3_phy_aux_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "usb3_phy_aux_clk_src",
-		.parent_names = gcc_xo_sleep_clk,
+		.parent_data = gcc_xo_sleep_clk,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -364,7 +380,7 @@ static struct clk_rcg2 usb20_master_clk_src = {
 	.freq_tbl = ftbl_usb20_master_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "usb20_master_clk_src",
-		.parent_names = gcc_xo_gpll0_gpll0_early_div,
+		.parent_data = gcc_xo_gpll0_gpll0_early_div,
 		.num_parents = 3,
 		.ops = &clk_rcg2_ops,
 	},
@@ -377,7 +393,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = {
 	.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "usb20_mock_utmi_clk_src",
-		.parent_names = gcc_xo_gpll0_gpll0_early_div,
+		.parent_data = gcc_xo_gpll0_gpll0_early_div,
 		.num_parents = 3,
 		.ops = &clk_rcg2_ops,
 	},
@@ -403,7 +419,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
 	.freq_tbl = ftbl_sdcc1_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "sdcc1_apps_clk_src",
-		.parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
+		.parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
 		.num_parents = 4,
 		.ops = &clk_rcg2_floor_ops,
 	},
@@ -423,7 +439,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = {
 	.freq_tbl = ftbl_sdcc1_ice_core_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "sdcc1_ice_core_clk_src",
-		.parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
+		.parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
 		.num_parents = 4,
 		.ops = &clk_rcg2_ops,
 	},
@@ -448,7 +464,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
 	.freq_tbl = ftbl_sdcc2_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "sdcc2_apps_clk_src",
-		.parent_names = gcc_xo_gpll0_gpll4,
+		.parent_data = gcc_xo_gpll0_gpll4,
 		.num_parents = 3,
 		.ops = &clk_rcg2_floor_ops,
 	},
@@ -462,7 +478,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
 	.freq_tbl = ftbl_sdcc2_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "sdcc3_apps_clk_src",
-		.parent_names = gcc_xo_gpll0_gpll4,
+		.parent_data = gcc_xo_gpll0_gpll4,
 		.num_parents = 3,
 		.ops = &clk_rcg2_floor_ops,
 	},
@@ -486,7 +502,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
 	.freq_tbl = ftbl_sdcc4_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "sdcc4_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_floor_ops,
 	},
@@ -511,7 +527,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup1_spi_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -530,7 +546,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup1_i2c_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -563,7 +579,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_uart1_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -577,7 +593,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup2_spi_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -590,7 +606,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup2_i2c_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -604,7 +620,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_uart2_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -618,7 +634,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup3_spi_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -631,7 +647,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup3_i2c_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -645,7 +661,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_uart3_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -659,7 +675,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup4_spi_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -672,7 +688,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup4_i2c_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -686,7 +702,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_uart4_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -700,7 +716,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup5_spi_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -713,7 +729,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup5_i2c_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -727,7 +743,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_uart5_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -741,7 +757,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup6_spi_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -754,7 +770,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup6_i2c_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -768,7 +784,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_uart6_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -782,7 +798,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup1_spi_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -795,7 +811,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup1_i2c_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -809,7 +825,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_uart1_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -823,7 +839,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup2_spi_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -836,7 +852,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup2_i2c_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -850,7 +866,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_uart2_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -864,7 +880,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup3_spi_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -877,7 +893,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup3_i2c_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -891,7 +907,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_uart3_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -905,7 +921,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup4_spi_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -918,7 +934,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup4_i2c_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -932,7 +948,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_uart4_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -946,7 +962,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup5_spi_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -959,7 +975,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup5_i2c_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -973,7 +989,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_uart5_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -987,7 +1003,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup6_spi_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -1000,7 +1016,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup6_i2c_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -1014,7 +1030,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
 	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_uart6_apps_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -1032,7 +1048,7 @@ static struct clk_rcg2 pdm2_clk_src = {
 	.freq_tbl = ftbl_pdm2_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pdm2_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -1051,7 +1067,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
 	.freq_tbl = ftbl_tsif_ref_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "tsif_ref_clk_src",
-		.parent_names = gcc_xo_gpll0_aud_ref_clk,
+		.parent_data = gcc_xo_gpll0_aud_ref_clk,
 		.num_parents = 3,
 		.ops = &clk_rcg2_ops,
 	},
@@ -1063,7 +1079,7 @@ static struct clk_rcg2 gcc_sleep_clk_src = {
 	.parent_map = gcc_sleep_clk_map,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gcc_sleep_clk_src",
-		.parent_names = gcc_sleep_clk,
+		.parent_data = gcc_sleep_clk,
 		.num_parents = 1,
 		.ops = &clk_rcg2_ops,
 	},
@@ -1076,7 +1092,7 @@ static struct clk_rcg2 hmss_rbcpr_clk_src = {
 	.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "hmss_rbcpr_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -1088,7 +1104,7 @@ static struct clk_rcg2 hmss_gpll0_clk_src = {
 	.parent_map = gcc_xo_gpll0_map,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "hmss_gpll0_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -1109,7 +1125,7 @@ static struct clk_rcg2 gp1_clk_src = {
 	.freq_tbl = ftbl_gp1_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gp1_clk_src",
-		.parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
+		.parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
 		.num_parents = 4,
 		.ops = &clk_rcg2_ops,
 	},
@@ -1123,7 +1139,7 @@ static struct clk_rcg2 gp2_clk_src = {
 	.freq_tbl = ftbl_gp1_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gp2_clk_src",
-		.parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
+		.parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
 		.num_parents = 4,
 		.ops = &clk_rcg2_ops,
 	},
@@ -1137,7 +1153,7 @@ static struct clk_rcg2 gp3_clk_src = {
 	.freq_tbl = ftbl_gp1_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gp3_clk_src",
-		.parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
+		.parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
 		.num_parents = 4,
 		.ops = &clk_rcg2_ops,
 	},
@@ -1156,7 +1172,7 @@ static struct clk_rcg2 pcie_aux_clk_src = {
 	.freq_tbl = ftbl_pcie_aux_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pcie_aux_clk_src",
-		.parent_names = gcc_xo_sleep_clk,
+		.parent_data = gcc_xo_sleep_clk,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -1177,7 +1193,7 @@ static struct clk_rcg2 ufs_axi_clk_src = {
 	.freq_tbl = ftbl_ufs_axi_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "ufs_axi_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -1197,7 +1213,7 @@ static struct clk_rcg2 ufs_ice_core_clk_src = {
 	.freq_tbl = ftbl_ufs_ice_core_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "ufs_ice_core_clk_src",
-		.parent_names = gcc_xo_gpll0,
+		.parent_data = gcc_xo_gpll0,
 		.num_parents = 2,
 		.ops = &clk_rcg2_ops,
 	},
@@ -1218,7 +1234,7 @@ static struct clk_rcg2 qspi_ser_clk_src = {
 	.freq_tbl = ftbl_qspi_ser_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "qspi_ser_clk_src",
-		.parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
+		.parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
 		.num_parents = 4,
 		.ops = &clk_rcg2_ops,
 	},
@@ -1231,7 +1247,9 @@ static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_sys_noc_usb3_axi_clk",
-			.parent_names = (const char *[]){ "usb30_master_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&usb30_master_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1246,7 +1264,9 @@ static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_sys_noc_ufs_axi_clk",
-			.parent_names = (const char *[]){ "ufs_axi_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&ufs_axi_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1261,7 +1281,9 @@ static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_periph_noc_usb20_ahb_clk",
-			.parent_names = (const char *[]){ "usb20_master_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&usb20_master_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1276,7 +1298,9 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_mmss_noc_cfg_ahb_clk",
-			.parent_names = (const char *[]){ "config_noc_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&config_noc_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
 			.ops = &clk_branch2_ops,
@@ -1304,7 +1328,9 @@ static struct clk_branch gcc_usb30_master_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_usb30_master_clk",
-			.parent_names = (const char *[]){ "usb30_master_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&usb30_master_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1319,7 +1345,9 @@ static struct clk_branch gcc_usb30_sleep_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_usb30_sleep_clk",
-			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&gcc_sleep_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1334,7 +1362,9 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_usb30_mock_utmi_clk",
-			.parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&usb30_mock_utmi_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1349,7 +1379,9 @@ static struct clk_branch gcc_usb3_phy_aux_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_usb3_phy_aux_clk",
-			.parent_names = (const char *[]){ "usb3_phy_aux_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&usb3_phy_aux_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1365,7 +1397,9 @@ static struct clk_branch gcc_usb3_phy_pipe_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_usb3_phy_pipe_clk",
-			.parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "usb3_phy_pipe_clk_src", .name = "usb3_phy_pipe_clk_src",
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1380,7 +1414,9 @@ static struct clk_branch gcc_usb20_master_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_usb20_master_clk",
-			.parent_names = (const char *[]){ "usb20_master_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&usb20_master_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1395,7 +1431,9 @@ static struct clk_branch gcc_usb20_sleep_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_usb20_sleep_clk",
-			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&gcc_sleep_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1410,7 +1448,9 @@ static struct clk_branch gcc_usb20_mock_utmi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_usb20_mock_utmi_clk",
-			.parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&usb20_mock_utmi_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1425,7 +1465,9 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_usb_phy_cfg_ahb2phy_clk",
-			.parent_names = (const char *[]){ "periph_noc_clk_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1440,7 +1482,9 @@ static struct clk_branch gcc_sdcc1_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_sdcc1_apps_clk",
-			.parent_names = (const char *[]){ "sdcc1_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&sdcc1_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1455,7 +1499,9 @@ static struct clk_branch gcc_sdcc1_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_sdcc1_ahb_clk",
-			.parent_names = (const char *[]){ "periph_noc_clk_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1470,7 +1516,9 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_sdcc1_ice_core_clk",
-			.parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&sdcc1_ice_core_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1485,7 +1533,9 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_sdcc2_apps_clk",
-			.parent_names = (const char *[]){ "sdcc2_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&sdcc2_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1500,7 +1550,9 @@ static struct clk_branch gcc_sdcc2_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_sdcc2_ahb_clk",
-			.parent_names = (const char *[]){ "periph_noc_clk_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1515,7 +1567,9 @@ static struct clk_branch gcc_sdcc3_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_sdcc3_apps_clk",
-			.parent_names = (const char *[]){ "sdcc3_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&sdcc3_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1530,7 +1584,9 @@ static struct clk_branch gcc_sdcc3_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_sdcc3_ahb_clk",
-			.parent_names = (const char *[]){ "periph_noc_clk_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1545,7 +1601,9 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_sdcc4_apps_clk",
-			.parent_names = (const char *[]){ "sdcc4_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&sdcc4_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1560,7 +1618,9 @@ static struct clk_branch gcc_sdcc4_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_sdcc4_ahb_clk",
-			.parent_names = (const char *[]){ "periph_noc_clk_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1576,7 +1636,9 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
 		.enable_mask = BIT(17),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_ahb_clk",
-			.parent_names = (const char *[]){ "periph_noc_clk_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1592,7 +1654,9 @@ static struct clk_branch gcc_blsp1_sleep_clk = {
 		.enable_mask = BIT(16),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_sleep_clk",
-			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&gcc_sleep_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1607,7 +1671,9 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_qup1_spi_apps_clk",
-			.parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_qup1_spi_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1622,7 +1688,9 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_qup1_i2c_apps_clk",
-			.parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1637,7 +1705,9 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_uart1_apps_clk",
-			.parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_uart1_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1652,7 +1722,9 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_qup2_spi_apps_clk",
-			.parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_qup2_spi_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1667,7 +1739,9 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_qup2_i2c_apps_clk",
-			.parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1682,7 +1756,9 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_uart2_apps_clk",
-			.parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_uart2_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1697,7 +1773,9 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_qup3_spi_apps_clk",
-			.parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_qup3_spi_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1712,7 +1790,9 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_qup3_i2c_apps_clk",
-			.parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1727,7 +1807,9 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_uart3_apps_clk",
-			.parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_uart3_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1742,7 +1824,9 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_qup4_spi_apps_clk",
-			.parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_qup4_spi_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1757,7 +1841,9 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_qup4_i2c_apps_clk",
-			.parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_qup4_i2c_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1772,7 +1858,9 @@ static struct clk_branch gcc_blsp1_uart4_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_uart4_apps_clk",
-			.parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_uart4_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1787,7 +1875,9 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_qup5_spi_apps_clk",
-			.parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_qup5_spi_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1802,7 +1892,9 @@ static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_qup5_i2c_apps_clk",
-			.parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_qup5_i2c_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1817,7 +1909,9 @@ static struct clk_branch gcc_blsp1_uart5_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_uart5_apps_clk",
-			.parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_uart5_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1832,7 +1926,9 @@ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_qup6_spi_apps_clk",
-			.parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_qup6_spi_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1847,7 +1943,9 @@ static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_qup6_i2c_apps_clk",
-			.parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_qup6_i2c_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1862,7 +1960,9 @@ static struct clk_branch gcc_blsp1_uart6_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp1_uart6_apps_clk",
-			.parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp1_uart6_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1878,7 +1978,9 @@ static struct clk_branch gcc_blsp2_ahb_clk = {
 		.enable_mask = BIT(15),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_ahb_clk",
-			.parent_names = (const char *[]){ "periph_noc_clk_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1894,7 +1996,9 @@ static struct clk_branch gcc_blsp2_sleep_clk = {
 		.enable_mask = BIT(14),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_sleep_clk",
-			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&gcc_sleep_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1909,7 +2013,9 @@ static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_qup1_spi_apps_clk",
-			.parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_qup1_spi_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1924,7 +2030,9 @@ static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_qup1_i2c_apps_clk",
-			.parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_qup1_i2c_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1939,7 +2047,9 @@ static struct clk_branch gcc_blsp2_uart1_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_uart1_apps_clk",
-			.parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_uart1_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1954,7 +2064,9 @@ static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_qup2_spi_apps_clk",
-			.parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_qup2_spi_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1969,7 +2081,9 @@ static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_qup2_i2c_apps_clk",
-			.parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_qup2_i2c_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1984,7 +2098,9 @@ static struct clk_branch gcc_blsp2_uart2_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_uart2_apps_clk",
-			.parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_uart2_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -1999,7 +2115,9 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_qup3_spi_apps_clk",
-			.parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_qup3_spi_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2014,7 +2132,9 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_qup3_i2c_apps_clk",
-			.parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_qup3_i2c_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2029,7 +2149,9 @@ static struct clk_branch gcc_blsp2_uart3_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_uart3_apps_clk",
-			.parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_uart3_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2044,7 +2166,9 @@ static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_qup4_spi_apps_clk",
-			.parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_qup4_spi_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2059,7 +2183,9 @@ static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_qup4_i2c_apps_clk",
-			.parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_qup4_i2c_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2074,7 +2200,9 @@ static struct clk_branch gcc_blsp2_uart4_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_uart4_apps_clk",
-			.parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_uart4_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2089,7 +2217,9 @@ static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_qup5_spi_apps_clk",
-			.parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_qup5_spi_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2104,7 +2234,9 @@ static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_qup5_i2c_apps_clk",
-			.parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_qup5_i2c_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2119,7 +2251,9 @@ static struct clk_branch gcc_blsp2_uart5_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_uart5_apps_clk",
-			.parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_uart5_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2134,7 +2268,9 @@ static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_qup6_spi_apps_clk",
-			.parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_qup6_spi_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2149,7 +2285,9 @@ static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_qup6_i2c_apps_clk",
-			.parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_qup6_i2c_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2164,7 +2302,9 @@ static struct clk_branch gcc_blsp2_uart6_apps_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_blsp2_uart6_apps_clk",
-			.parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&blsp2_uart6_apps_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2179,7 +2319,9 @@ static struct clk_branch gcc_pdm_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pdm_ahb_clk",
-			.parent_names = (const char *[]){ "periph_noc_clk_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2194,7 +2336,9 @@ static struct clk_branch gcc_pdm2_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pdm2_clk",
-			.parent_names = (const char *[]){ "pdm2_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&pdm2_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2210,7 +2354,9 @@ static struct clk_branch gcc_prng_ahb_clk = {
 		.enable_mask = BIT(13),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_prng_ahb_clk",
-			.parent_names = (const char *[]){ "config_noc_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&config_noc_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2225,7 +2371,9 @@ static struct clk_branch gcc_tsif_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_tsif_ahb_clk",
-			.parent_names = (const char *[]){ "periph_noc_clk_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2240,7 +2388,9 @@ static struct clk_branch gcc_tsif_ref_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_tsif_ref_clk",
-			.parent_names = (const char *[]){ "tsif_ref_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&tsif_ref_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2255,7 +2405,9 @@ static struct clk_branch gcc_tsif_inactivity_timers_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_tsif_inactivity_timers_clk",
-			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&gcc_sleep_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2271,7 +2423,9 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
 		.enable_mask = BIT(10),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_boot_rom_ahb_clk",
-			.parent_names = (const char *[]){ "config_noc_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&config_noc_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2299,7 +2453,9 @@ static struct clk_branch gcc_hmss_rbcpr_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_hmss_rbcpr_clk",
-			.parent_names = (const char *[]){ "hmss_rbcpr_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&hmss_rbcpr_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2314,7 +2470,9 @@ static struct clk_branch gcc_gp1_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_gp1_clk",
-			.parent_names = (const char *[]){ "gp1_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&gp1_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2329,7 +2487,9 @@ static struct clk_branch gcc_gp2_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_gp2_clk",
-			.parent_names = (const char *[]){ "gp2_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&gp2_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2344,7 +2504,9 @@ static struct clk_branch gcc_gp3_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_gp3_clk",
-			.parent_names = (const char *[]){ "gp3_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&gp3_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2359,7 +2521,9 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pcie_0_slv_axi_clk",
-			.parent_names = (const char *[]){ "system_noc_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&system_noc_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2374,7 +2538,9 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pcie_0_mstr_axi_clk",
-			.parent_names = (const char *[]){ "system_noc_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&system_noc_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2389,7 +2555,9 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pcie_0_cfg_ahb_clk",
-			.parent_names = (const char *[]){ "config_noc_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&config_noc_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2404,7 +2572,9 @@ static struct clk_branch gcc_pcie_0_aux_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pcie_0_aux_clk",
-			.parent_names = (const char *[]){ "pcie_aux_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&pcie_aux_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2420,7 +2590,9 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pcie_0_pipe_clk",
-			.parent_names = (const char *[]){ "pcie_0_pipe_clk_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "pcie_0_pipe_clk_src", .name = "pcie_0_pipe_clk_src",
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2435,7 +2607,9 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pcie_1_slv_axi_clk",
-			.parent_names = (const char *[]){ "system_noc_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&system_noc_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2450,7 +2624,9 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pcie_1_mstr_axi_clk",
-			.parent_names = (const char *[]){ "system_noc_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&system_noc_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2465,7 +2641,9 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pcie_1_cfg_ahb_clk",
-			.parent_names = (const char *[]){ "config_noc_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&config_noc_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2480,7 +2658,9 @@ static struct clk_branch gcc_pcie_1_aux_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pcie_1_aux_clk",
-			.parent_names = (const char *[]){ "pcie_aux_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&pcie_aux_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2496,7 +2676,9 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pcie_1_pipe_clk",
-			.parent_names = (const char *[]){ "pcie_1_pipe_clk_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "pcie_1_pipe_clk_src", .name = "pcie_1_pipe_clk_src",
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2511,7 +2693,9 @@ static struct clk_branch gcc_pcie_2_slv_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pcie_2_slv_axi_clk",
-			.parent_names = (const char *[]){ "system_noc_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&system_noc_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2526,7 +2710,9 @@ static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pcie_2_mstr_axi_clk",
-			.parent_names = (const char *[]){ "system_noc_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&system_noc_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2541,7 +2727,9 @@ static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pcie_2_cfg_ahb_clk",
-			.parent_names = (const char *[]){ "config_noc_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&config_noc_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2556,7 +2744,9 @@ static struct clk_branch gcc_pcie_2_aux_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pcie_2_aux_clk",
-			.parent_names = (const char *[]){ "pcie_aux_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&pcie_aux_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2572,7 +2762,9 @@ static struct clk_branch gcc_pcie_2_pipe_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pcie_2_pipe_clk",
-			.parent_names = (const char *[]){ "pcie_2_pipe_clk_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "pcie_2_pipe_clk_src", .name = "pcie_2_pipe_clk_src",
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2587,7 +2779,9 @@ static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pcie_phy_cfg_ahb_clk",
-			.parent_names = (const char *[]){ "config_noc_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&config_noc_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2602,7 +2796,9 @@ static struct clk_branch gcc_pcie_phy_aux_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_pcie_phy_aux_clk",
-			.parent_names = (const char *[]){ "pcie_aux_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&pcie_aux_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2617,7 +2813,9 @@ static struct clk_branch gcc_ufs_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_ufs_axi_clk",
-			.parent_names = (const char *[]){ "ufs_axi_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&ufs_axi_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2632,7 +2830,9 @@ static struct clk_branch gcc_ufs_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_ufs_ahb_clk",
-			.parent_names = (const char *[]){ "config_noc_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&config_noc_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2645,7 +2845,9 @@ static struct clk_fixed_factor ufs_tx_cfg_clk_src = {
 	.div = 16,
 	.hw.init = &(struct clk_init_data){
 		.name = "ufs_tx_cfg_clk_src",
-		.parent_names = (const char *[]){ "ufs_axi_clk_src" },
+		.parent_hws = (const struct clk_hw*[]){
+			&ufs_axi_clk_src.clkr.hw,
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_fixed_factor_ops,
@@ -2659,7 +2861,9 @@ static struct clk_branch gcc_ufs_tx_cfg_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_ufs_tx_cfg_clk",
-			.parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&ufs_tx_cfg_clk_src.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2672,7 +2876,9 @@ static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
 	.div = 16,
 	.hw.init = &(struct clk_init_data){
 		.name = "ufs_rx_cfg_clk_src",
-		.parent_names = (const char *[]){ "ufs_axi_clk_src" },
+		.parent_hws = (const struct clk_hw*[]){
+			&ufs_axi_clk_src.clkr.hw,
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_fixed_factor_ops,
@@ -2712,7 +2918,9 @@ static struct clk_branch gcc_ufs_rx_cfg_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_ufs_rx_cfg_clk",
-			.parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&ufs_rx_cfg_clk_src.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2728,7 +2936,9 @@ static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_ufs_tx_symbol_0_clk",
-			.parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "ufs_tx_symbol_0_clk_src", .name = "ufs_tx_symbol_0_clk_src",
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2744,7 +2954,9 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_ufs_rx_symbol_0_clk",
-			.parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "ufs_rx_symbol_0_clk_src", .name = "ufs_rx_symbol_0_clk_src",
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2760,7 +2972,9 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_ufs_rx_symbol_1_clk",
-			.parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "ufs_rx_symbol_1_clk_src", .name = "ufs_rx_symbol_1_clk_src",
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2773,7 +2987,9 @@ static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {
 	.div = 2,
 	.hw.init = &(struct clk_init_data){
 		.name = "ufs_ice_core_postdiv_clk_src",
-		.parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
+		.parent_hws = (const struct clk_hw*[]){
+			&ufs_ice_core_clk_src.clkr.hw,
+		},
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_fixed_factor_ops,
@@ -2787,7 +3003,9 @@ static struct clk_branch gcc_ufs_unipro_core_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_ufs_unipro_core_clk",
-			.parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&ufs_ice_core_postdiv_clk_src.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2802,7 +3020,9 @@ static struct clk_branch gcc_ufs_ice_core_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_ufs_ice_core_clk",
-			.parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&ufs_ice_core_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2841,7 +3061,9 @@ static struct clk_branch gcc_aggre0_snoc_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_aggre0_snoc_axi_clk",
-			.parent_names = (const char *[]){ "system_noc_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&system_noc_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
 			.ops = &clk_branch2_ops,
@@ -2856,7 +3078,9 @@ static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_aggre0_cnoc_ahb_clk",
-			.parent_names = (const char *[]){ "config_noc_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&config_noc_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
 			.ops = &clk_branch2_ops,
@@ -2871,7 +3095,9 @@ static struct clk_branch gcc_smmu_aggre0_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_smmu_aggre0_axi_clk",
-			.parent_names = (const char *[]){ "system_noc_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&system_noc_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
 			.ops = &clk_branch2_ops,
@@ -2886,7 +3112,9 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_smmu_aggre0_ahb_clk",
-			.parent_names = (const char *[]){ "config_noc_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&config_noc_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
 			.ops = &clk_branch2_ops,
@@ -2901,7 +3129,9 @@ static struct clk_branch gcc_aggre2_ufs_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_aggre2_ufs_axi_clk",
-			.parent_names = (const char *[]){ "ufs_axi_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&ufs_axi_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2916,7 +3146,9 @@ static struct clk_branch gcc_aggre2_usb3_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_aggre2_usb3_axi_clk",
-			.parent_names = (const char *[]){ "usb30_master_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&usb30_master_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2931,7 +3163,9 @@ static struct clk_branch gcc_dcc_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_dcc_ahb_clk",
-			.parent_names = (const char *[]){ "config_noc_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&config_noc_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
 		},
@@ -2945,7 +3179,9 @@ static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",
-			.parent_names = (const char *[]){ "config_noc_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&config_noc_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
 		},
@@ -2959,7 +3195,9 @@ static struct clk_branch gcc_qspi_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_qspi_ahb_clk",
-			.parent_names = (const char *[]){ "periph_noc_clk_src" },
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -2974,7 +3212,9 @@ static struct clk_branch gcc_qspi_ser_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_qspi_ser_clk",
-			.parent_names = (const char *[]){ "qspi_ser_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&qspi_ser_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
@@ -3108,7 +3348,9 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_mss_cfg_ahb_clk",
-			.parent_names = (const char *[]){ "config_noc_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&config_noc_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
 		},
@@ -3122,7 +3364,9 @@ static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_mss_mnoc_bimc_axi_clk",
-			.parent_names = (const char *[]){ "system_noc_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&system_noc_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
 		},
@@ -3136,7 +3380,9 @@ static struct clk_branch gcc_mss_snoc_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_mss_snoc_axi_clk",
-			.parent_names = (const char *[]){ "system_noc_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&system_noc_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
 		},
@@ -3150,7 +3396,9 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gcc_mss_q6_bimc_axi_clk",
-			.parent_names = (const char *[]){ "system_noc_clk_src" },
+			.parent_hws = (const struct clk_hw*[]){
+				&system_noc_clk_src.clkr.hw,
+			},
 			.num_parents = 1,
 			.ops = &clk_branch2_ops,
 		},
-- 
2.33.0

[PATCH 11/11] clk: qcom: gcc-msm8996: use ARRAY_SIZE instead of specifying num_parents

[Dmitry Baryshkov]

Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/clk/qcom/gcc-msm8996.c | 122 ++++++++++++++++-----------------
 1 file changed, 61 insertions(+), 61 deletions(-)

diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index 186e682e730f..204c1f4c68c4 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -263,7 +263,7 @@ static struct clk_rcg2 system_noc_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "system_noc_clk_src",
 		.parent_data = gcc_xo_gpll0_gpll0_early_div,
-		.num_parents = 3,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -283,7 +283,7 @@ static struct clk_rcg2 config_noc_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "config_noc_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -305,7 +305,7 @@ static struct clk_rcg2 periph_noc_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "periph_noc_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -326,7 +326,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "usb30_master_clk_src",
 		.parent_data = gcc_xo_gpll0_gpll0_early_div,
-		.num_parents = 3,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -344,7 +344,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "usb30_mock_utmi_clk_src",
 		.parent_data = gcc_xo_gpll0_gpll0_early_div,
-		.num_parents = 3,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -362,7 +362,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "usb3_phy_aux_clk_src",
 		.parent_data = gcc_xo_sleep_clk,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -381,7 +381,7 @@ static struct clk_rcg2 usb20_master_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "usb20_master_clk_src",
 		.parent_data = gcc_xo_gpll0_gpll0_early_div,
-		.num_parents = 3,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -394,7 +394,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "usb20_mock_utmi_clk_src",
 		.parent_data = gcc_xo_gpll0_gpll0_early_div,
-		.num_parents = 3,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -420,7 +420,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "sdcc1_apps_clk_src",
 		.parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
 		.ops = &clk_rcg2_floor_ops,
 	},
 };
@@ -440,7 +440,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "sdcc1_ice_core_clk_src",
 		.parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -465,7 +465,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "sdcc2_apps_clk_src",
 		.parent_data = gcc_xo_gpll0_gpll4,
-		.num_parents = 3,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
 		.ops = &clk_rcg2_floor_ops,
 	},
 };
@@ -479,7 +479,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "sdcc3_apps_clk_src",
 		.parent_data = gcc_xo_gpll0_gpll4,
-		.num_parents = 3,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
 		.ops = &clk_rcg2_floor_ops,
 	},
 };
@@ -503,7 +503,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "sdcc4_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_floor_ops,
 	},
 };
@@ -528,7 +528,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup1_spi_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -547,7 +547,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup1_i2c_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -580,7 +580,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_uart1_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -594,7 +594,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup2_spi_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -607,7 +607,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup2_i2c_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -621,7 +621,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_uart2_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -635,7 +635,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup3_spi_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -648,7 +648,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup3_i2c_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -662,7 +662,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_uart3_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -676,7 +676,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup4_spi_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -689,7 +689,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup4_i2c_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -703,7 +703,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_uart4_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -717,7 +717,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup5_spi_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -730,7 +730,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup5_i2c_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -744,7 +744,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_uart5_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -758,7 +758,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup6_spi_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -771,7 +771,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_qup6_i2c_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -785,7 +785,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp1_uart6_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -799,7 +799,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup1_spi_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -812,7 +812,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup1_i2c_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -826,7 +826,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_uart1_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -840,7 +840,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup2_spi_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -853,7 +853,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup2_i2c_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -867,7 +867,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_uart2_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -881,7 +881,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup3_spi_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -894,7 +894,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup3_i2c_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -908,7 +908,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_uart3_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -922,7 +922,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup4_spi_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -935,7 +935,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup4_i2c_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -949,7 +949,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_uart4_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -963,7 +963,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup5_spi_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -976,7 +976,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup5_i2c_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -990,7 +990,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_uart5_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -1004,7 +1004,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup6_spi_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -1017,7 +1017,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_qup6_i2c_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -1031,7 +1031,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "blsp2_uart6_apps_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -1049,7 +1049,7 @@ static struct clk_rcg2 pdm2_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pdm2_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -1068,7 +1068,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "tsif_ref_clk_src",
 		.parent_data = gcc_xo_gpll0_aud_ref_clk,
-		.num_parents = 3,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_aud_ref_clk),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -1080,7 +1080,7 @@ static struct clk_rcg2 gcc_sleep_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gcc_sleep_clk_src",
 		.parent_data = gcc_sleep_clk,
-		.num_parents = 1,
+		.num_parents = ARRAY_SIZE(gcc_sleep_clk),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -1093,7 +1093,7 @@ static struct clk_rcg2 hmss_rbcpr_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "hmss_rbcpr_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -1105,7 +1105,7 @@ static struct clk_rcg2 hmss_gpll0_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "hmss_gpll0_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -1126,7 +1126,7 @@ static struct clk_rcg2 gp1_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gp1_clk_src",
 		.parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -1140,7 +1140,7 @@ static struct clk_rcg2 gp2_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gp2_clk_src",
 		.parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -1154,7 +1154,7 @@ static struct clk_rcg2 gp3_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gp3_clk_src",
 		.parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -1173,7 +1173,7 @@ static struct clk_rcg2 pcie_aux_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "pcie_aux_clk_src",
 		.parent_data = gcc_xo_sleep_clk,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -1194,7 +1194,7 @@ static struct clk_rcg2 ufs_axi_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "ufs_axi_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -1214,7 +1214,7 @@ static struct clk_rcg2 ufs_ice_core_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "ufs_ice_core_clk_src",
 		.parent_data = gcc_xo_gpll0,
-		.num_parents = 2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 		.ops = &clk_rcg2_ops,
 	},
 };
@@ -1235,7 +1235,7 @@ static struct clk_rcg2 qspi_ser_clk_src = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "qspi_ser_clk_src",
 		.parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
-		.num_parents = 4,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
 		.ops = &clk_rcg2_ops,
 	},
 };
-- 
2.33.0

Re: [PATCH 02/11] clk: qcom: gpucc-sdm660: use parent_hws instead of parent_data

[Marijn Suijten]

On 2021-12-08 20:54:21, Dmitry Baryshkov wrote:
> If all parents are specified as clk_hw, we can use parent_hws instead of
> parent_data.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>

> ---
>  drivers/clk/qcom/gpucc-sdm660.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gpucc-sdm660.c b/drivers/clk/qcom/gpucc-sdm660.c
> index 26e17f349a77..27a506a78a25 100644
> --- a/drivers/clk/qcom/gpucc-sdm660.c
> +++ b/drivers/clk/qcom/gpucc-sdm660.c
> @@ -65,8 +65,8 @@ static struct clk_alpha_pll gpu_pll0_pll_out_main = {
>  	.num_vco = ARRAY_SIZE(gpu_vco),
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "gpu_pll0_pll_out_main",
> -		.parent_data =  &(const struct clk_parent_data){
> -			.hw = &gpucc_cxo_clk.clkr.hw,
> +		.parent_hws = (const struct clk_hw*[]){
> +			&gpucc_cxo_clk.clkr.hw,
>  		},
>  		.num_parents = 1,
>  		.ops = &clk_alpha_pll_ops,
> @@ -80,8 +80,8 @@ static struct clk_alpha_pll gpu_pll1_pll_out_main = {
>  	.num_vco = ARRAY_SIZE(gpu_vco),
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "gpu_pll1_pll_out_main",
> -		.parent_data = &(const struct clk_parent_data){
> -			.hw = &gpucc_cxo_clk.clkr.hw,
> +		.parent_hws = (const struct clk_hw*[]){
> +			&gpucc_cxo_clk.clkr.hw,
>  		},
>  		.num_parents = 1,
>  		.ops = &clk_alpha_pll_ops,
> @@ -134,8 +134,8 @@ static struct clk_branch gpucc_gfx3d_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gpucc_gfx3d_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &gfx3d_clk_src.rcg.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&gfx3d_clk_src.rcg.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> -- 
> 2.33.0
> 

Re: [PATCH 03/11] clk: qcom: camcc-sc7180: get rid of the test clock

[Marijn Suijten]

On 2021-12-08 20:54:22, Dmitry Baryshkov wrote:
> The test clock isn't in the bindings and apparently it's not used by
> anyone upstream.  Remove it.
> 
> Suggested-by: Stephen Boyd <swboyd@chromium.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  drivers/clk/qcom/camcc-sc7180.c | 65 +++++++++++++--------------------
>  1 file changed, 25 insertions(+), 40 deletions(-)
> 
> diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c
> index ce73ee9037cb..3c15e551419f 100644
> --- a/drivers/clk/qcom/camcc-sc7180.c
> +++ b/drivers/clk/qcom/camcc-sc7180.c
> [..]
> @@ -303,7 +288,7 @@ static struct clk_rcg2 cam_cc_bps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_bps_clk_src",
>  		.parent_data = cam_cc_parent_data_2,
> -		.num_parents = 5,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),

Perhaps it is more clear to perform this conversion in a separate patch,
before this patch that removes the test clock?  Otherwise this
transition to ARRAY_SIZE should probably at least be mentioned in the
title and commit body.

- Marijn

>  		.ops = &clk_rcg2_shared_ops,
>  	},
>  };
> [..]

Re: [PATCH 07/11] clk: qcom: videocc-sc7180: use parent_hws instead of parent_data

[Marijn Suijten]

On 2021-12-08 20:54:26, Dmitry Baryshkov wrote:
> If all parents are specified as clk_hw, we can use parent_hws instead of
> parent_data.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>

> ---
>  drivers/clk/qcom/videocc-sc7180.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/qcom/videocc-sc7180.c b/drivers/clk/qcom/videocc-sc7180.c
> index ed57bbb19f88..5b9b54f616b8 100644
> --- a/drivers/clk/qcom/videocc-sc7180.c
> +++ b/drivers/clk/qcom/videocc-sc7180.c
> @@ -99,8 +99,8 @@ static struct clk_branch video_cc_vcodec0_core_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "video_cc_vcodec0_core_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &video_cc_venus_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&video_cc_venus_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -143,8 +143,8 @@ static struct clk_branch video_cc_venus_ctl_core_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "video_cc_venus_ctl_core_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &video_cc_venus_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&video_cc_venus_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> -- 
> 2.33.0
> 

Re: [PATCH 11/11] clk: qcom: gcc-msm8996: use ARRAY_SIZE instead of specifying num_parents

[Marijn Suijten]

On 2021-12-08 20:54:30, Dmitry Baryshkov wrote:
> Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
> adding/removing entries to/from parent_data easy and errorproof.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>

> ---
>  drivers/clk/qcom/gcc-msm8996.c | 122 ++++++++++++++++-----------------
>  1 file changed, 61 insertions(+), 61 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
> index 186e682e730f..204c1f4c68c4 100644
> --- a/drivers/clk/qcom/gcc-msm8996.c
> +++ b/drivers/clk/qcom/gcc-msm8996.c
> @@ -263,7 +263,7 @@ static struct clk_rcg2 system_noc_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "system_noc_clk_src",
>  		.parent_data = gcc_xo_gpll0_gpll0_early_div,
> -		.num_parents = 3,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -283,7 +283,7 @@ static struct clk_rcg2 config_noc_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "config_noc_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -305,7 +305,7 @@ static struct clk_rcg2 periph_noc_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "periph_noc_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -326,7 +326,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "usb30_master_clk_src",
>  		.parent_data = gcc_xo_gpll0_gpll0_early_div,
> -		.num_parents = 3,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -344,7 +344,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "usb30_mock_utmi_clk_src",
>  		.parent_data = gcc_xo_gpll0_gpll0_early_div,
> -		.num_parents = 3,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -362,7 +362,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "usb3_phy_aux_clk_src",
>  		.parent_data = gcc_xo_sleep_clk,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -381,7 +381,7 @@ static struct clk_rcg2 usb20_master_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "usb20_master_clk_src",
>  		.parent_data = gcc_xo_gpll0_gpll0_early_div,
> -		.num_parents = 3,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -394,7 +394,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "usb20_mock_utmi_clk_src",
>  		.parent_data = gcc_xo_gpll0_gpll0_early_div,
> -		.num_parents = 3,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -420,7 +420,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "sdcc1_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
>  		.ops = &clk_rcg2_floor_ops,
>  	},
>  };
> @@ -440,7 +440,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "sdcc1_ice_core_clk_src",
>  		.parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -465,7 +465,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "sdcc2_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0_gpll4,
> -		.num_parents = 3,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
>  		.ops = &clk_rcg2_floor_ops,
>  	},
>  };
> @@ -479,7 +479,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "sdcc3_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0_gpll4,
> -		.num_parents = 3,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
>  		.ops = &clk_rcg2_floor_ops,
>  	},
>  };
> @@ -503,7 +503,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "sdcc4_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_floor_ops,
>  	},
>  };
> @@ -528,7 +528,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup1_spi_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -547,7 +547,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup1_i2c_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -580,7 +580,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_uart1_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -594,7 +594,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup2_spi_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -607,7 +607,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup2_i2c_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -621,7 +621,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_uart2_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -635,7 +635,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup3_spi_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -648,7 +648,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup3_i2c_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -662,7 +662,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_uart3_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -676,7 +676,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup4_spi_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -689,7 +689,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup4_i2c_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -703,7 +703,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_uart4_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -717,7 +717,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup5_spi_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -730,7 +730,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup5_i2c_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -744,7 +744,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_uart5_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -758,7 +758,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup6_spi_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -771,7 +771,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup6_i2c_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -785,7 +785,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_uart6_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -799,7 +799,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup1_spi_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -812,7 +812,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup1_i2c_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -826,7 +826,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_uart1_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -840,7 +840,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup2_spi_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -853,7 +853,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup2_i2c_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -867,7 +867,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_uart2_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -881,7 +881,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup3_spi_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -894,7 +894,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup3_i2c_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -908,7 +908,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_uart3_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -922,7 +922,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup4_spi_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -935,7 +935,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup4_i2c_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -949,7 +949,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_uart4_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -963,7 +963,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup5_spi_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -976,7 +976,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup5_i2c_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -990,7 +990,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_uart5_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -1004,7 +1004,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup6_spi_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -1017,7 +1017,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup6_i2c_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -1031,7 +1031,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_uart6_apps_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -1049,7 +1049,7 @@ static struct clk_rcg2 pdm2_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "pdm2_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -1068,7 +1068,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "tsif_ref_clk_src",
>  		.parent_data = gcc_xo_gpll0_aud_ref_clk,
> -		.num_parents = 3,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_aud_ref_clk),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -1080,7 +1080,7 @@ static struct clk_rcg2 gcc_sleep_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "gcc_sleep_clk_src",
>  		.parent_data = gcc_sleep_clk,
> -		.num_parents = 1,
> +		.num_parents = ARRAY_SIZE(gcc_sleep_clk),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -1093,7 +1093,7 @@ static struct clk_rcg2 hmss_rbcpr_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "hmss_rbcpr_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -1105,7 +1105,7 @@ static struct clk_rcg2 hmss_gpll0_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "hmss_gpll0_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -1126,7 +1126,7 @@ static struct clk_rcg2 gp1_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "gp1_clk_src",
>  		.parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -1140,7 +1140,7 @@ static struct clk_rcg2 gp2_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "gp2_clk_src",
>  		.parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -1154,7 +1154,7 @@ static struct clk_rcg2 gp3_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "gp3_clk_src",
>  		.parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk_gpll0_early_div),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -1173,7 +1173,7 @@ static struct clk_rcg2 pcie_aux_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "pcie_aux_clk_src",
>  		.parent_data = gcc_xo_sleep_clk,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_sleep_clk),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -1194,7 +1194,7 @@ static struct clk_rcg2 ufs_axi_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "ufs_axi_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -1214,7 +1214,7 @@ static struct clk_rcg2 ufs_ice_core_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "ufs_ice_core_clk_src",
>  		.parent_data = gcc_xo_gpll0,
> -		.num_parents = 2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -1235,7 +1235,7 @@ static struct clk_rcg2 qspi_ser_clk_src = {
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "qspi_ser_clk_src",
>  		.parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
> -		.num_parents = 4,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> -- 
> 2.33.0
> 

Re: [PATCH 10/11] clk: qcom: gcc-msm8996: use parent_hws/_data instead of parent_names

[Marijn Suijten]

On 2021-12-08 20:54:29, Dmitry Baryshkov wrote:
> Convert the clock driver to specify parent data rather than parent
> names, to actually bind using 'clock-names' specified in the DTS rather
> than global clock names. Use parent_hws where possible to refer parent
> clocks directly, skipping the lookup.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  drivers/clk/qcom/gcc-msm8996.c | 678 ++++++++++++++++++++++-----------
>  1 file changed, 463 insertions(+), 215 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
> index c2f9ae729d1e..186e682e730f 100644
> --- a/drivers/clk/qcom/gcc-msm8996.c
> +++ b/drivers/clk/qcom/gcc-msm8996.c
> @@ -38,7 +38,9 @@ static struct clk_fixed_factor xo = {
>  	.div = 1,
>  	.hw.init = &(struct clk_init_data){
>  		.name = "xo",
> -		.parent_names = (const char *[]){ "xo_board" },
> +		.parent_data = &(const struct clk_parent_data){
> +			.fw_name = "cxo", .name = "xo_board",

I assume you'll submit DT changes later to provide this cxo clock in the
DT?  msm8996.dtsi currently only seems to provide a cxo2 clock.

> +		},
>  		.num_parents = 1,
>  		.ops = &clk_fixed_factor_ops,
>  	},
> @@ -52,7 +54,9 @@ static struct clk_alpha_pll gpll0_early = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gpll0_early",
> -			.parent_names = (const char *[]){ "xo" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&xo.hw,

I always view this local "xo" clock as a "hack" to provide an "xo" clock
in the global namespace for drivers and older DTs that don't use clocks=
and clock-names= yet.  Since it's an alias for xo_board, it is perhaps
better to repeat `.fw_name = "cxo", .name = "xo_board"` here?

Otherwise we might want to swap all those over to `&xo.hw` instead.

> +			},
>  			.num_parents = 1,
>  			.ops = &clk_alpha_pll_ops,
>  		},
> @@ -64,7 +68,9 @@ static struct clk_fixed_factor gpll0_early_div = {
>  	.div = 2,
>  	.hw.init = &(struct clk_init_data){
>  		.name = "gpll0_early_div",
> -		.parent_names = (const char *[]){ "gpll0_early" },
> +		.parent_hws = (const struct clk_hw*[]){
> +			&gpll0_early.clkr.hw,
> +		},
>  		.num_parents = 1,
>  		.ops = &clk_fixed_factor_ops,
>  	},
> @@ -75,7 +81,9 @@ static struct clk_alpha_pll_postdiv gpll0 = {
>  	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "gpll0",
> -		.parent_names = (const char *[]){ "gpll0_early" },
> +		.parent_hws = (const struct clk_hw*[]){
> +			&gpll0_early.clkr.hw,
> +		},
>  		.num_parents = 1,
>  		.ops = &clk_alpha_pll_postdiv_ops,
>  	},
> @@ -88,7 +96,9 @@ static struct clk_branch gcc_mmss_gpll0_div_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_mmss_gpll0_div_clk",
> -			.parent_names = (const char *[]){ "gpll0" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&gpll0.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -103,7 +113,9 @@ static struct clk_branch gcc_mss_gpll0_div_clk = {
>  		.enable_mask = BIT(2),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_mss_gpll0_div_clk",
> -			.parent_names = (const char *[]){ "gpll0" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&gpll0.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops
> @@ -119,7 +131,9 @@ static struct clk_alpha_pll gpll4_early = {
>  		.enable_mask = BIT(4),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gpll4_early",
> -			.parent_names = (const char *[]){ "xo" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&xo.hw,

Same question here, and all the other conversions for "xo".

> +			},
>  			.num_parents = 1,
>  			.ops = &clk_alpha_pll_ops,
>  		},
> @@ -131,7 +145,9 @@ static struct clk_alpha_pll_postdiv gpll4 = {
>  	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "gpll4",
> -		.parent_names = (const char *[]){ "gpll4_early" },
> +		.parent_hws = (const struct clk_hw*[]){
> +			&gpll4_early.clkr.hw,
> +		},
>  		.num_parents = 1,
>  		.ops = &clk_alpha_pll_postdiv_ops,
>  	},
> @@ -141,8 +157,8 @@ static const struct parent_map gcc_sleep_clk_map[] = {
>  	{ P_SLEEP_CLK, 5 }
>  };
>  
> -static const char * const gcc_sleep_clk[] = {
> -	"sleep_clk"
> +static const struct clk_parent_data gcc_sleep_clk[] = {
> +	{ .fw_name = "sleep_clk", .name = "sleep_clk" }

This should also be added to the DT.

>  };
>  
>  static const struct parent_map gcc_xo_gpll0_map[] = {
> @@ -150,9 +166,9 @@ static const struct parent_map gcc_xo_gpll0_map[] = {
>  	{ P_GPLL0, 1 }
>  };
>  
> -static const char * const gcc_xo_gpll0[] = {
> -	"xo",
> -	"gpll0"
> +static const struct clk_parent_data gcc_xo_gpll0[] = {
> +	{ .hw = &xo.hw },
> +	{ .hw = &gpll0.clkr.hw }
>  };
>  
>  static const struct parent_map gcc_xo_sleep_clk_map[] = {
> @@ -160,9 +176,9 @@ static const struct parent_map gcc_xo_sleep_clk_map[] = {
>  	{ P_SLEEP_CLK, 5 }
>  };
>  
> -static const char * const gcc_xo_sleep_clk[] = {
> -	"xo",
> -	"sleep_clk"
> +static const struct clk_parent_data gcc_xo_sleep_clk[] = {
> +	{ .hw = &xo.hw },
> +	{ .fw_name = "sleep_clk", .name = "sleep_clk" }
>  };
>  
>  static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
> @@ -171,10 +187,10 @@ static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
>  	{ P_GPLL0_EARLY_DIV, 6 }
>  };
>  
> -static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
> -	"xo",
> -	"gpll0",
> -	"gpll0_early_div"
> +static const struct clk_parent_data gcc_xo_gpll0_gpll0_early_div[] = {
> +	{ .hw = &xo.hw },
> +	{ .hw = &gpll0.clkr.hw },
> +	{ .hw = &gpll0_early_div.hw }
>  };
>  
>  static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
> @@ -183,10 +199,10 @@ static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
>  	{ P_GPLL4, 5 }
>  };
>  
> -static const char * const gcc_xo_gpll0_gpll4[] = {
> -	"xo",
> -	"gpll0",
> -	"gpll4"
> +static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
> +	{ .hw = &xo.hw },
> +	{ .hw = &gpll0.clkr.hw },
> +	{ .hw = &gpll4.clkr.hw }
>  };
>  
>  static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
> @@ -195,10 +211,10 @@ static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
>  	{ P_AUD_REF_CLK, 2 }
>  };
>  
> -static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
> -	"xo",
> -	"gpll0",
> -	"aud_ref_clk"
> +static const struct clk_parent_data gcc_xo_gpll0_aud_ref_clk[] = {
> +	{ .hw = &xo.hw },
> +	{ .hw = &gpll0.clkr.hw },
> +	{ .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }

Don't forget to add this clock to the DT-bindings.

>  };
>  
>  static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
> @@ -208,11 +224,11 @@ static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
>  	{ P_GPLL0_EARLY_DIV, 6 }
>  };
>  
> -static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
> -	"xo",
> -	"gpll0",
> -	"sleep_clk",
> -	"gpll0_early_div"
> +static const struct clk_parent_data gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
> +	{ .hw = &xo.hw },
> +	{ .hw = &gpll0.clkr.hw },
> +	{ .fw_name = "sleep_clk", .name = "sleep_clk" },
> +	{ .hw = &gpll0_early_div.hw }
>  };
>  
>  static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
> @@ -222,11 +238,11 @@ static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
>  	{ P_GPLL0_EARLY_DIV, 6 }
>  };
>  
> -static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
> -	"xo",
> -	"gpll0",
> -	"gpll4",
> -	"gpll0_early_div"
> +static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
> +	{ .hw = &xo.hw },
> +	{ .hw = &gpll0.clkr.hw },
> +	{ .hw = &gpll4.clkr.hw },
> +	{ .hw = &gpll0_early_div.hw }
>  };
>  
>  static const struct freq_tbl ftbl_system_noc_clk_src[] = {
> @@ -246,7 +262,7 @@ static struct clk_rcg2 system_noc_clk_src = {
>  	.freq_tbl = ftbl_system_noc_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "system_noc_clk_src",
> -		.parent_names = gcc_xo_gpll0_gpll0_early_div,
> +		.parent_data = gcc_xo_gpll0_gpll0_early_div,
>  		.num_parents = 3,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -266,7 +282,7 @@ static struct clk_rcg2 config_noc_clk_src = {
>  	.freq_tbl = ftbl_config_noc_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "config_noc_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -288,7 +304,7 @@ static struct clk_rcg2 periph_noc_clk_src = {
>  	.freq_tbl = ftbl_periph_noc_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "periph_noc_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -309,7 +325,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
>  	.freq_tbl = ftbl_usb30_master_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "usb30_master_clk_src",
> -		.parent_names = gcc_xo_gpll0_gpll0_early_div,
> +		.parent_data = gcc_xo_gpll0_gpll0_early_div,
>  		.num_parents = 3,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -327,7 +343,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
>  	.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "usb30_mock_utmi_clk_src",
> -		.parent_names = gcc_xo_gpll0_gpll0_early_div,
> +		.parent_data = gcc_xo_gpll0_gpll0_early_div,
>  		.num_parents = 3,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -345,7 +361,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = {
>  	.freq_tbl = ftbl_usb3_phy_aux_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "usb3_phy_aux_clk_src",
> -		.parent_names = gcc_xo_sleep_clk,
> +		.parent_data = gcc_xo_sleep_clk,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -364,7 +380,7 @@ static struct clk_rcg2 usb20_master_clk_src = {
>  	.freq_tbl = ftbl_usb20_master_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "usb20_master_clk_src",
> -		.parent_names = gcc_xo_gpll0_gpll0_early_div,
> +		.parent_data = gcc_xo_gpll0_gpll0_early_div,
>  		.num_parents = 3,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -377,7 +393,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = {
>  	.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "usb20_mock_utmi_clk_src",
> -		.parent_names = gcc_xo_gpll0_gpll0_early_div,
> +		.parent_data = gcc_xo_gpll0_gpll0_early_div,
>  		.num_parents = 3,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -403,7 +419,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
>  	.freq_tbl = ftbl_sdcc1_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "sdcc1_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
> +		.parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
>  		.num_parents = 4,
>  		.ops = &clk_rcg2_floor_ops,
>  	},
> @@ -423,7 +439,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = {
>  	.freq_tbl = ftbl_sdcc1_ice_core_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "sdcc1_ice_core_clk_src",
> -		.parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
> +		.parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
>  		.num_parents = 4,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -448,7 +464,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
>  	.freq_tbl = ftbl_sdcc2_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "sdcc2_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0_gpll4,
> +		.parent_data = gcc_xo_gpll0_gpll4,
>  		.num_parents = 3,
>  		.ops = &clk_rcg2_floor_ops,
>  	},
> @@ -462,7 +478,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
>  	.freq_tbl = ftbl_sdcc2_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "sdcc3_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0_gpll4,
> +		.parent_data = gcc_xo_gpll0_gpll4,
>  		.num_parents = 3,
>  		.ops = &clk_rcg2_floor_ops,
>  	},
> @@ -486,7 +502,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
>  	.freq_tbl = ftbl_sdcc4_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "sdcc4_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_floor_ops,
>  	},
> @@ -511,7 +527,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup1_spi_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -530,7 +546,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup1_i2c_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -563,7 +579,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_uart1_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -577,7 +593,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup2_spi_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -590,7 +606,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup2_i2c_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -604,7 +620,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_uart2_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -618,7 +634,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup3_spi_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -631,7 +647,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup3_i2c_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -645,7 +661,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_uart3_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -659,7 +675,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup4_spi_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -672,7 +688,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup4_i2c_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -686,7 +702,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_uart4_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -700,7 +716,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup5_spi_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -713,7 +729,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup5_i2c_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -727,7 +743,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_uart5_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -741,7 +757,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup6_spi_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -754,7 +770,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_qup6_i2c_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -768,7 +784,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp1_uart6_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -782,7 +798,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup1_spi_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -795,7 +811,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup1_i2c_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -809,7 +825,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_uart1_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -823,7 +839,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup2_spi_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -836,7 +852,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup2_i2c_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -850,7 +866,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_uart2_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -864,7 +880,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup3_spi_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -877,7 +893,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup3_i2c_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -891,7 +907,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_uart3_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -905,7 +921,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup4_spi_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -918,7 +934,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup4_i2c_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -932,7 +948,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_uart4_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -946,7 +962,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup5_spi_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -959,7 +975,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup5_i2c_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -973,7 +989,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_uart5_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -987,7 +1003,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup6_spi_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -1000,7 +1016,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_qup6_i2c_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -1014,7 +1030,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
>  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "blsp2_uart6_apps_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -1032,7 +1048,7 @@ static struct clk_rcg2 pdm2_clk_src = {
>  	.freq_tbl = ftbl_pdm2_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "pdm2_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -1051,7 +1067,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
>  	.freq_tbl = ftbl_tsif_ref_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "tsif_ref_clk_src",
> -		.parent_names = gcc_xo_gpll0_aud_ref_clk,
> +		.parent_data = gcc_xo_gpll0_aud_ref_clk,
>  		.num_parents = 3,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -1063,7 +1079,7 @@ static struct clk_rcg2 gcc_sleep_clk_src = {
>  	.parent_map = gcc_sleep_clk_map,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "gcc_sleep_clk_src",
> -		.parent_names = gcc_sleep_clk,
> +		.parent_data = gcc_sleep_clk,
>  		.num_parents = 1,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -1076,7 +1092,7 @@ static struct clk_rcg2 hmss_rbcpr_clk_src = {
>  	.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "hmss_rbcpr_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -1088,7 +1104,7 @@ static struct clk_rcg2 hmss_gpll0_clk_src = {
>  	.parent_map = gcc_xo_gpll0_map,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "hmss_gpll0_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -1109,7 +1125,7 @@ static struct clk_rcg2 gp1_clk_src = {
>  	.freq_tbl = ftbl_gp1_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "gp1_clk_src",
> -		.parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
> +		.parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
>  		.num_parents = 4,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -1123,7 +1139,7 @@ static struct clk_rcg2 gp2_clk_src = {
>  	.freq_tbl = ftbl_gp1_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "gp2_clk_src",
> -		.parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
> +		.parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
>  		.num_parents = 4,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -1137,7 +1153,7 @@ static struct clk_rcg2 gp3_clk_src = {
>  	.freq_tbl = ftbl_gp1_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "gp3_clk_src",
> -		.parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
> +		.parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
>  		.num_parents = 4,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -1156,7 +1172,7 @@ static struct clk_rcg2 pcie_aux_clk_src = {
>  	.freq_tbl = ftbl_pcie_aux_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "pcie_aux_clk_src",
> -		.parent_names = gcc_xo_sleep_clk,
> +		.parent_data = gcc_xo_sleep_clk,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -1177,7 +1193,7 @@ static struct clk_rcg2 ufs_axi_clk_src = {
>  	.freq_tbl = ftbl_ufs_axi_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "ufs_axi_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -1197,7 +1213,7 @@ static struct clk_rcg2 ufs_ice_core_clk_src = {
>  	.freq_tbl = ftbl_ufs_ice_core_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "ufs_ice_core_clk_src",
> -		.parent_names = gcc_xo_gpll0,
> +		.parent_data = gcc_xo_gpll0,
>  		.num_parents = 2,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -1218,7 +1234,7 @@ static struct clk_rcg2 qspi_ser_clk_src = {
>  	.freq_tbl = ftbl_qspi_ser_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "qspi_ser_clk_src",
> -		.parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
> +		.parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
>  		.num_parents = 4,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -1231,7 +1247,9 @@ static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_sys_noc_usb3_axi_clk",
> -			.parent_names = (const char *[]){ "usb30_master_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&usb30_master_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1246,7 +1264,9 @@ static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_sys_noc_ufs_axi_clk",
> -			.parent_names = (const char *[]){ "ufs_axi_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&ufs_axi_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1261,7 +1281,9 @@ static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_periph_noc_usb20_ahb_clk",
> -			.parent_names = (const char *[]){ "usb20_master_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&usb20_master_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1276,7 +1298,9 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_mmss_noc_cfg_ahb_clk",
> -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&config_noc_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>  			.ops = &clk_branch2_ops,
> @@ -1304,7 +1328,9 @@ static struct clk_branch gcc_usb30_master_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_usb30_master_clk",
> -			.parent_names = (const char *[]){ "usb30_master_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&usb30_master_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1319,7 +1345,9 @@ static struct clk_branch gcc_usb30_sleep_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_usb30_sleep_clk",
> -			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&gcc_sleep_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1334,7 +1362,9 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_usb30_mock_utmi_clk",
> -			.parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&usb30_mock_utmi_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1349,7 +1379,9 @@ static struct clk_branch gcc_usb3_phy_aux_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_usb3_phy_aux_clk",
> -			.parent_names = (const char *[]){ "usb3_phy_aux_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&usb3_phy_aux_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1365,7 +1397,9 @@ static struct clk_branch gcc_usb3_phy_pipe_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_usb3_phy_pipe_clk",
> -			.parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "usb3_phy_pipe_clk_src", .name = "usb3_phy_pipe_clk_src",

Don't forget to add this clock to the DT-bindings.

> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1380,7 +1414,9 @@ static struct clk_branch gcc_usb20_master_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_usb20_master_clk",
> -			.parent_names = (const char *[]){ "usb20_master_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&usb20_master_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1395,7 +1431,9 @@ static struct clk_branch gcc_usb20_sleep_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_usb20_sleep_clk",
> -			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&gcc_sleep_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1410,7 +1448,9 @@ static struct clk_branch gcc_usb20_mock_utmi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_usb20_mock_utmi_clk",
> -			.parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&usb20_mock_utmi_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1425,7 +1465,9 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_usb_phy_cfg_ahb2phy_clk",
> -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",

Don't forget to add this clock to the DT-bindings.

> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1440,7 +1482,9 @@ static struct clk_branch gcc_sdcc1_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_sdcc1_apps_clk",
> -			.parent_names = (const char *[]){ "sdcc1_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&sdcc1_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1455,7 +1499,9 @@ static struct clk_branch gcc_sdcc1_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_sdcc1_ahb_clk",
> -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1470,7 +1516,9 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_sdcc1_ice_core_clk",
> -			.parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&sdcc1_ice_core_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1485,7 +1533,9 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_sdcc2_apps_clk",
> -			.parent_names = (const char *[]){ "sdcc2_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&sdcc2_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1500,7 +1550,9 @@ static struct clk_branch gcc_sdcc2_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_sdcc2_ahb_clk",
> -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1515,7 +1567,9 @@ static struct clk_branch gcc_sdcc3_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_sdcc3_apps_clk",
> -			.parent_names = (const char *[]){ "sdcc3_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&sdcc3_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1530,7 +1584,9 @@ static struct clk_branch gcc_sdcc3_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_sdcc3_ahb_clk",
> -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1545,7 +1601,9 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_sdcc4_apps_clk",
> -			.parent_names = (const char *[]){ "sdcc4_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&sdcc4_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1560,7 +1618,9 @@ static struct clk_branch gcc_sdcc4_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_sdcc4_ahb_clk",
> -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1576,7 +1636,9 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
>  		.enable_mask = BIT(17),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp1_ahb_clk",
> -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1592,7 +1654,9 @@ static struct clk_branch gcc_blsp1_sleep_clk = {
>  		.enable_mask = BIT(16),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp1_sleep_clk",
> -			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&gcc_sleep_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1607,7 +1671,9 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp1_qup1_spi_apps_clk",
> -			.parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp1_qup1_spi_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1622,7 +1688,9 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp1_qup1_i2c_apps_clk",
> -			.parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1637,7 +1705,9 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp1_uart1_apps_clk",
> -			.parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp1_uart1_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1652,7 +1722,9 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp1_qup2_spi_apps_clk",
> -			.parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp1_qup2_spi_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1667,7 +1739,9 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp1_qup2_i2c_apps_clk",
> -			.parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1682,7 +1756,9 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp1_uart2_apps_clk",
> -			.parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp1_uart2_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1697,7 +1773,9 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp1_qup3_spi_apps_clk",
> -			.parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp1_qup3_spi_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1712,7 +1790,9 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp1_qup3_i2c_apps_clk",
> -			.parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1727,7 +1807,9 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp1_uart3_apps_clk",
> -			.parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp1_uart3_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1742,7 +1824,9 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp1_qup4_spi_apps_clk",
> -			.parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp1_qup4_spi_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1757,7 +1841,9 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp1_qup4_i2c_apps_clk",
> -			.parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp1_qup4_i2c_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1772,7 +1858,9 @@ static struct clk_branch gcc_blsp1_uart4_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp1_uart4_apps_clk",
> -			.parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp1_uart4_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1787,7 +1875,9 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp1_qup5_spi_apps_clk",
> -			.parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp1_qup5_spi_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1802,7 +1892,9 @@ static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp1_qup5_i2c_apps_clk",
> -			.parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp1_qup5_i2c_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1817,7 +1909,9 @@ static struct clk_branch gcc_blsp1_uart5_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp1_uart5_apps_clk",
> -			.parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp1_uart5_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1832,7 +1926,9 @@ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp1_qup6_spi_apps_clk",
> -			.parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp1_qup6_spi_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1847,7 +1943,9 @@ static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp1_qup6_i2c_apps_clk",
> -			.parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp1_qup6_i2c_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1862,7 +1960,9 @@ static struct clk_branch gcc_blsp1_uart6_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp1_uart6_apps_clk",
> -			.parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp1_uart6_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1878,7 +1978,9 @@ static struct clk_branch gcc_blsp2_ahb_clk = {
>  		.enable_mask = BIT(15),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp2_ahb_clk",
> -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1894,7 +1996,9 @@ static struct clk_branch gcc_blsp2_sleep_clk = {
>  		.enable_mask = BIT(14),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp2_sleep_clk",
> -			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&gcc_sleep_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1909,7 +2013,9 @@ static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp2_qup1_spi_apps_clk",
> -			.parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp2_qup1_spi_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1924,7 +2030,9 @@ static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp2_qup1_i2c_apps_clk",
> -			.parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp2_qup1_i2c_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1939,7 +2047,9 @@ static struct clk_branch gcc_blsp2_uart1_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp2_uart1_apps_clk",
> -			.parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp2_uart1_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1954,7 +2064,9 @@ static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp2_qup2_spi_apps_clk",
> -			.parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp2_qup2_spi_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1969,7 +2081,9 @@ static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp2_qup2_i2c_apps_clk",
> -			.parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp2_qup2_i2c_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1984,7 +2098,9 @@ static struct clk_branch gcc_blsp2_uart2_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp2_uart2_apps_clk",
> -			.parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp2_uart2_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -1999,7 +2115,9 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp2_qup3_spi_apps_clk",
> -			.parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp2_qup3_spi_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2014,7 +2132,9 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp2_qup3_i2c_apps_clk",
> -			.parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp2_qup3_i2c_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2029,7 +2149,9 @@ static struct clk_branch gcc_blsp2_uart3_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp2_uart3_apps_clk",
> -			.parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp2_uart3_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2044,7 +2166,9 @@ static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp2_qup4_spi_apps_clk",
> -			.parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp2_qup4_spi_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2059,7 +2183,9 @@ static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp2_qup4_i2c_apps_clk",
> -			.parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp2_qup4_i2c_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2074,7 +2200,9 @@ static struct clk_branch gcc_blsp2_uart4_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp2_uart4_apps_clk",
> -			.parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp2_uart4_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2089,7 +2217,9 @@ static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp2_qup5_spi_apps_clk",
> -			.parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp2_qup5_spi_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2104,7 +2234,9 @@ static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp2_qup5_i2c_apps_clk",
> -			.parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp2_qup5_i2c_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2119,7 +2251,9 @@ static struct clk_branch gcc_blsp2_uart5_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp2_uart5_apps_clk",
> -			.parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp2_uart5_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2134,7 +2268,9 @@ static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp2_qup6_spi_apps_clk",
> -			.parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp2_qup6_spi_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2149,7 +2285,9 @@ static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp2_qup6_i2c_apps_clk",
> -			.parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp2_qup6_i2c_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2164,7 +2302,9 @@ static struct clk_branch gcc_blsp2_uart6_apps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_blsp2_uart6_apps_clk",
> -			.parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&blsp2_uart6_apps_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2179,7 +2319,9 @@ static struct clk_branch gcc_pdm_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_pdm_ahb_clk",
> -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2194,7 +2336,9 @@ static struct clk_branch gcc_pdm2_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_pdm2_clk",
> -			.parent_names = (const char *[]){ "pdm2_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&pdm2_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2210,7 +2354,9 @@ static struct clk_branch gcc_prng_ahb_clk = {
>  		.enable_mask = BIT(13),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_prng_ahb_clk",
> -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&config_noc_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2225,7 +2371,9 @@ static struct clk_branch gcc_tsif_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_tsif_ahb_clk",
> -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2240,7 +2388,9 @@ static struct clk_branch gcc_tsif_ref_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_tsif_ref_clk",
> -			.parent_names = (const char *[]){ "tsif_ref_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&tsif_ref_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2255,7 +2405,9 @@ static struct clk_branch gcc_tsif_inactivity_timers_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_tsif_inactivity_timers_clk",
> -			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&gcc_sleep_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2271,7 +2423,9 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
>  		.enable_mask = BIT(10),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_boot_rom_ahb_clk",
> -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&config_noc_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2299,7 +2453,9 @@ static struct clk_branch gcc_hmss_rbcpr_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_hmss_rbcpr_clk",
> -			.parent_names = (const char *[]){ "hmss_rbcpr_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&hmss_rbcpr_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2314,7 +2470,9 @@ static struct clk_branch gcc_gp1_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_gp1_clk",
> -			.parent_names = (const char *[]){ "gp1_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&gp1_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2329,7 +2487,9 @@ static struct clk_branch gcc_gp2_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_gp2_clk",
> -			.parent_names = (const char *[]){ "gp2_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&gp2_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2344,7 +2504,9 @@ static struct clk_branch gcc_gp3_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_gp3_clk",
> -			.parent_names = (const char *[]){ "gp3_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&gp3_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2359,7 +2521,9 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_pcie_0_slv_axi_clk",
> -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&system_noc_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2374,7 +2538,9 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_pcie_0_mstr_axi_clk",
> -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&system_noc_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2389,7 +2555,9 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_pcie_0_cfg_ahb_clk",
> -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&config_noc_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2404,7 +2572,9 @@ static struct clk_branch gcc_pcie_0_aux_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_pcie_0_aux_clk",
> -			.parent_names = (const char *[]){ "pcie_aux_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&pcie_aux_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2420,7 +2590,9 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_pcie_0_pipe_clk",
> -			.parent_names = (const char *[]){ "pcie_0_pipe_clk_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "pcie_0_pipe_clk_src", .name = "pcie_0_pipe_clk_src",

Don't forget to add this clock to the DT-bindings.

> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2435,7 +2607,9 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_pcie_1_slv_axi_clk",
> -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&system_noc_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2450,7 +2624,9 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_pcie_1_mstr_axi_clk",
> -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&system_noc_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2465,7 +2641,9 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_pcie_1_cfg_ahb_clk",
> -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&config_noc_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2480,7 +2658,9 @@ static struct clk_branch gcc_pcie_1_aux_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_pcie_1_aux_clk",
> -			.parent_names = (const char *[]){ "pcie_aux_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&pcie_aux_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2496,7 +2676,9 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_pcie_1_pipe_clk",
> -			.parent_names = (const char *[]){ "pcie_1_pipe_clk_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "pcie_1_pipe_clk_src", .name = "pcie_1_pipe_clk_src",

Don't forget to add this clock to the DT-bindings.

> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2511,7 +2693,9 @@ static struct clk_branch gcc_pcie_2_slv_axi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_pcie_2_slv_axi_clk",
> -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&system_noc_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2526,7 +2710,9 @@ static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_pcie_2_mstr_axi_clk",
> -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&system_noc_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2541,7 +2727,9 @@ static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_pcie_2_cfg_ahb_clk",
> -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&config_noc_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2556,7 +2744,9 @@ static struct clk_branch gcc_pcie_2_aux_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_pcie_2_aux_clk",
> -			.parent_names = (const char *[]){ "pcie_aux_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&pcie_aux_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2572,7 +2762,9 @@ static struct clk_branch gcc_pcie_2_pipe_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_pcie_2_pipe_clk",
> -			.parent_names = (const char *[]){ "pcie_2_pipe_clk_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "pcie_2_pipe_clk_src", .name = "pcie_2_pipe_clk_src",

Don't forget to add this clock to the DT-bindings.

> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2587,7 +2779,9 @@ static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_pcie_phy_cfg_ahb_clk",
> -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&config_noc_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2602,7 +2796,9 @@ static struct clk_branch gcc_pcie_phy_aux_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_pcie_phy_aux_clk",
> -			.parent_names = (const char *[]){ "pcie_aux_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&pcie_aux_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2617,7 +2813,9 @@ static struct clk_branch gcc_ufs_axi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_ufs_axi_clk",
> -			.parent_names = (const char *[]){ "ufs_axi_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&ufs_axi_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2632,7 +2830,9 @@ static struct clk_branch gcc_ufs_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_ufs_ahb_clk",
> -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&config_noc_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2645,7 +2845,9 @@ static struct clk_fixed_factor ufs_tx_cfg_clk_src = {
>  	.div = 16,
>  	.hw.init = &(struct clk_init_data){
>  		.name = "ufs_tx_cfg_clk_src",
> -		.parent_names = (const char *[]){ "ufs_axi_clk_src" },
> +		.parent_hws = (const struct clk_hw*[]){
> +			&ufs_axi_clk_src.clkr.hw,
> +		},
>  		.num_parents = 1,
>  		.flags = CLK_SET_RATE_PARENT,
>  		.ops = &clk_fixed_factor_ops,
> @@ -2659,7 +2861,9 @@ static struct clk_branch gcc_ufs_tx_cfg_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_ufs_tx_cfg_clk",
> -			.parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&ufs_tx_cfg_clk_src.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2672,7 +2876,9 @@ static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
>  	.div = 16,
>  	.hw.init = &(struct clk_init_data){
>  		.name = "ufs_rx_cfg_clk_src",
> -		.parent_names = (const char *[]){ "ufs_axi_clk_src" },
> +		.parent_hws = (const struct clk_hw*[]){
> +			&ufs_axi_clk_src.clkr.hw,
> +		},
>  		.num_parents = 1,
>  		.flags = CLK_SET_RATE_PARENT,
>  		.ops = &clk_fixed_factor_ops,
> @@ -2712,7 +2918,9 @@ static struct clk_branch gcc_ufs_rx_cfg_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_ufs_rx_cfg_clk",
> -			.parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&ufs_rx_cfg_clk_src.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2728,7 +2936,9 @@ static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_ufs_tx_symbol_0_clk",
> -			.parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "ufs_tx_symbol_0_clk_src", .name = "ufs_tx_symbol_0_clk_src",

Don't forget to add this clock to the DT-bindings.

> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2744,7 +2954,9 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_ufs_rx_symbol_0_clk",
> -			.parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "ufs_rx_symbol_0_clk_src", .name = "ufs_rx_symbol_0_clk_src",

Don't forget to add this clock to the DT-bindings.

> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2760,7 +2972,9 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_ufs_rx_symbol_1_clk",
> -			.parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "ufs_rx_symbol_1_clk_src", .name = "ufs_rx_symbol_1_clk_src",

Don't forget to add this clock to the DT-bindings.

- Marijn

> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2773,7 +2987,9 @@ static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {
>  	.div = 2,
>  	.hw.init = &(struct clk_init_data){
>  		.name = "ufs_ice_core_postdiv_clk_src",
> -		.parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
> +		.parent_hws = (const struct clk_hw*[]){
> +			&ufs_ice_core_clk_src.clkr.hw,
> +		},
>  		.num_parents = 1,
>  		.flags = CLK_SET_RATE_PARENT,
>  		.ops = &clk_fixed_factor_ops,
> @@ -2787,7 +3003,9 @@ static struct clk_branch gcc_ufs_unipro_core_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_ufs_unipro_core_clk",
> -			.parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&ufs_ice_core_postdiv_clk_src.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2802,7 +3020,9 @@ static struct clk_branch gcc_ufs_ice_core_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_ufs_ice_core_clk",
> -			.parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&ufs_ice_core_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2841,7 +3061,9 @@ static struct clk_branch gcc_aggre0_snoc_axi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_aggre0_snoc_axi_clk",
> -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&system_noc_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
>  			.ops = &clk_branch2_ops,
> @@ -2856,7 +3078,9 @@ static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_aggre0_cnoc_ahb_clk",
> -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&config_noc_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
>  			.ops = &clk_branch2_ops,
> @@ -2871,7 +3095,9 @@ static struct clk_branch gcc_smmu_aggre0_axi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_smmu_aggre0_axi_clk",
> -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&system_noc_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
>  			.ops = &clk_branch2_ops,
> @@ -2886,7 +3112,9 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_smmu_aggre0_ahb_clk",
> -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&config_noc_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
>  			.ops = &clk_branch2_ops,
> @@ -2901,7 +3129,9 @@ static struct clk_branch gcc_aggre2_ufs_axi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_aggre2_ufs_axi_clk",
> -			.parent_names = (const char *[]){ "ufs_axi_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&ufs_axi_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2916,7 +3146,9 @@ static struct clk_branch gcc_aggre2_usb3_axi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_aggre2_usb3_axi_clk",
> -			.parent_names = (const char *[]){ "usb30_master_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&usb30_master_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2931,7 +3163,9 @@ static struct clk_branch gcc_dcc_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_dcc_ahb_clk",
> -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&config_noc_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
>  		},
> @@ -2945,7 +3179,9 @@ static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",
> -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&config_noc_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
>  		},
> @@ -2959,7 +3195,9 @@ static struct clk_branch gcc_qspi_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_qspi_ahb_clk",
> -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -2974,7 +3212,9 @@ static struct clk_branch gcc_qspi_ser_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_qspi_ser_clk",
> -			.parent_names = (const char *[]){ "qspi_ser_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&qspi_ser_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
>  			.ops = &clk_branch2_ops,
> @@ -3108,7 +3348,9 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_mss_cfg_ahb_clk",
> -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&config_noc_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
>  		},
> @@ -3122,7 +3364,9 @@ static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_mss_mnoc_bimc_axi_clk",
> -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&system_noc_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
>  		},
> @@ -3136,7 +3380,9 @@ static struct clk_branch gcc_mss_snoc_axi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_mss_snoc_axi_clk",
> -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&system_noc_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
>  		},
> @@ -3150,7 +3396,9 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "gcc_mss_q6_bimc_axi_clk",
> -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> +			.parent_hws = (const struct clk_hw*[]){
> +				&system_noc_clk_src.clkr.hw,
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
>  		},
> -- 
> 2.33.0
> 

Re: [PATCH 09/11] clk: qcom: gcc-msm8996: move clock parent tables down

[Marijn Suijten]

On 2021-12-08 20:54:28, Dmitry Baryshkov wrote:
> Move clock parent tables down, after the GPLL declrataions, so that we
> can use gpll hw clock fields in the next commit.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>

> ---
>  drivers/clk/qcom/gcc-msm8996.c | 184 ++++++++++++++++-----------------
>  1 file changed, 92 insertions(+), 92 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
> index 3acefe16355c..c2f9ae729d1e 100644
> --- a/drivers/clk/qcom/gcc-msm8996.c
> +++ b/drivers/clk/qcom/gcc-msm8996.c
> @@ -33,98 +33,6 @@ enum {
>  	P_AUD_REF_CLK,
>  };
>  
> -static const struct parent_map gcc_sleep_clk_map[] = {
> -	{ P_SLEEP_CLK, 5 }
> -};
> -
> -static const char * const gcc_sleep_clk[] = {
> -	"sleep_clk"
> -};
> -
> -static const struct parent_map gcc_xo_gpll0_map[] = {
> -	{ P_XO, 0 },
> -	{ P_GPLL0, 1 }
> -};
> -
> -static const char * const gcc_xo_gpll0[] = {
> -	"xo",
> -	"gpll0"
> -};
> -
> -static const struct parent_map gcc_xo_sleep_clk_map[] = {
> -	{ P_XO, 0 },
> -	{ P_SLEEP_CLK, 5 }
> -};
> -
> -static const char * const gcc_xo_sleep_clk[] = {
> -	"xo",
> -	"sleep_clk"
> -};
> -
> -static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
> -	{ P_XO, 0 },
> -	{ P_GPLL0, 1 },
> -	{ P_GPLL0_EARLY_DIV, 6 }
> -};
> -
> -static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
> -	"xo",
> -	"gpll0",
> -	"gpll0_early_div"
> -};
> -
> -static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
> -	{ P_XO, 0 },
> -	{ P_GPLL0, 1 },
> -	{ P_GPLL4, 5 }
> -};
> -
> -static const char * const gcc_xo_gpll0_gpll4[] = {
> -	"xo",
> -	"gpll0",
> -	"gpll4"
> -};
> -
> -static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
> -	{ P_XO, 0 },
> -	{ P_GPLL0, 1 },
> -	{ P_AUD_REF_CLK, 2 }
> -};
> -
> -static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
> -	"xo",
> -	"gpll0",
> -	"aud_ref_clk"
> -};
> -
> -static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
> -	{ P_XO, 0 },
> -	{ P_GPLL0, 1 },
> -	{ P_SLEEP_CLK, 5 },
> -	{ P_GPLL0_EARLY_DIV, 6 }
> -};
> -
> -static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
> -	"xo",
> -	"gpll0",
> -	"sleep_clk",
> -	"gpll0_early_div"
> -};
> -
> -static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
> -	{ P_XO, 0 },
> -	{ P_GPLL0, 1 },
> -	{ P_GPLL4, 5 },
> -	{ P_GPLL0_EARLY_DIV, 6 }
> -};
> -
> -static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
> -	"xo",
> -	"gpll0",
> -	"gpll4",
> -	"gpll0_early_div"
> -};
> -
>  static struct clk_fixed_factor xo = {
>  	.mult = 1,
>  	.div = 1,
> @@ -229,6 +137,98 @@ static struct clk_alpha_pll_postdiv gpll4 = {
>  	},
>  };
>  
> +static const struct parent_map gcc_sleep_clk_map[] = {
> +	{ P_SLEEP_CLK, 5 }
> +};
> +
> +static const char * const gcc_sleep_clk[] = {
> +	"sleep_clk"
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_map[] = {
> +	{ P_XO, 0 },
> +	{ P_GPLL0, 1 }
> +};
> +
> +static const char * const gcc_xo_gpll0[] = {
> +	"xo",
> +	"gpll0"
> +};
> +
> +static const struct parent_map gcc_xo_sleep_clk_map[] = {
> +	{ P_XO, 0 },
> +	{ P_SLEEP_CLK, 5 }
> +};
> +
> +static const char * const gcc_xo_sleep_clk[] = {
> +	"xo",
> +	"sleep_clk"
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
> +	{ P_XO, 0 },
> +	{ P_GPLL0, 1 },
> +	{ P_GPLL0_EARLY_DIV, 6 }
> +};
> +
> +static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
> +	"xo",
> +	"gpll0",
> +	"gpll0_early_div"
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
> +	{ P_XO, 0 },
> +	{ P_GPLL0, 1 },
> +	{ P_GPLL4, 5 }
> +};
> +
> +static const char * const gcc_xo_gpll0_gpll4[] = {
> +	"xo",
> +	"gpll0",
> +	"gpll4"
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
> +	{ P_XO, 0 },
> +	{ P_GPLL0, 1 },
> +	{ P_AUD_REF_CLK, 2 }
> +};
> +
> +static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
> +	"xo",
> +	"gpll0",
> +	"aud_ref_clk"
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
> +	{ P_XO, 0 },
> +	{ P_GPLL0, 1 },
> +	{ P_SLEEP_CLK, 5 },
> +	{ P_GPLL0_EARLY_DIV, 6 }
> +};
> +
> +static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
> +	"xo",
> +	"gpll0",
> +	"sleep_clk",
> +	"gpll0_early_div"
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
> +	{ P_XO, 0 },
> +	{ P_GPLL0, 1 },
> +	{ P_GPLL4, 5 },
> +	{ P_GPLL0_EARLY_DIV, 6 }
> +};
> +
> +static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
> +	"xo",
> +	"gpll0",
> +	"gpll4",
> +	"gpll0_early_div"
> +};
> +
>  static const struct freq_tbl ftbl_system_noc_clk_src[] = {
>  	F(19200000, P_XO, 1, 0, 0),
>  	F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
> -- 
> 2.33.0
> 

Re: [PATCH 06/11] clk: qcom: camcc-sc7180: use parent_hws instead of parent_data

[Marijn Suijten]

On 2021-12-08 20:54:25, Dmitry Baryshkov wrote:
> If all parents are specified as clk_hw, we can use parent_hws instead of
> parent_data.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>

> ---
>  drivers/clk/qcom/camcc-sc7180.c | 156 ++++++++++++++++----------------
>  1 file changed, 79 insertions(+), 77 deletions(-)
> 
> diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c
> index 3c15e551419f..e2b4804695f3 100644
> --- a/drivers/clk/qcom/camcc-sc7180.c
> +++ b/drivers/clk/qcom/camcc-sc7180.c
> @@ -126,7 +126,9 @@ static struct clk_fixed_factor cam_cc_pll2_out_early = {
>  	.div = 2,
>  	.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_pll2_out_early",
> -		.parent_names = (const char *[]){ "cam_cc_pll2" },
> +		.parent_hws = (const struct clk_hw*[]){
> +			&cam_cc_pll2.clkr.hw,
> +		},
>  		.num_parents = 1,
>  		.ops = &clk_fixed_factor_ops,
>  	},
> @@ -146,8 +148,8 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_aux = {
>  	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_AGERA],
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_pll2_out_aux",
> -		.parent_data = &(const struct clk_parent_data){
> -			.hw = &cam_cc_pll2.clkr.hw,
> +		.parent_hws = (const struct clk_hw*[]){
> +			&cam_cc_pll2.clkr.hw,
>  		},
>  		.num_parents = 1,
>  		.flags = CLK_SET_RATE_PARENT,
> @@ -729,8 +731,8 @@ static struct clk_branch cam_cc_bps_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_bps_ahb_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_slow_ahb_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -747,8 +749,8 @@ static struct clk_branch cam_cc_bps_areg_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_bps_areg_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_fast_ahb_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -778,8 +780,8 @@ static struct clk_branch cam_cc_bps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_bps_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_bps_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_bps_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -809,8 +811,8 @@ static struct clk_branch cam_cc_cci_0_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_cci_0_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_cci_0_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_cci_0_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -827,8 +829,8 @@ static struct clk_branch cam_cc_cci_1_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_cci_1_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_cci_1_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_cci_1_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -845,8 +847,8 @@ static struct clk_branch cam_cc_core_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_core_ahb_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_slow_ahb_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -863,8 +865,8 @@ static struct clk_branch cam_cc_cpas_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_cpas_ahb_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_slow_ahb_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -881,8 +883,8 @@ static struct clk_branch cam_cc_csi0phytimer_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_csi0phytimer_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_csi0phytimer_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_csi0phytimer_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -899,8 +901,8 @@ static struct clk_branch cam_cc_csi1phytimer_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_csi1phytimer_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_csi1phytimer_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_csi1phytimer_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -917,8 +919,8 @@ static struct clk_branch cam_cc_csi2phytimer_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_csi2phytimer_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_csi2phytimer_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_csi2phytimer_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -935,8 +937,8 @@ static struct clk_branch cam_cc_csi3phytimer_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_csi3phytimer_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_csi3phytimer_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_csi3phytimer_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -953,8 +955,8 @@ static struct clk_branch cam_cc_csiphy0_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_csiphy0_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_cphy_rx_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -971,8 +973,8 @@ static struct clk_branch cam_cc_csiphy1_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_csiphy1_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_cphy_rx_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -989,8 +991,8 @@ static struct clk_branch cam_cc_csiphy2_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_csiphy2_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_cphy_rx_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1007,8 +1009,8 @@ static struct clk_branch cam_cc_csiphy3_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_csiphy3_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_cphy_rx_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1025,8 +1027,8 @@ static struct clk_branch cam_cc_icp_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_icp_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_icp_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_icp_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1056,8 +1058,8 @@ static struct clk_branch cam_cc_ife_0_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ife_0_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_ife_0_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_ife_0_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1074,8 +1076,8 @@ static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ife_0_cphy_rx_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_cphy_rx_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1092,8 +1094,8 @@ static struct clk_branch cam_cc_ife_0_csid_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ife_0_csid_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_ife_0_csid_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_ife_0_csid_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1110,8 +1112,8 @@ static struct clk_branch cam_cc_ife_0_dsp_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ife_0_dsp_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_ife_0_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_ife_0_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1141,8 +1143,8 @@ static struct clk_branch cam_cc_ife_1_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ife_1_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_ife_1_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_ife_1_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1159,8 +1161,8 @@ static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ife_1_cphy_rx_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_cphy_rx_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1177,8 +1179,8 @@ static struct clk_branch cam_cc_ife_1_csid_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ife_1_csid_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_ife_1_csid_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_ife_1_csid_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1195,8 +1197,8 @@ static struct clk_branch cam_cc_ife_1_dsp_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ife_1_dsp_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_ife_1_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_ife_1_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1213,8 +1215,8 @@ static struct clk_branch cam_cc_ife_lite_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ife_lite_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_ife_lite_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_ife_lite_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1231,8 +1233,8 @@ static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ife_lite_cphy_rx_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_cphy_rx_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1249,8 +1251,8 @@ static struct clk_branch cam_cc_ife_lite_csid_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ife_lite_csid_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_ife_lite_csid_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_ife_lite_csid_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1267,8 +1269,8 @@ static struct clk_branch cam_cc_ipe_0_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ipe_0_ahb_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_slow_ahb_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1285,8 +1287,8 @@ static struct clk_branch cam_cc_ipe_0_areg_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ipe_0_areg_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_fast_ahb_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1316,8 +1318,8 @@ static struct clk_branch cam_cc_ipe_0_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ipe_0_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_ipe_0_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_ipe_0_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1334,8 +1336,8 @@ static struct clk_branch cam_cc_jpeg_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_jpeg_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_jpeg_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_jpeg_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1352,8 +1354,8 @@ static struct clk_branch cam_cc_lrme_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_lrme_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_lrme_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_lrme_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1370,8 +1372,8 @@ static struct clk_branch cam_cc_mclk0_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_mclk0_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_mclk0_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_mclk0_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1388,8 +1390,8 @@ static struct clk_branch cam_cc_mclk1_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_mclk1_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_mclk1_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_mclk1_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1406,8 +1408,8 @@ static struct clk_branch cam_cc_mclk2_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_mclk2_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_mclk2_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_mclk2_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1424,8 +1426,8 @@ static struct clk_branch cam_cc_mclk3_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_mclk3_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_mclk3_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_mclk3_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1442,8 +1444,8 @@ static struct clk_branch cam_cc_mclk4_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_mclk4_clk",
> -			.parent_data = &(const struct clk_parent_data){
> -				.hw = &cam_cc_mclk4_clk_src.clkr.hw,
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_mclk4_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> -- 
> 2.33.0
> 

Re: [PATCH 05/11] clk: qcom: camcc-sdm845: convert to parent data

[Marijn Suijten]

On 2021-12-08 20:54:24, Dmitry Baryshkov wrote:
> Convert the clock driver to specify parent data rather than parent
> names, to actually bind using 'clock-names' specified in the DTS rather
> than global clock names.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  drivers/clk/qcom/camcc-sdm845.c | 320 +++++++++++++++++---------------
>  1 file changed, 168 insertions(+), 152 deletions(-)
> 
> diff --git a/drivers/clk/qcom/camcc-sdm845.c b/drivers/clk/qcom/camcc-sdm845.c
> index 545c288a7f98..be3f95326965 100644
> --- a/drivers/clk/qcom/camcc-sdm845.c
> +++ b/drivers/clk/qcom/camcc-sdm845.c
> @@ -25,29 +25,15 @@ enum {
>  	P_CAM_CC_PLL3_OUT_EVEN,
>  };
>  
> -static const struct parent_map cam_cc_parent_map_0[] = {
> -	{ P_BI_TCXO, 0 },
> -	{ P_CAM_CC_PLL2_OUT_EVEN, 1 },
> -	{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
> -	{ P_CAM_CC_PLL3_OUT_EVEN, 5 },
> -	{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
> -};
> -
> -static const char * const cam_cc_parent_names_0[] = {
> -	"bi_tcxo",
> -	"cam_cc_pll2_out_even",
> -	"cam_cc_pll1_out_even",
> -	"cam_cc_pll3_out_even",
> -	"cam_cc_pll0_out_even",
> -};
> -

Much like the msm8996 patches you might want to perform this move in a
separate commit?

>  static struct clk_alpha_pll cam_cc_pll0 = {
>  	.offset = 0x0,
>  	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
>  	.clkr = {
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_pll0",
> -			.parent_names = (const char *[]){ "bi_tcxo" },
> +			.parent_data = &(const struct clk_parent_data){

The title says this change only uses parent_hws.  Perhaps you want to
adopt the `parent_hws/_data` title from the gcc-msm8996 patch?

> +				.fw_name = "bi_tcxo", .name = "bi_tcxo",

Would be nice to add this to the DT, eventually in a different series.

> +			},
>  			.num_parents = 1,
>  			.ops = &clk_alpha_pll_fabia_ops,
>  		},
> @@ -69,7 +55,9 @@ static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
>  	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_pll0_out_even",
> -		.parent_names = (const char *[]){ "cam_cc_pll0" },
> +		.parent_hws = (const struct clk_hw*[]){
> +			&cam_cc_pll0.clkr.hw,
> +		},
>  		.num_parents = 1,
>  		.ops = &clk_alpha_pll_postdiv_fabia_ops,
>  	},
> @@ -81,7 +69,9 @@ static struct clk_alpha_pll cam_cc_pll1 = {
>  	.clkr = {
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_pll1",
> -			.parent_names = (const char *[]){ "bi_tcxo" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "bi_tcxo", .name = "bi_tcxo",
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_alpha_pll_fabia_ops,
>  		},
> @@ -97,7 +87,9 @@ static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
>  	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_pll1_out_even",
> -		.parent_names = (const char *[]){ "cam_cc_pll1" },
> +		.parent_hws = (const struct clk_hw*[]){
> +			&cam_cc_pll1.clkr.hw,
> +		},
>  		.num_parents = 1,
>  		.ops = &clk_alpha_pll_postdiv_fabia_ops,
>  	},
> @@ -109,7 +101,9 @@ static struct clk_alpha_pll cam_cc_pll2 = {
>  	.clkr = {
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_pll2",
> -			.parent_names = (const char *[]){ "bi_tcxo" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "bi_tcxo", .name = "bi_tcxo",
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_alpha_pll_fabia_ops,
>  		},
> @@ -125,7 +119,9 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_even = {
>  	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_pll2_out_even",
> -		.parent_names = (const char *[]){ "cam_cc_pll2" },
> +		.parent_hws = (const struct clk_hw*[]){
> +			&cam_cc_pll2.clkr.hw,
> +		},
>  		.num_parents = 1,
>  		.ops = &clk_alpha_pll_postdiv_fabia_ops,
>  	},
> @@ -137,7 +133,9 @@ static struct clk_alpha_pll cam_cc_pll3 = {
>  	.clkr = {
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_pll3",
> -			.parent_names = (const char *[]){ "bi_tcxo" },
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "bi_tcxo", .name = "bi_tcxo",
> +			},
>  			.num_parents = 1,
>  			.ops = &clk_alpha_pll_fabia_ops,
>  		},
> @@ -153,12 +151,30 @@ static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
>  	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_pll3_out_even",
> -		.parent_names = (const char *[]){ "cam_cc_pll3" },
> +		.parent_hws = (const struct clk_hw*[]){
> +			&cam_cc_pll3.clkr.hw,
> +		},
>  		.num_parents = 1,
>  		.ops = &clk_alpha_pll_postdiv_fabia_ops,
>  	},
>  };
>  
> +static const struct parent_map cam_cc_parent_map_0[] = {
> +	{ P_BI_TCXO, 0 },
> +	{ P_CAM_CC_PLL2_OUT_EVEN, 1 },
> +	{ P_CAM_CC_PLL1_OUT_EVEN, 2 },
> +	{ P_CAM_CC_PLL3_OUT_EVEN, 5 },
> +	{ P_CAM_CC_PLL0_OUT_EVEN, 6 },
> +};
> +
> +static const struct clk_parent_data cam_cc_parent_data_0[] = {
> +	{ .fw_name = "bi_tcxo", .name = "bi_tcxo" },
> +	{ .hw = &cam_cc_pll2_out_even.clkr.hw },
> +	{ .hw = &cam_cc_pll1_out_even.clkr.hw },
> +	{ .hw = &cam_cc_pll3_out_even.clkr.hw },
> +	{ .hw = &cam_cc_pll0_out_even.clkr.hw },
> +};
> +
>  static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
>  	F(19200000, P_BI_TCXO, 1, 0, 0),
>  	F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
> @@ -186,8 +202,8 @@ static struct clk_rcg2 cam_cc_bps_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_bps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_bps_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),

And this ARRAY_SIZE conversion should probably also be performed in yet
another patch?

>  		.flags = CLK_SET_RATE_PARENT,
>  		.ops = &clk_rcg2_shared_ops,
>  	},
> @@ -209,8 +225,8 @@ static struct clk_rcg2 cam_cc_cci_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_cci_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_cci_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -229,8 +245,8 @@ static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_cphy_rx_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -250,8 +266,8 @@ static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_csi0phytimer_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
>  		.flags = CLK_SET_RATE_PARENT,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -265,8 +281,8 @@ static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_csi1phytimer_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
>  		.flags = CLK_SET_RATE_PARENT,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -280,8 +296,8 @@ static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_csi2phytimer_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
>  		.flags = CLK_SET_RATE_PARENT,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -295,8 +311,8 @@ static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_csi3phytimer_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
>  		.flags = CLK_SET_RATE_PARENT,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -320,8 +336,8 @@ static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_fast_ahb_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -343,8 +359,8 @@ static struct clk_rcg2 cam_cc_fd_core_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_fd_core_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_fd_core_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
>  		.ops = &clk_rcg2_shared_ops,
>  	},
>  };
> @@ -366,8 +382,8 @@ static struct clk_rcg2 cam_cc_icp_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_icp_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_icp_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
>  		.ops = &clk_rcg2_shared_ops,
>  	},
>  };
> @@ -390,8 +406,8 @@ static struct clk_rcg2 cam_cc_ife_0_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_ife_0_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
>  		.flags = CLK_SET_RATE_PARENT,
>  		.ops = &clk_rcg2_shared_ops,
>  	},
> @@ -413,8 +429,8 @@ static struct clk_rcg2 cam_cc_ife_0_csid_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_ife_0_csid_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
>  		.ops = &clk_rcg2_shared_ops,
>  	},
>  };
> @@ -427,8 +443,8 @@ static struct clk_rcg2 cam_cc_ife_1_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_ife_1_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
>  		.flags = CLK_SET_RATE_PARENT,
>  		.ops = &clk_rcg2_shared_ops,
>  	},
> @@ -442,8 +458,8 @@ static struct clk_rcg2 cam_cc_ife_1_csid_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_ife_1_csid_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
>  		.ops = &clk_rcg2_shared_ops,
>  	},
>  };
> @@ -456,8 +472,8 @@ static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_ife_lite_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
>  		.flags = CLK_SET_RATE_PARENT,
>  		.ops = &clk_rcg2_shared_ops,
>  	},
> @@ -471,8 +487,8 @@ static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_ife_0_csid_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_ife_lite_csid_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
>  		.ops = &clk_rcg2_shared_ops,
>  	},
>  };
> @@ -496,8 +512,8 @@ static struct clk_rcg2 cam_cc_ipe_0_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_ipe_0_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
>  		.flags = CLK_SET_RATE_PARENT,
>  		.ops = &clk_rcg2_shared_ops,
>  	},
> @@ -511,8 +527,8 @@ static struct clk_rcg2 cam_cc_ipe_1_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_ipe_0_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_ipe_1_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
>  		.flags = CLK_SET_RATE_PARENT,
>  		.ops = &clk_rcg2_shared_ops,
>  	},
> @@ -526,8 +542,8 @@ static struct clk_rcg2 cam_cc_jpeg_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_bps_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_jpeg_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
>  		.flags = CLK_SET_RATE_PARENT,
>  		.ops = &clk_rcg2_shared_ops,
>  	},
> @@ -551,8 +567,8 @@ static struct clk_rcg2 cam_cc_lrme_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_lrme_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_lrme_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
>  		.flags = CLK_SET_RATE_PARENT,
>  		.ops = &clk_rcg2_shared_ops,
>  	},
> @@ -574,8 +590,8 @@ static struct clk_rcg2 cam_cc_mclk0_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_mclk0_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
>  		.flags = CLK_SET_RATE_PARENT,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -589,8 +605,8 @@ static struct clk_rcg2 cam_cc_mclk1_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_mclk1_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
>  		.flags = CLK_SET_RATE_PARENT,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -604,8 +620,8 @@ static struct clk_rcg2 cam_cc_mclk2_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_mclk2_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
>  		.flags = CLK_SET_RATE_PARENT,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -619,8 +635,8 @@ static struct clk_rcg2 cam_cc_mclk3_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_mclk3_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
>  		.flags = CLK_SET_RATE_PARENT,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -643,8 +659,8 @@ static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
>  	.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "cam_cc_slow_ahb_clk_src",
> -		.parent_names = cam_cc_parent_names_0,
> -		.num_parents = 6,
> +		.parent_data = cam_cc_parent_data_0,
> +		.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
>  		.flags = CLK_SET_RATE_PARENT,
>  		.ops = &clk_rcg2_ops,
>  	},
> @@ -658,8 +674,8 @@ static struct clk_branch cam_cc_bps_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_bps_ahb_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_slow_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_slow_ahb_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -676,8 +692,8 @@ static struct clk_branch cam_cc_bps_areg_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_bps_areg_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_fast_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_fast_ahb_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -707,8 +723,8 @@ static struct clk_branch cam_cc_bps_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_bps_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_bps_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_bps_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -751,8 +767,8 @@ static struct clk_branch cam_cc_cci_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_cci_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_cci_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_cci_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -769,8 +785,8 @@ static struct clk_branch cam_cc_cpas_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_cpas_ahb_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_slow_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_slow_ahb_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -787,8 +803,8 @@ static struct clk_branch cam_cc_csi0phytimer_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_csi0phytimer_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_csi0phytimer_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_csi0phytimer_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -805,8 +821,8 @@ static struct clk_branch cam_cc_csi1phytimer_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_csi1phytimer_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_csi1phytimer_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_csi1phytimer_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -823,8 +839,8 @@ static struct clk_branch cam_cc_csi2phytimer_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_csi2phytimer_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_csi2phytimer_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_csi2phytimer_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -841,8 +857,8 @@ static struct clk_branch cam_cc_csi3phytimer_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_csi3phytimer_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_csi3phytimer_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_csi3phytimer_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -859,8 +875,8 @@ static struct clk_branch cam_cc_csiphy0_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_csiphy0_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_cphy_rx_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_cphy_rx_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -877,8 +893,8 @@ static struct clk_branch cam_cc_csiphy1_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_csiphy1_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_cphy_rx_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_cphy_rx_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -895,8 +911,8 @@ static struct clk_branch cam_cc_csiphy2_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_csiphy2_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_cphy_rx_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_cphy_rx_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -913,8 +929,8 @@ static struct clk_branch cam_cc_csiphy3_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_csiphy3_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_cphy_rx_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_cphy_rx_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -931,8 +947,8 @@ static struct clk_branch cam_cc_fd_core_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_fd_core_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_fd_core_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_fd_core_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -949,8 +965,8 @@ static struct clk_branch cam_cc_fd_core_uar_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_fd_core_uar_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_fd_core_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_fd_core_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -992,8 +1008,8 @@ static struct clk_branch cam_cc_icp_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_icp_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_icp_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_icp_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1049,8 +1065,8 @@ static struct clk_branch cam_cc_ife_0_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ife_0_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_ife_0_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_ife_0_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1067,8 +1083,8 @@ static struct clk_branch cam_cc_ife_0_cphy_rx_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ife_0_cphy_rx_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_cphy_rx_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_cphy_rx_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1085,8 +1101,8 @@ static struct clk_branch cam_cc_ife_0_csid_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ife_0_csid_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_ife_0_csid_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_ife_0_csid_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1103,8 +1119,8 @@ static struct clk_branch cam_cc_ife_0_dsp_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ife_0_dsp_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_ife_0_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_ife_0_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -1133,8 +1149,8 @@ static struct clk_branch cam_cc_ife_1_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ife_1_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_ife_1_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_ife_1_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1151,8 +1167,8 @@ static struct clk_branch cam_cc_ife_1_cphy_rx_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ife_1_cphy_rx_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_cphy_rx_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_cphy_rx_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1169,8 +1185,8 @@ static struct clk_branch cam_cc_ife_1_csid_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ife_1_csid_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_ife_1_csid_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_ife_1_csid_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1187,8 +1203,8 @@ static struct clk_branch cam_cc_ife_1_dsp_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ife_1_dsp_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_ife_1_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_ife_1_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.ops = &clk_branch2_ops,
> @@ -1204,8 +1220,8 @@ static struct clk_branch cam_cc_ife_lite_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ife_lite_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_ife_lite_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_ife_lite_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1222,8 +1238,8 @@ static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ife_lite_cphy_rx_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_cphy_rx_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_cphy_rx_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1240,8 +1256,8 @@ static struct clk_branch cam_cc_ife_lite_csid_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ife_lite_csid_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_ife_lite_csid_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_ife_lite_csid_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1258,8 +1274,8 @@ static struct clk_branch cam_cc_ipe_0_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ipe_0_ahb_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_slow_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_slow_ahb_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1276,8 +1292,8 @@ static struct clk_branch cam_cc_ipe_0_areg_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ipe_0_areg_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_fast_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_fast_ahb_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1307,8 +1323,8 @@ static struct clk_branch cam_cc_ipe_0_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ipe_0_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_ipe_0_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_ipe_0_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1325,8 +1341,8 @@ static struct clk_branch cam_cc_ipe_1_ahb_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ipe_1_ahb_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_slow_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_slow_ahb_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1343,8 +1359,8 @@ static struct clk_branch cam_cc_ipe_1_areg_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ipe_1_areg_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_fast_ahb_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_fast_ahb_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1374,8 +1390,8 @@ static struct clk_branch cam_cc_ipe_1_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_ipe_1_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_ipe_1_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_ipe_1_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1392,8 +1408,8 @@ static struct clk_branch cam_cc_jpeg_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_jpeg_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_jpeg_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_jpeg_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1410,8 +1426,8 @@ static struct clk_branch cam_cc_lrme_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_lrme_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_lrme_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_lrme_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1428,8 +1444,8 @@ static struct clk_branch cam_cc_mclk0_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_mclk0_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_mclk0_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_mclk0_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1446,8 +1462,8 @@ static struct clk_branch cam_cc_mclk1_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_mclk1_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_mclk1_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_mclk1_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1464,8 +1480,8 @@ static struct clk_branch cam_cc_mclk2_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_mclk2_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_mclk2_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_mclk2_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> @@ -1482,8 +1498,8 @@ static struct clk_branch cam_cc_mclk3_clk = {
>  		.enable_mask = BIT(0),
>  		.hw.init = &(struct clk_init_data){
>  			.name = "cam_cc_mclk3_clk",
> -			.parent_names = (const char *[]){
> -				"cam_cc_mclk3_clk_src",
> +			.parent_hws = (const struct clk_hw*[]){
> +				&cam_cc_mclk3_clk_src.clkr.hw,
>  			},
>  			.num_parents = 1,
>  			.flags = CLK_SET_RATE_PARENT,
> -- 
> 2.33.0
> 

Re: [PATCH 08/11] clk: qcom: gcc-msm8996: drop unsupported clock sources

[Marijn Suijten]

On 2021-12-08 20:54:27, Dmitry Baryshkov wrote:
> In preparation of updating the msm8996 gcc driver, drop all unsupported
> GPLL sources (gpll1/gpll1_early_div, gpll2/gpll2_early and gpll3).
> Downstream kernel also does not provide support for these GPLL sources,
> so it is safe to drop them.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  drivers/clk/qcom/gcc-msm8996.c | 55 ++++------------------------------
>  1 file changed, 6 insertions(+), 49 deletions(-)
> 
> diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
> index 9b1674b28d45..3acefe16355c 100644
> --- a/drivers/clk/qcom/gcc-msm8996.c
> +++ b/drivers/clk/qcom/gcc-msm8996.c
> @@ -27,15 +27,10 @@
>  enum {
>  	P_XO,
>  	P_GPLL0,
> -	P_GPLL2,
> -	P_GPLL3,
> -	P_GPLL1,
> -	P_GPLL2_EARLY,
>  	P_GPLL0_EARLY_DIV,
>  	P_SLEEP_CLK,
>  	P_GPLL4,
>  	P_AUD_REF_CLK,
> -	P_GPLL1_EARLY_DIV
>  };
>  
>  static const struct parent_map gcc_sleep_clk_map[] = {
> @@ -130,44 +125,6 @@ static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
>  	"gpll0_early_div"
>  };
>  
> -static const struct parent_map gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map[] = {
> -	{ P_XO, 0 },
> -	{ P_GPLL0, 1 },
> -	{ P_GPLL1_EARLY_DIV, 3 },
> -	{ P_GPLL1, 4 },
> -	{ P_GPLL4, 5 },
> -	{ P_GPLL0_EARLY_DIV, 6 }
> -};
> -
> -static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div[] = {
> -	"xo",
> -	"gpll0",
> -	"gpll1_early_div",
> -	"gpll1",
> -	"gpll4",
> -	"gpll0_early_div"
> -};
> -
> -static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map[] = {
> -	{ P_XO, 0 },
> -	{ P_GPLL0, 1 },
> -	{ P_GPLL2, 2 },
> -	{ P_GPLL3, 3 },
> -	{ P_GPLL1, 4 },
> -	{ P_GPLL2_EARLY, 5 },
> -	{ P_GPLL0_EARLY_DIV, 6 }
> -};
> -
> -static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div[] = {
> -	"xo",
> -	"gpll0",
> -	"gpll2",
> -	"gpll3",
> -	"gpll1",
> -	"gpll2_early",
> -	"gpll0_early_div"
> -};
> -
>  static struct clk_fixed_factor xo = {
>  	.mult = 1,
>  	.div = 1,
> @@ -285,12 +242,12 @@ static const struct freq_tbl ftbl_system_noc_clk_src[] = {
>  static struct clk_rcg2 system_noc_clk_src = {
>  	.cmd_rcgr = 0x0401c,
>  	.hid_width = 5,
> -	.parent_map = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map,
> +	.parent_map = gcc_xo_gpll0_gpll0_early_div_map,
>  	.freq_tbl = ftbl_system_noc_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "system_noc_clk_src",
> -		.parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div,
> -		.num_parents = 7,
> +		.parent_names = gcc_xo_gpll0_gpll0_early_div,
> +		.num_parents = 3,

Is it perhaps preferred to perform the ARRAY_SIZE conversion _before_
this patch, such that num_parents doesn't need to be updated
temporarily?  That said, yes the name would have to be updated in two
places then, but that seems less fragile than the hardcoded numbers we'd
like to avoid.

>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> @@ -1257,12 +1214,12 @@ static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
>  static struct clk_rcg2 qspi_ser_clk_src = {
>  	.cmd_rcgr = 0x8b00c,
>  	.hid_width = 5,
> -	.parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map,
> +	.parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
>  	.freq_tbl = ftbl_qspi_ser_clk_src,
>  	.clkr.hw.init = &(struct clk_init_data){
>  		.name = "qspi_ser_clk_src",
> -		.parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
> -		.num_parents = 6,
> +		.parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
> +		.num_parents = 4,
>  		.ops = &clk_rcg2_ops,
>  	},
>  };
> -- 
> 2.33.0
> 

Re: [PATCH 02/11] clk: qcom: gpucc-sdm660: use parent_hws instead of parent_data

[Stephen Boyd]

Quoting Dmitry Baryshkov (2021-12-08 09:54:21)
> If all parents are specified as clk_hw, we can use parent_hws instead of
> parent_data.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---

Reviewed-by: Stephen Boyd <sboyd@kernel.org>

Re: [PATCH 01/11] clk: qcom: gpucc-sdm660: get rid of the test clock

[Stephen Boyd]

Quoting Dmitry Baryshkov (2021-12-08 09:54:20)
> The test clock isn't in the bindings and apparently it's not used by
> anyone upstream.  Remove it.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---

Reviewed-by: Stephen Boyd <sboyd@kernel.org>

Re: [PATCH 03/11] clk: qcom: camcc-sc7180: get rid of the test clock

[Stephen Boyd]

Quoting Dmitry Baryshkov (2021-12-08 09:54:22)
> The test clock isn't in the bindings and apparently it's not used by
> anyone upstream.  Remove it.
> 
> Suggested-by: Stephen Boyd <swboyd@chromium.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---

Reviewed-by: Stephen Boyd <sboyd@kernel.org>

Re: [PATCH 04/11] clk: qcom: camcc-sdm845: get rid of the test clock

[Stephen Boyd]

Quoting Dmitry Baryshkov (2021-12-08 09:54:23)
> The test clock isn't in the bindings and apparently it's not used by
> anyone upstream.  Remove it.
> 
> Suggested-by: Stephen Boyd <swboyd@chromium.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---

Reviewed-by: Stephen Boyd <sboyd@kernel.org>

Re: [PATCH 06/11] clk: qcom: camcc-sc7180: use parent_hws instead of parent_data

[Stephen Boyd]

Quoting Dmitry Baryshkov (2021-12-08 09:54:25)
> If all parents are specified as clk_hw, we can use parent_hws instead of
> parent_data.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---

Is the code size smaller? Would be nice to add that detail.

Reviewed-by: Stephen Boyd <sboyd@kernel.org>

Re: [PATCH 07/11] clk: qcom: videocc-sc7180: use parent_hws instead of parent_data

[Stephen Boyd]

Quoting Dmitry Baryshkov (2021-12-08 09:54:26)
> If all parents are specified as clk_hw, we can use parent_hws instead of
> parent_data.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---

Reviewed-by: Stephen Boyd <sboyd@kernel.org>

Re: [PATCH 09/11] clk: qcom: gcc-msm8996: move clock parent tables down

[Stephen Boyd]

Quoting Dmitry Baryshkov (2021-12-08 09:54:28)
> Move clock parent tables down, after the GPLL declrataions, so that we
> can use gpll hw clock fields in the next commit.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---

Reviewed-by: Stephen Boyd <sboyd@kernel.org>

Re: [PATCH 11/11] clk: qcom: gcc-msm8996: use ARRAY_SIZE instead of specifying num_parents

[Stephen Boyd]

Quoting Dmitry Baryshkov (2021-12-08 09:54:30)
> Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
> adding/removing entries to/from parent_data easy and errorproof.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---

Reviewed-by: Stephen Boyd <sboyd@kernel.org>

Re: [PATCH 10/11] clk: qcom: gcc-msm8996: use parent_hws/_data instead of parent_names

[Bjorn Andersson]

On Wed 08 Dec 17:09 CST 2021, Marijn Suijten wrote:

> On 2021-12-08 20:54:29, Dmitry Baryshkov wrote:
> > Convert the clock driver to specify parent data rather than parent
> > names, to actually bind using 'clock-names' specified in the DTS rather
> > than global clock names. Use parent_hws where possible to refer parent
> > clocks directly, skipping the lookup.
> > 
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> >  drivers/clk/qcom/gcc-msm8996.c | 678 ++++++++++++++++++++++-----------
> >  1 file changed, 463 insertions(+), 215 deletions(-)
> > 
> > diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
> > index c2f9ae729d1e..186e682e730f 100644
> > --- a/drivers/clk/qcom/gcc-msm8996.c
> > +++ b/drivers/clk/qcom/gcc-msm8996.c
> > @@ -38,7 +38,9 @@ static struct clk_fixed_factor xo = {
> >  	.div = 1,
> >  	.hw.init = &(struct clk_init_data){
> >  		.name = "xo",
> > -		.parent_names = (const char *[]){ "xo_board" },
> > +		.parent_data = &(const struct clk_parent_data){
> > +			.fw_name = "cxo", .name = "xo_board",
> 
> I assume you'll submit DT changes later to provide this cxo clock in the
> DT?  msm8996.dtsi currently only seems to provide a cxo2 clock.
> 
> > +		},
> >  		.num_parents = 1,
> >  		.ops = &clk_fixed_factor_ops,
> >  	},
> > @@ -52,7 +54,9 @@ static struct clk_alpha_pll gpll0_early = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gpll0_early",
> > -			.parent_names = (const char *[]){ "xo" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&xo.hw,
> 
> I always view this local "xo" clock as a "hack" to provide an "xo" clock
> in the global namespace for drivers and older DTs that don't use clocks=
> and clock-names= yet.  Since it's an alias for xo_board, it is perhaps
> better to repeat `.fw_name = "cxo", .name = "xo_board"` here?
> 

As mentioned elsewhere, xo_board is the oscillator feeding the PMIC,
while cxo is the input xo on the SoC, which is connected to an output
from the PMIC - controlled through rpmh's RPM_SMD_BB_CLK1.

So the separation is correct, but you're totally right that the local xo
is a hack from a time when we couldn't make rpmhcc the root of all
clocks.

Regards,
Bjorn

> Otherwise we might want to swap all those over to `&xo.hw` instead.
> 
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_alpha_pll_ops,
> >  		},
> > @@ -64,7 +68,9 @@ static struct clk_fixed_factor gpll0_early_div = {
> >  	.div = 2,
> >  	.hw.init = &(struct clk_init_data){
> >  		.name = "gpll0_early_div",
> > -		.parent_names = (const char *[]){ "gpll0_early" },
> > +		.parent_hws = (const struct clk_hw*[]){
> > +			&gpll0_early.clkr.hw,
> > +		},
> >  		.num_parents = 1,
> >  		.ops = &clk_fixed_factor_ops,
> >  	},
> > @@ -75,7 +81,9 @@ static struct clk_alpha_pll_postdiv gpll0 = {
> >  	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "gpll0",
> > -		.parent_names = (const char *[]){ "gpll0_early" },
> > +		.parent_hws = (const struct clk_hw*[]){
> > +			&gpll0_early.clkr.hw,
> > +		},
> >  		.num_parents = 1,
> >  		.ops = &clk_alpha_pll_postdiv_ops,
> >  	},
> > @@ -88,7 +96,9 @@ static struct clk_branch gcc_mmss_gpll0_div_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_mmss_gpll0_div_clk",
> > -			.parent_names = (const char *[]){ "gpll0" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&gpll0.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -103,7 +113,9 @@ static struct clk_branch gcc_mss_gpll0_div_clk = {
> >  		.enable_mask = BIT(2),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_mss_gpll0_div_clk",
> > -			.parent_names = (const char *[]){ "gpll0" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&gpll0.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops
> > @@ -119,7 +131,9 @@ static struct clk_alpha_pll gpll4_early = {
> >  		.enable_mask = BIT(4),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gpll4_early",
> > -			.parent_names = (const char *[]){ "xo" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&xo.hw,
> 
> Same question here, and all the other conversions for "xo".
> 
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_alpha_pll_ops,
> >  		},
> > @@ -131,7 +145,9 @@ static struct clk_alpha_pll_postdiv gpll4 = {
> >  	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "gpll4",
> > -		.parent_names = (const char *[]){ "gpll4_early" },
> > +		.parent_hws = (const struct clk_hw*[]){
> > +			&gpll4_early.clkr.hw,
> > +		},
> >  		.num_parents = 1,
> >  		.ops = &clk_alpha_pll_postdiv_ops,
> >  	},
> > @@ -141,8 +157,8 @@ static const struct parent_map gcc_sleep_clk_map[] = {
> >  	{ P_SLEEP_CLK, 5 }
> >  };
> >  
> > -static const char * const gcc_sleep_clk[] = {
> > -	"sleep_clk"
> > +static const struct clk_parent_data gcc_sleep_clk[] = {
> > +	{ .fw_name = "sleep_clk", .name = "sleep_clk" }
> 
> This should also be added to the DT.
> 
> >  };
> >  
> >  static const struct parent_map gcc_xo_gpll0_map[] = {
> > @@ -150,9 +166,9 @@ static const struct parent_map gcc_xo_gpll0_map[] = {
> >  	{ P_GPLL0, 1 }
> >  };
> >  
> > -static const char * const gcc_xo_gpll0[] = {
> > -	"xo",
> > -	"gpll0"
> > +static const struct clk_parent_data gcc_xo_gpll0[] = {
> > +	{ .hw = &xo.hw },
> > +	{ .hw = &gpll0.clkr.hw }
> >  };
> >  
> >  static const struct parent_map gcc_xo_sleep_clk_map[] = {
> > @@ -160,9 +176,9 @@ static const struct parent_map gcc_xo_sleep_clk_map[] = {
> >  	{ P_SLEEP_CLK, 5 }
> >  };
> >  
> > -static const char * const gcc_xo_sleep_clk[] = {
> > -	"xo",
> > -	"sleep_clk"
> > +static const struct clk_parent_data gcc_xo_sleep_clk[] = {
> > +	{ .hw = &xo.hw },
> > +	{ .fw_name = "sleep_clk", .name = "sleep_clk" }
> >  };
> >  
> >  static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
> > @@ -171,10 +187,10 @@ static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
> >  	{ P_GPLL0_EARLY_DIV, 6 }
> >  };
> >  
> > -static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
> > -	"xo",
> > -	"gpll0",
> > -	"gpll0_early_div"
> > +static const struct clk_parent_data gcc_xo_gpll0_gpll0_early_div[] = {
> > +	{ .hw = &xo.hw },
> > +	{ .hw = &gpll0.clkr.hw },
> > +	{ .hw = &gpll0_early_div.hw }
> >  };
> >  
> >  static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
> > @@ -183,10 +199,10 @@ static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
> >  	{ P_GPLL4, 5 }
> >  };
> >  
> > -static const char * const gcc_xo_gpll0_gpll4[] = {
> > -	"xo",
> > -	"gpll0",
> > -	"gpll4"
> > +static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
> > +	{ .hw = &xo.hw },
> > +	{ .hw = &gpll0.clkr.hw },
> > +	{ .hw = &gpll4.clkr.hw }
> >  };
> >  
> >  static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
> > @@ -195,10 +211,10 @@ static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
> >  	{ P_AUD_REF_CLK, 2 }
> >  };
> >  
> > -static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
> > -	"xo",
> > -	"gpll0",
> > -	"aud_ref_clk"
> > +static const struct clk_parent_data gcc_xo_gpll0_aud_ref_clk[] = {
> > +	{ .hw = &xo.hw },
> > +	{ .hw = &gpll0.clkr.hw },
> > +	{ .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }
> 
> Don't forget to add this clock to the DT-bindings.
> 
> >  };
> >  
> >  static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
> > @@ -208,11 +224,11 @@ static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
> >  	{ P_GPLL0_EARLY_DIV, 6 }
> >  };
> >  
> > -static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
> > -	"xo",
> > -	"gpll0",
> > -	"sleep_clk",
> > -	"gpll0_early_div"
> > +static const struct clk_parent_data gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
> > +	{ .hw = &xo.hw },
> > +	{ .hw = &gpll0.clkr.hw },
> > +	{ .fw_name = "sleep_clk", .name = "sleep_clk" },
> > +	{ .hw = &gpll0_early_div.hw }
> >  };
> >  
> >  static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
> > @@ -222,11 +238,11 @@ static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
> >  	{ P_GPLL0_EARLY_DIV, 6 }
> >  };
> >  
> > -static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
> > -	"xo",
> > -	"gpll0",
> > -	"gpll4",
> > -	"gpll0_early_div"
> > +static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
> > +	{ .hw = &xo.hw },
> > +	{ .hw = &gpll0.clkr.hw },
> > +	{ .hw = &gpll4.clkr.hw },
> > +	{ .hw = &gpll0_early_div.hw }
> >  };
> >  
> >  static const struct freq_tbl ftbl_system_noc_clk_src[] = {
> > @@ -246,7 +262,7 @@ static struct clk_rcg2 system_noc_clk_src = {
> >  	.freq_tbl = ftbl_system_noc_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "system_noc_clk_src",
> > -		.parent_names = gcc_xo_gpll0_gpll0_early_div,
> > +		.parent_data = gcc_xo_gpll0_gpll0_early_div,
> >  		.num_parents = 3,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -266,7 +282,7 @@ static struct clk_rcg2 config_noc_clk_src = {
> >  	.freq_tbl = ftbl_config_noc_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "config_noc_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -288,7 +304,7 @@ static struct clk_rcg2 periph_noc_clk_src = {
> >  	.freq_tbl = ftbl_periph_noc_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "periph_noc_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -309,7 +325,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
> >  	.freq_tbl = ftbl_usb30_master_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "usb30_master_clk_src",
> > -		.parent_names = gcc_xo_gpll0_gpll0_early_div,
> > +		.parent_data = gcc_xo_gpll0_gpll0_early_div,
> >  		.num_parents = 3,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -327,7 +343,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
> >  	.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "usb30_mock_utmi_clk_src",
> > -		.parent_names = gcc_xo_gpll0_gpll0_early_div,
> > +		.parent_data = gcc_xo_gpll0_gpll0_early_div,
> >  		.num_parents = 3,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -345,7 +361,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = {
> >  	.freq_tbl = ftbl_usb3_phy_aux_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "usb3_phy_aux_clk_src",
> > -		.parent_names = gcc_xo_sleep_clk,
> > +		.parent_data = gcc_xo_sleep_clk,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -364,7 +380,7 @@ static struct clk_rcg2 usb20_master_clk_src = {
> >  	.freq_tbl = ftbl_usb20_master_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "usb20_master_clk_src",
> > -		.parent_names = gcc_xo_gpll0_gpll0_early_div,
> > +		.parent_data = gcc_xo_gpll0_gpll0_early_div,
> >  		.num_parents = 3,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -377,7 +393,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = {
> >  	.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "usb20_mock_utmi_clk_src",
> > -		.parent_names = gcc_xo_gpll0_gpll0_early_div,
> > +		.parent_data = gcc_xo_gpll0_gpll0_early_div,
> >  		.num_parents = 3,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -403,7 +419,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
> >  	.freq_tbl = ftbl_sdcc1_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "sdcc1_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
> > +		.parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
> >  		.num_parents = 4,
> >  		.ops = &clk_rcg2_floor_ops,
> >  	},
> > @@ -423,7 +439,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = {
> >  	.freq_tbl = ftbl_sdcc1_ice_core_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "sdcc1_ice_core_clk_src",
> > -		.parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
> > +		.parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
> >  		.num_parents = 4,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -448,7 +464,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
> >  	.freq_tbl = ftbl_sdcc2_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "sdcc2_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0_gpll4,
> > +		.parent_data = gcc_xo_gpll0_gpll4,
> >  		.num_parents = 3,
> >  		.ops = &clk_rcg2_floor_ops,
> >  	},
> > @@ -462,7 +478,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
> >  	.freq_tbl = ftbl_sdcc2_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "sdcc3_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0_gpll4,
> > +		.parent_data = gcc_xo_gpll0_gpll4,
> >  		.num_parents = 3,
> >  		.ops = &clk_rcg2_floor_ops,
> >  	},
> > @@ -486,7 +502,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
> >  	.freq_tbl = ftbl_sdcc4_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "sdcc4_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_floor_ops,
> >  	},
> > @@ -511,7 +527,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp1_qup1_spi_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -530,7 +546,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp1_qup1_i2c_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -563,7 +579,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp1_uart1_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -577,7 +593,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp1_qup2_spi_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -590,7 +606,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp1_qup2_i2c_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -604,7 +620,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp1_uart2_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -618,7 +634,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp1_qup3_spi_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -631,7 +647,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp1_qup3_i2c_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -645,7 +661,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp1_uart3_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -659,7 +675,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp1_qup4_spi_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -672,7 +688,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp1_qup4_i2c_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -686,7 +702,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp1_uart4_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -700,7 +716,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp1_qup5_spi_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -713,7 +729,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp1_qup5_i2c_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -727,7 +743,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp1_uart5_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -741,7 +757,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp1_qup6_spi_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -754,7 +770,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp1_qup6_i2c_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -768,7 +784,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp1_uart6_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -782,7 +798,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp2_qup1_spi_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -795,7 +811,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp2_qup1_i2c_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -809,7 +825,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp2_uart1_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -823,7 +839,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp2_qup2_spi_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -836,7 +852,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp2_qup2_i2c_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -850,7 +866,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp2_uart2_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -864,7 +880,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp2_qup3_spi_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -877,7 +893,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp2_qup3_i2c_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -891,7 +907,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp2_uart3_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -905,7 +921,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp2_qup4_spi_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -918,7 +934,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp2_qup4_i2c_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -932,7 +948,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp2_uart4_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -946,7 +962,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp2_qup5_spi_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -959,7 +975,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp2_qup5_i2c_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -973,7 +989,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp2_uart5_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -987,7 +1003,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp2_qup6_spi_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -1000,7 +1016,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp2_qup6_i2c_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -1014,7 +1030,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
> >  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "blsp2_uart6_apps_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -1032,7 +1048,7 @@ static struct clk_rcg2 pdm2_clk_src = {
> >  	.freq_tbl = ftbl_pdm2_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "pdm2_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -1051,7 +1067,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
> >  	.freq_tbl = ftbl_tsif_ref_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "tsif_ref_clk_src",
> > -		.parent_names = gcc_xo_gpll0_aud_ref_clk,
> > +		.parent_data = gcc_xo_gpll0_aud_ref_clk,
> >  		.num_parents = 3,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -1063,7 +1079,7 @@ static struct clk_rcg2 gcc_sleep_clk_src = {
> >  	.parent_map = gcc_sleep_clk_map,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "gcc_sleep_clk_src",
> > -		.parent_names = gcc_sleep_clk,
> > +		.parent_data = gcc_sleep_clk,
> >  		.num_parents = 1,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -1076,7 +1092,7 @@ static struct clk_rcg2 hmss_rbcpr_clk_src = {
> >  	.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "hmss_rbcpr_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -1088,7 +1104,7 @@ static struct clk_rcg2 hmss_gpll0_clk_src = {
> >  	.parent_map = gcc_xo_gpll0_map,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "hmss_gpll0_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -1109,7 +1125,7 @@ static struct clk_rcg2 gp1_clk_src = {
> >  	.freq_tbl = ftbl_gp1_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "gp1_clk_src",
> > -		.parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
> > +		.parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
> >  		.num_parents = 4,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -1123,7 +1139,7 @@ static struct clk_rcg2 gp2_clk_src = {
> >  	.freq_tbl = ftbl_gp1_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "gp2_clk_src",
> > -		.parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
> > +		.parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
> >  		.num_parents = 4,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -1137,7 +1153,7 @@ static struct clk_rcg2 gp3_clk_src = {
> >  	.freq_tbl = ftbl_gp1_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "gp3_clk_src",
> > -		.parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
> > +		.parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
> >  		.num_parents = 4,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -1156,7 +1172,7 @@ static struct clk_rcg2 pcie_aux_clk_src = {
> >  	.freq_tbl = ftbl_pcie_aux_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "pcie_aux_clk_src",
> > -		.parent_names = gcc_xo_sleep_clk,
> > +		.parent_data = gcc_xo_sleep_clk,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -1177,7 +1193,7 @@ static struct clk_rcg2 ufs_axi_clk_src = {
> >  	.freq_tbl = ftbl_ufs_axi_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "ufs_axi_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -1197,7 +1213,7 @@ static struct clk_rcg2 ufs_ice_core_clk_src = {
> >  	.freq_tbl = ftbl_ufs_ice_core_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "ufs_ice_core_clk_src",
> > -		.parent_names = gcc_xo_gpll0,
> > +		.parent_data = gcc_xo_gpll0,
> >  		.num_parents = 2,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -1218,7 +1234,7 @@ static struct clk_rcg2 qspi_ser_clk_src = {
> >  	.freq_tbl = ftbl_qspi_ser_clk_src,
> >  	.clkr.hw.init = &(struct clk_init_data){
> >  		.name = "qspi_ser_clk_src",
> > -		.parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
> > +		.parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
> >  		.num_parents = 4,
> >  		.ops = &clk_rcg2_ops,
> >  	},
> > @@ -1231,7 +1247,9 @@ static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_sys_noc_usb3_axi_clk",
> > -			.parent_names = (const char *[]){ "usb30_master_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&usb30_master_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1246,7 +1264,9 @@ static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_sys_noc_ufs_axi_clk",
> > -			.parent_names = (const char *[]){ "ufs_axi_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&ufs_axi_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1261,7 +1281,9 @@ static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_periph_noc_usb20_ahb_clk",
> > -			.parent_names = (const char *[]){ "usb20_master_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&usb20_master_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1276,7 +1298,9 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_mmss_noc_cfg_ahb_clk",
> > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&config_noc_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> >  			.ops = &clk_branch2_ops,
> > @@ -1304,7 +1328,9 @@ static struct clk_branch gcc_usb30_master_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_usb30_master_clk",
> > -			.parent_names = (const char *[]){ "usb30_master_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&usb30_master_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1319,7 +1345,9 @@ static struct clk_branch gcc_usb30_sleep_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_usb30_sleep_clk",
> > -			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&gcc_sleep_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1334,7 +1362,9 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_usb30_mock_utmi_clk",
> > -			.parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&usb30_mock_utmi_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1349,7 +1379,9 @@ static struct clk_branch gcc_usb3_phy_aux_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_usb3_phy_aux_clk",
> > -			.parent_names = (const char *[]){ "usb3_phy_aux_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&usb3_phy_aux_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1365,7 +1397,9 @@ static struct clk_branch gcc_usb3_phy_pipe_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_usb3_phy_pipe_clk",
> > -			.parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.fw_name = "usb3_phy_pipe_clk_src", .name = "usb3_phy_pipe_clk_src",
> 
> Don't forget to add this clock to the DT-bindings.
> 
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1380,7 +1414,9 @@ static struct clk_branch gcc_usb20_master_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_usb20_master_clk",
> > -			.parent_names = (const char *[]){ "usb20_master_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&usb20_master_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1395,7 +1431,9 @@ static struct clk_branch gcc_usb20_sleep_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_usb20_sleep_clk",
> > -			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&gcc_sleep_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1410,7 +1448,9 @@ static struct clk_branch gcc_usb20_mock_utmi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_usb20_mock_utmi_clk",
> > -			.parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&usb20_mock_utmi_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1425,7 +1465,9 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_usb_phy_cfg_ahb2phy_clk",
> > -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> 
> Don't forget to add this clock to the DT-bindings.
> 
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1440,7 +1482,9 @@ static struct clk_branch gcc_sdcc1_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_sdcc1_apps_clk",
> > -			.parent_names = (const char *[]){ "sdcc1_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&sdcc1_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1455,7 +1499,9 @@ static struct clk_branch gcc_sdcc1_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_sdcc1_ahb_clk",
> > -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1470,7 +1516,9 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_sdcc1_ice_core_clk",
> > -			.parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&sdcc1_ice_core_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1485,7 +1533,9 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_sdcc2_apps_clk",
> > -			.parent_names = (const char *[]){ "sdcc2_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&sdcc2_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1500,7 +1550,9 @@ static struct clk_branch gcc_sdcc2_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_sdcc2_ahb_clk",
> > -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1515,7 +1567,9 @@ static struct clk_branch gcc_sdcc3_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_sdcc3_apps_clk",
> > -			.parent_names = (const char *[]){ "sdcc3_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&sdcc3_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1530,7 +1584,9 @@ static struct clk_branch gcc_sdcc3_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_sdcc3_ahb_clk",
> > -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1545,7 +1601,9 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_sdcc4_apps_clk",
> > -			.parent_names = (const char *[]){ "sdcc4_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&sdcc4_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1560,7 +1618,9 @@ static struct clk_branch gcc_sdcc4_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_sdcc4_ahb_clk",
> > -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1576,7 +1636,9 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
> >  		.enable_mask = BIT(17),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp1_ahb_clk",
> > -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1592,7 +1654,9 @@ static struct clk_branch gcc_blsp1_sleep_clk = {
> >  		.enable_mask = BIT(16),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp1_sleep_clk",
> > -			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&gcc_sleep_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1607,7 +1671,9 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp1_qup1_spi_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp1_qup1_spi_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1622,7 +1688,9 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp1_qup1_i2c_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1637,7 +1705,9 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp1_uart1_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp1_uart1_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1652,7 +1722,9 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp1_qup2_spi_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp1_qup2_spi_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1667,7 +1739,9 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp1_qup2_i2c_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1682,7 +1756,9 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp1_uart2_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp1_uart2_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1697,7 +1773,9 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp1_qup3_spi_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp1_qup3_spi_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1712,7 +1790,9 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp1_qup3_i2c_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1727,7 +1807,9 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp1_uart3_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp1_uart3_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1742,7 +1824,9 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp1_qup4_spi_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp1_qup4_spi_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1757,7 +1841,9 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp1_qup4_i2c_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp1_qup4_i2c_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1772,7 +1858,9 @@ static struct clk_branch gcc_blsp1_uart4_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp1_uart4_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp1_uart4_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1787,7 +1875,9 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp1_qup5_spi_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp1_qup5_spi_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1802,7 +1892,9 @@ static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp1_qup5_i2c_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp1_qup5_i2c_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1817,7 +1909,9 @@ static struct clk_branch gcc_blsp1_uart5_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp1_uart5_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp1_uart5_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1832,7 +1926,9 @@ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp1_qup6_spi_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp1_qup6_spi_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1847,7 +1943,9 @@ static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp1_qup6_i2c_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp1_qup6_i2c_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1862,7 +1960,9 @@ static struct clk_branch gcc_blsp1_uart6_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp1_uart6_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp1_uart6_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1878,7 +1978,9 @@ static struct clk_branch gcc_blsp2_ahb_clk = {
> >  		.enable_mask = BIT(15),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp2_ahb_clk",
> > -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1894,7 +1996,9 @@ static struct clk_branch gcc_blsp2_sleep_clk = {
> >  		.enable_mask = BIT(14),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp2_sleep_clk",
> > -			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&gcc_sleep_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1909,7 +2013,9 @@ static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp2_qup1_spi_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp2_qup1_spi_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1924,7 +2030,9 @@ static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp2_qup1_i2c_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp2_qup1_i2c_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1939,7 +2047,9 @@ static struct clk_branch gcc_blsp2_uart1_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp2_uart1_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp2_uart1_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1954,7 +2064,9 @@ static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp2_qup2_spi_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp2_qup2_spi_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1969,7 +2081,9 @@ static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp2_qup2_i2c_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp2_qup2_i2c_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1984,7 +2098,9 @@ static struct clk_branch gcc_blsp2_uart2_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp2_uart2_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp2_uart2_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -1999,7 +2115,9 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp2_qup3_spi_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp2_qup3_spi_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2014,7 +2132,9 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp2_qup3_i2c_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp2_qup3_i2c_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2029,7 +2149,9 @@ static struct clk_branch gcc_blsp2_uart3_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp2_uart3_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp2_uart3_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2044,7 +2166,9 @@ static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp2_qup4_spi_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp2_qup4_spi_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2059,7 +2183,9 @@ static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp2_qup4_i2c_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp2_qup4_i2c_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2074,7 +2200,9 @@ static struct clk_branch gcc_blsp2_uart4_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp2_uart4_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp2_uart4_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2089,7 +2217,9 @@ static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp2_qup5_spi_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp2_qup5_spi_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2104,7 +2234,9 @@ static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp2_qup5_i2c_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp2_qup5_i2c_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2119,7 +2251,9 @@ static struct clk_branch gcc_blsp2_uart5_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp2_uart5_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp2_uart5_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2134,7 +2268,9 @@ static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp2_qup6_spi_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp2_qup6_spi_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2149,7 +2285,9 @@ static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp2_qup6_i2c_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp2_qup6_i2c_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2164,7 +2302,9 @@ static struct clk_branch gcc_blsp2_uart6_apps_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_blsp2_uart6_apps_clk",
> > -			.parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&blsp2_uart6_apps_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2179,7 +2319,9 @@ static struct clk_branch gcc_pdm_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_pdm_ahb_clk",
> > -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2194,7 +2336,9 @@ static struct clk_branch gcc_pdm2_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_pdm2_clk",
> > -			.parent_names = (const char *[]){ "pdm2_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&pdm2_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2210,7 +2354,9 @@ static struct clk_branch gcc_prng_ahb_clk = {
> >  		.enable_mask = BIT(13),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_prng_ahb_clk",
> > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&config_noc_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2225,7 +2371,9 @@ static struct clk_branch gcc_tsif_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_tsif_ahb_clk",
> > -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2240,7 +2388,9 @@ static struct clk_branch gcc_tsif_ref_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_tsif_ref_clk",
> > -			.parent_names = (const char *[]){ "tsif_ref_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&tsif_ref_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2255,7 +2405,9 @@ static struct clk_branch gcc_tsif_inactivity_timers_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_tsif_inactivity_timers_clk",
> > -			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&gcc_sleep_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2271,7 +2423,9 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
> >  		.enable_mask = BIT(10),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_boot_rom_ahb_clk",
> > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&config_noc_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2299,7 +2453,9 @@ static struct clk_branch gcc_hmss_rbcpr_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_hmss_rbcpr_clk",
> > -			.parent_names = (const char *[]){ "hmss_rbcpr_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&hmss_rbcpr_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2314,7 +2470,9 @@ static struct clk_branch gcc_gp1_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_gp1_clk",
> > -			.parent_names = (const char *[]){ "gp1_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&gp1_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2329,7 +2487,9 @@ static struct clk_branch gcc_gp2_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_gp2_clk",
> > -			.parent_names = (const char *[]){ "gp2_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&gp2_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2344,7 +2504,9 @@ static struct clk_branch gcc_gp3_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_gp3_clk",
> > -			.parent_names = (const char *[]){ "gp3_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&gp3_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2359,7 +2521,9 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_pcie_0_slv_axi_clk",
> > -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&system_noc_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2374,7 +2538,9 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_pcie_0_mstr_axi_clk",
> > -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&system_noc_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2389,7 +2555,9 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_pcie_0_cfg_ahb_clk",
> > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&config_noc_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2404,7 +2572,9 @@ static struct clk_branch gcc_pcie_0_aux_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_pcie_0_aux_clk",
> > -			.parent_names = (const char *[]){ "pcie_aux_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&pcie_aux_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2420,7 +2590,9 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_pcie_0_pipe_clk",
> > -			.parent_names = (const char *[]){ "pcie_0_pipe_clk_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.fw_name = "pcie_0_pipe_clk_src", .name = "pcie_0_pipe_clk_src",
> 
> Don't forget to add this clock to the DT-bindings.
> 
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2435,7 +2607,9 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_pcie_1_slv_axi_clk",
> > -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&system_noc_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2450,7 +2624,9 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_pcie_1_mstr_axi_clk",
> > -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&system_noc_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2465,7 +2641,9 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_pcie_1_cfg_ahb_clk",
> > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&config_noc_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2480,7 +2658,9 @@ static struct clk_branch gcc_pcie_1_aux_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_pcie_1_aux_clk",
> > -			.parent_names = (const char *[]){ "pcie_aux_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&pcie_aux_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2496,7 +2676,9 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_pcie_1_pipe_clk",
> > -			.parent_names = (const char *[]){ "pcie_1_pipe_clk_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.fw_name = "pcie_1_pipe_clk_src", .name = "pcie_1_pipe_clk_src",
> 
> Don't forget to add this clock to the DT-bindings.
> 
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2511,7 +2693,9 @@ static struct clk_branch gcc_pcie_2_slv_axi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_pcie_2_slv_axi_clk",
> > -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&system_noc_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2526,7 +2710,9 @@ static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_pcie_2_mstr_axi_clk",
> > -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&system_noc_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2541,7 +2727,9 @@ static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_pcie_2_cfg_ahb_clk",
> > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&config_noc_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2556,7 +2744,9 @@ static struct clk_branch gcc_pcie_2_aux_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_pcie_2_aux_clk",
> > -			.parent_names = (const char *[]){ "pcie_aux_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&pcie_aux_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2572,7 +2762,9 @@ static struct clk_branch gcc_pcie_2_pipe_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_pcie_2_pipe_clk",
> > -			.parent_names = (const char *[]){ "pcie_2_pipe_clk_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.fw_name = "pcie_2_pipe_clk_src", .name = "pcie_2_pipe_clk_src",
> 
> Don't forget to add this clock to the DT-bindings.
> 
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2587,7 +2779,9 @@ static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_pcie_phy_cfg_ahb_clk",
> > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&config_noc_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2602,7 +2796,9 @@ static struct clk_branch gcc_pcie_phy_aux_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_pcie_phy_aux_clk",
> > -			.parent_names = (const char *[]){ "pcie_aux_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&pcie_aux_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2617,7 +2813,9 @@ static struct clk_branch gcc_ufs_axi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_ufs_axi_clk",
> > -			.parent_names = (const char *[]){ "ufs_axi_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&ufs_axi_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2632,7 +2830,9 @@ static struct clk_branch gcc_ufs_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_ufs_ahb_clk",
> > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&config_noc_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2645,7 +2845,9 @@ static struct clk_fixed_factor ufs_tx_cfg_clk_src = {
> >  	.div = 16,
> >  	.hw.init = &(struct clk_init_data){
> >  		.name = "ufs_tx_cfg_clk_src",
> > -		.parent_names = (const char *[]){ "ufs_axi_clk_src" },
> > +		.parent_hws = (const struct clk_hw*[]){
> > +			&ufs_axi_clk_src.clkr.hw,
> > +		},
> >  		.num_parents = 1,
> >  		.flags = CLK_SET_RATE_PARENT,
> >  		.ops = &clk_fixed_factor_ops,
> > @@ -2659,7 +2861,9 @@ static struct clk_branch gcc_ufs_tx_cfg_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_ufs_tx_cfg_clk",
> > -			.parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&ufs_tx_cfg_clk_src.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2672,7 +2876,9 @@ static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
> >  	.div = 16,
> >  	.hw.init = &(struct clk_init_data){
> >  		.name = "ufs_rx_cfg_clk_src",
> > -		.parent_names = (const char *[]){ "ufs_axi_clk_src" },
> > +		.parent_hws = (const struct clk_hw*[]){
> > +			&ufs_axi_clk_src.clkr.hw,
> > +		},
> >  		.num_parents = 1,
> >  		.flags = CLK_SET_RATE_PARENT,
> >  		.ops = &clk_fixed_factor_ops,
> > @@ -2712,7 +2918,9 @@ static struct clk_branch gcc_ufs_rx_cfg_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_ufs_rx_cfg_clk",
> > -			.parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&ufs_rx_cfg_clk_src.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2728,7 +2936,9 @@ static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_ufs_tx_symbol_0_clk",
> > -			.parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.fw_name = "ufs_tx_symbol_0_clk_src", .name = "ufs_tx_symbol_0_clk_src",
> 
> Don't forget to add this clock to the DT-bindings.
> 
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2744,7 +2954,9 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_ufs_rx_symbol_0_clk",
> > -			.parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.fw_name = "ufs_rx_symbol_0_clk_src", .name = "ufs_rx_symbol_0_clk_src",
> 
> Don't forget to add this clock to the DT-bindings.
> 
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2760,7 +2972,9 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_ufs_rx_symbol_1_clk",
> > -			.parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.fw_name = "ufs_rx_symbol_1_clk_src", .name = "ufs_rx_symbol_1_clk_src",
> 
> Don't forget to add this clock to the DT-bindings.
> 
> - Marijn
> 
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2773,7 +2987,9 @@ static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {
> >  	.div = 2,
> >  	.hw.init = &(struct clk_init_data){
> >  		.name = "ufs_ice_core_postdiv_clk_src",
> > -		.parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
> > +		.parent_hws = (const struct clk_hw*[]){
> > +			&ufs_ice_core_clk_src.clkr.hw,
> > +		},
> >  		.num_parents = 1,
> >  		.flags = CLK_SET_RATE_PARENT,
> >  		.ops = &clk_fixed_factor_ops,
> > @@ -2787,7 +3003,9 @@ static struct clk_branch gcc_ufs_unipro_core_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_ufs_unipro_core_clk",
> > -			.parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&ufs_ice_core_postdiv_clk_src.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2802,7 +3020,9 @@ static struct clk_branch gcc_ufs_ice_core_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_ufs_ice_core_clk",
> > -			.parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&ufs_ice_core_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2841,7 +3061,9 @@ static struct clk_branch gcc_aggre0_snoc_axi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_aggre0_snoc_axi_clk",
> > -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&system_noc_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> >  			.ops = &clk_branch2_ops,
> > @@ -2856,7 +3078,9 @@ static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_aggre0_cnoc_ahb_clk",
> > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&config_noc_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> >  			.ops = &clk_branch2_ops,
> > @@ -2871,7 +3095,9 @@ static struct clk_branch gcc_smmu_aggre0_axi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_smmu_aggre0_axi_clk",
> > -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&system_noc_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> >  			.ops = &clk_branch2_ops,
> > @@ -2886,7 +3112,9 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_smmu_aggre0_ahb_clk",
> > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&config_noc_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> >  			.ops = &clk_branch2_ops,
> > @@ -2901,7 +3129,9 @@ static struct clk_branch gcc_aggre2_ufs_axi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_aggre2_ufs_axi_clk",
> > -			.parent_names = (const char *[]){ "ufs_axi_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&ufs_axi_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2916,7 +3146,9 @@ static struct clk_branch gcc_aggre2_usb3_axi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_aggre2_usb3_axi_clk",
> > -			.parent_names = (const char *[]){ "usb30_master_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&usb30_master_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2931,7 +3163,9 @@ static struct clk_branch gcc_dcc_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_dcc_ahb_clk",
> > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&config_noc_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> >  		},
> > @@ -2945,7 +3179,9 @@ static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",
> > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&config_noc_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> >  		},
> > @@ -2959,7 +3195,9 @@ static struct clk_branch gcc_qspi_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_qspi_ahb_clk",
> > -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> > +			.parent_data = &(const struct clk_parent_data){
> > +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -2974,7 +3212,9 @@ static struct clk_branch gcc_qspi_ser_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_qspi_ser_clk",
> > -			.parent_names = (const char *[]){ "qspi_ser_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&qspi_ser_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.flags = CLK_SET_RATE_PARENT,
> >  			.ops = &clk_branch2_ops,
> > @@ -3108,7 +3348,9 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_mss_cfg_ahb_clk",
> > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&config_noc_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> >  		},
> > @@ -3122,7 +3364,9 @@ static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_mss_mnoc_bimc_axi_clk",
> > -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&system_noc_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> >  		},
> > @@ -3136,7 +3380,9 @@ static struct clk_branch gcc_mss_snoc_axi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_mss_snoc_axi_clk",
> > -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&system_noc_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> >  		},
> > @@ -3150,7 +3396,9 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
> >  		.enable_mask = BIT(0),
> >  		.hw.init = &(struct clk_init_data){
> >  			.name = "gcc_mss_q6_bimc_axi_clk",
> > -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> > +			.parent_hws = (const struct clk_hw*[]){
> > +				&system_noc_clk_src.clkr.hw,
> > +			},
> >  			.num_parents = 1,
> >  			.ops = &clk_branch2_ops,
> >  		},
> > -- 
> > 2.33.0
> > 

Re: [PATCH 10/11] clk: qcom: gcc-msm8996: use parent_hws/_data instead of parent_names

[Marijn Suijten]

On 2021-12-13 17:44:03, Bjorn Andersson wrote:
> On Wed 08 Dec 17:09 CST 2021, Marijn Suijten wrote:
> 
> > On 2021-12-08 20:54:29, Dmitry Baryshkov wrote:
> > > Convert the clock driver to specify parent data rather than parent
> > > names, to actually bind using 'clock-names' specified in the DTS rather
> > > than global clock names. Use parent_hws where possible to refer parent
> > > clocks directly, skipping the lookup.
> > > 
> > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > ---
> > >  drivers/clk/qcom/gcc-msm8996.c | 678 ++++++++++++++++++++++-----------
> > >  1 file changed, 463 insertions(+), 215 deletions(-)
> > > 
> > > diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
> > > index c2f9ae729d1e..186e682e730f 100644
> > > --- a/drivers/clk/qcom/gcc-msm8996.c
> > > +++ b/drivers/clk/qcom/gcc-msm8996.c
> > > @@ -38,7 +38,9 @@ static struct clk_fixed_factor xo = {
> > >  	.div = 1,
> > >  	.hw.init = &(struct clk_init_data){
> > >  		.name = "xo",
> > > -		.parent_names = (const char *[]){ "xo_board" },
> > > +		.parent_data = &(const struct clk_parent_data){
> > > +			.fw_name = "cxo", .name = "xo_board",
> > 
> > I assume you'll submit DT changes later to provide this cxo clock in the
> > DT?  msm8996.dtsi currently only seems to provide a cxo2 clock.
> > 
> > > +		},
> > >  		.num_parents = 1,
> > >  		.ops = &clk_fixed_factor_ops,
> > >  	},
> > > @@ -52,7 +54,9 @@ static struct clk_alpha_pll gpll0_early = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gpll0_early",
> > > -			.parent_names = (const char *[]){ "xo" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&xo.hw,
> > 
> > I always view this local "xo" clock as a "hack" to provide an "xo" clock
> > in the global namespace for drivers and older DTs that don't use clocks=
> > and clock-names= yet.  Since it's an alias for xo_board, it is perhaps
> > better to repeat `.fw_name = "cxo", .name = "xo_board"` here?
> > 
> 
> As mentioned elsewhere, xo_board is the oscillator feeding the PMIC,
> while cxo is the input xo on the SoC, which is connected to an output
> from the PMIC - controlled through rpmh's RPM_SMD_BB_CLK1.
> 
> So the separation is correct, but you're totally right that the local xo
> is a hack from a time when we couldn't make rpmhcc the root of all
> clocks.

So we're in a tough spot regarding keeping .name="xo_board" for
backwards compatibility with older DTs, and .fw_name="cxo" that will
probably receive the fixed-factor xo_board clock from DT until we're
able to substitute that with rpmh's clock.

This recommendation is merely about cutting out the `clk_fixed_factor
xo` middle man, and the suggestion is to use its clk_parent_data
directly here in hopes of removing "xo" and all global dependencies on
it some day (but again, that depends on updated DTs which is regarded
impossible these days).  That should be doable and desirable regardless
of the separation?

- Marijn

> Regards,
> Bjorn
> 
> > Otherwise we might want to swap all those over to `&xo.hw` instead.
> > 
> > > +			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_alpha_pll_ops,
> > >  		},
> > > @@ -64,7 +68,9 @@ static struct clk_fixed_factor gpll0_early_div = {
> > >  	.div = 2,
> > >  	.hw.init = &(struct clk_init_data){
> > >  		.name = "gpll0_early_div",
> > > -		.parent_names = (const char *[]){ "gpll0_early" },
> > > +		.parent_hws = (const struct clk_hw*[]){
> > > +			&gpll0_early.clkr.hw,
> > > +		},
> > >  		.num_parents = 1,
> > >  		.ops = &clk_fixed_factor_ops,
> > >  	},
> > > @@ -75,7 +81,9 @@ static struct clk_alpha_pll_postdiv gpll0 = {
> > >  	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "gpll0",
> > > -		.parent_names = (const char *[]){ "gpll0_early" },
> > > +		.parent_hws = (const struct clk_hw*[]){
> > > +			&gpll0_early.clkr.hw,
> > > +		},
> > >  		.num_parents = 1,
> > >  		.ops = &clk_alpha_pll_postdiv_ops,
> > >  	},
> > > @@ -88,7 +96,9 @@ static struct clk_branch gcc_mmss_gpll0_div_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_mmss_gpll0_div_clk",
> > > -			.parent_names = (const char *[]){ "gpll0" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&gpll0.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -103,7 +113,9 @@ static struct clk_branch gcc_mss_gpll0_div_clk = {
> > >  		.enable_mask = BIT(2),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_mss_gpll0_div_clk",
> > > -			.parent_names = (const char *[]){ "gpll0" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&gpll0.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops
> > > @@ -119,7 +131,9 @@ static struct clk_alpha_pll gpll4_early = {
> > >  		.enable_mask = BIT(4),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gpll4_early",
> > > -			.parent_names = (const char *[]){ "xo" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&xo.hw,
> > 
> > Same question here, and all the other conversions for "xo".
> > 
> > > +			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_alpha_pll_ops,
> > >  		},
> > > @@ -131,7 +145,9 @@ static struct clk_alpha_pll_postdiv gpll4 = {
> > >  	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "gpll4",
> > > -		.parent_names = (const char *[]){ "gpll4_early" },
> > > +		.parent_hws = (const struct clk_hw*[]){
> > > +			&gpll4_early.clkr.hw,
> > > +		},
> > >  		.num_parents = 1,
> > >  		.ops = &clk_alpha_pll_postdiv_ops,
> > >  	},
> > > @@ -141,8 +157,8 @@ static const struct parent_map gcc_sleep_clk_map[] = {
> > >  	{ P_SLEEP_CLK, 5 }
> > >  };
> > >  
> > > -static const char * const gcc_sleep_clk[] = {
> > > -	"sleep_clk"
> > > +static const struct clk_parent_data gcc_sleep_clk[] = {
> > > +	{ .fw_name = "sleep_clk", .name = "sleep_clk" }
> > 
> > This should also be added to the DT.
> > 
> > >  };
> > >  
> > >  static const struct parent_map gcc_xo_gpll0_map[] = {
> > > @@ -150,9 +166,9 @@ static const struct parent_map gcc_xo_gpll0_map[] = {
> > >  	{ P_GPLL0, 1 }
> > >  };
> > >  
> > > -static const char * const gcc_xo_gpll0[] = {
> > > -	"xo",
> > > -	"gpll0"
> > > +static const struct clk_parent_data gcc_xo_gpll0[] = {
> > > +	{ .hw = &xo.hw },
> > > +	{ .hw = &gpll0.clkr.hw }
> > >  };
> > >  
> > >  static const struct parent_map gcc_xo_sleep_clk_map[] = {
> > > @@ -160,9 +176,9 @@ static const struct parent_map gcc_xo_sleep_clk_map[] = {
> > >  	{ P_SLEEP_CLK, 5 }
> > >  };
> > >  
> > > -static const char * const gcc_xo_sleep_clk[] = {
> > > -	"xo",
> > > -	"sleep_clk"
> > > +static const struct clk_parent_data gcc_xo_sleep_clk[] = {
> > > +	{ .hw = &xo.hw },
> > > +	{ .fw_name = "sleep_clk", .name = "sleep_clk" }
> > >  };
> > >  
> > >  static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
> > > @@ -171,10 +187,10 @@ static const struct parent_map gcc_xo_gpll0_gpll0_early_div_map[] = {
> > >  	{ P_GPLL0_EARLY_DIV, 6 }
> > >  };
> > >  
> > > -static const char * const gcc_xo_gpll0_gpll0_early_div[] = {
> > > -	"xo",
> > > -	"gpll0",
> > > -	"gpll0_early_div"
> > > +static const struct clk_parent_data gcc_xo_gpll0_gpll0_early_div[] = {
> > > +	{ .hw = &xo.hw },
> > > +	{ .hw = &gpll0.clkr.hw },
> > > +	{ .hw = &gpll0_early_div.hw }
> > >  };
> > >  
> > >  static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
> > > @@ -183,10 +199,10 @@ static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
> > >  	{ P_GPLL4, 5 }
> > >  };
> > >  
> > > -static const char * const gcc_xo_gpll0_gpll4[] = {
> > > -	"xo",
> > > -	"gpll0",
> > > -	"gpll4"
> > > +static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
> > > +	{ .hw = &xo.hw },
> > > +	{ .hw = &gpll0.clkr.hw },
> > > +	{ .hw = &gpll4.clkr.hw }
> > >  };
> > >  
> > >  static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
> > > @@ -195,10 +211,10 @@ static const struct parent_map gcc_xo_gpll0_aud_ref_clk_map[] = {
> > >  	{ P_AUD_REF_CLK, 2 }
> > >  };
> > >  
> > > -static const char * const gcc_xo_gpll0_aud_ref_clk[] = {
> > > -	"xo",
> > > -	"gpll0",
> > > -	"aud_ref_clk"
> > > +static const struct clk_parent_data gcc_xo_gpll0_aud_ref_clk[] = {
> > > +	{ .hw = &xo.hw },
> > > +	{ .hw = &gpll0.clkr.hw },
> > > +	{ .fw_name = "aud_ref_clk", .name = "aud_ref_clk" }
> > 
> > Don't forget to add this clock to the DT-bindings.
> > 
> > >  };
> > >  
> > >  static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
> > > @@ -208,11 +224,11 @@ static const struct parent_map gcc_xo_gpll0_sleep_clk_gpll0_early_div_map[] = {
> > >  	{ P_GPLL0_EARLY_DIV, 6 }
> > >  };
> > >  
> > > -static const char * const gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
> > > -	"xo",
> > > -	"gpll0",
> > > -	"sleep_clk",
> > > -	"gpll0_early_div"
> > > +static const struct clk_parent_data gcc_xo_gpll0_sleep_clk_gpll0_early_div[] = {
> > > +	{ .hw = &xo.hw },
> > > +	{ .hw = &gpll0.clkr.hw },
> > > +	{ .fw_name = "sleep_clk", .name = "sleep_clk" },
> > > +	{ .hw = &gpll0_early_div.hw }
> > >  };
> > >  
> > >  static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
> > > @@ -222,11 +238,11 @@ static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_early_div_map[] = {
> > >  	{ P_GPLL0_EARLY_DIV, 6 }
> > >  };
> > >  
> > > -static const char * const gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
> > > -	"xo",
> > > -	"gpll0",
> > > -	"gpll4",
> > > -	"gpll0_early_div"
> > > +static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_early_div[] = {
> > > +	{ .hw = &xo.hw },
> > > +	{ .hw = &gpll0.clkr.hw },
> > > +	{ .hw = &gpll4.clkr.hw },
> > > +	{ .hw = &gpll0_early_div.hw }
> > >  };
> > >  
> > >  static const struct freq_tbl ftbl_system_noc_clk_src[] = {
> > > @@ -246,7 +262,7 @@ static struct clk_rcg2 system_noc_clk_src = {
> > >  	.freq_tbl = ftbl_system_noc_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "system_noc_clk_src",
> > > -		.parent_names = gcc_xo_gpll0_gpll0_early_div,
> > > +		.parent_data = gcc_xo_gpll0_gpll0_early_div,
> > >  		.num_parents = 3,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -266,7 +282,7 @@ static struct clk_rcg2 config_noc_clk_src = {
> > >  	.freq_tbl = ftbl_config_noc_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "config_noc_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -288,7 +304,7 @@ static struct clk_rcg2 periph_noc_clk_src = {
> > >  	.freq_tbl = ftbl_periph_noc_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "periph_noc_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -309,7 +325,7 @@ static struct clk_rcg2 usb30_master_clk_src = {
> > >  	.freq_tbl = ftbl_usb30_master_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "usb30_master_clk_src",
> > > -		.parent_names = gcc_xo_gpll0_gpll0_early_div,
> > > +		.parent_data = gcc_xo_gpll0_gpll0_early_div,
> > >  		.num_parents = 3,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -327,7 +343,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = {
> > >  	.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "usb30_mock_utmi_clk_src",
> > > -		.parent_names = gcc_xo_gpll0_gpll0_early_div,
> > > +		.parent_data = gcc_xo_gpll0_gpll0_early_div,
> > >  		.num_parents = 3,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -345,7 +361,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = {
> > >  	.freq_tbl = ftbl_usb3_phy_aux_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "usb3_phy_aux_clk_src",
> > > -		.parent_names = gcc_xo_sleep_clk,
> > > +		.parent_data = gcc_xo_sleep_clk,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -364,7 +380,7 @@ static struct clk_rcg2 usb20_master_clk_src = {
> > >  	.freq_tbl = ftbl_usb20_master_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "usb20_master_clk_src",
> > > -		.parent_names = gcc_xo_gpll0_gpll0_early_div,
> > > +		.parent_data = gcc_xo_gpll0_gpll0_early_div,
> > >  		.num_parents = 3,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -377,7 +393,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = {
> > >  	.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "usb20_mock_utmi_clk_src",
> > > -		.parent_names = gcc_xo_gpll0_gpll0_early_div,
> > > +		.parent_data = gcc_xo_gpll0_gpll0_early_div,
> > >  		.num_parents = 3,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -403,7 +419,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
> > >  	.freq_tbl = ftbl_sdcc1_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "sdcc1_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
> > > +		.parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
> > >  		.num_parents = 4,
> > >  		.ops = &clk_rcg2_floor_ops,
> > >  	},
> > > @@ -423,7 +439,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = {
> > >  	.freq_tbl = ftbl_sdcc1_ice_core_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "sdcc1_ice_core_clk_src",
> > > -		.parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
> > > +		.parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
> > >  		.num_parents = 4,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -448,7 +464,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = {
> > >  	.freq_tbl = ftbl_sdcc2_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "sdcc2_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0_gpll4,
> > > +		.parent_data = gcc_xo_gpll0_gpll4,
> > >  		.num_parents = 3,
> > >  		.ops = &clk_rcg2_floor_ops,
> > >  	},
> > > @@ -462,7 +478,7 @@ static struct clk_rcg2 sdcc3_apps_clk_src = {
> > >  	.freq_tbl = ftbl_sdcc2_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "sdcc3_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0_gpll4,
> > > +		.parent_data = gcc_xo_gpll0_gpll4,
> > >  		.num_parents = 3,
> > >  		.ops = &clk_rcg2_floor_ops,
> > >  	},
> > > @@ -486,7 +502,7 @@ static struct clk_rcg2 sdcc4_apps_clk_src = {
> > >  	.freq_tbl = ftbl_sdcc4_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "sdcc4_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_floor_ops,
> > >  	},
> > > @@ -511,7 +527,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp1_qup1_spi_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -530,7 +546,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp1_qup1_i2c_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -563,7 +579,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp1_uart1_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -577,7 +593,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp1_qup2_spi_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -590,7 +606,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp1_qup2_i2c_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -604,7 +620,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp1_uart2_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -618,7 +634,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp1_qup3_spi_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -631,7 +647,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp1_qup3_i2c_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -645,7 +661,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp1_uart3_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -659,7 +675,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp1_qup4_spi_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -672,7 +688,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp1_qup4_i2c_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -686,7 +702,7 @@ static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp1_uart4_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -700,7 +716,7 @@ static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp1_qup5_spi_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -713,7 +729,7 @@ static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp1_qup5_i2c_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -727,7 +743,7 @@ static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp1_uart5_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -741,7 +757,7 @@ static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp1_qup6_spi_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -754,7 +770,7 @@ static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp1_qup6_i2c_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -768,7 +784,7 @@ static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp1_uart6_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -782,7 +798,7 @@ static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp2_qup1_spi_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -795,7 +811,7 @@ static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp2_qup1_i2c_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -809,7 +825,7 @@ static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp2_uart1_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -823,7 +839,7 @@ static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp2_qup2_spi_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -836,7 +852,7 @@ static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp2_qup2_i2c_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -850,7 +866,7 @@ static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp2_uart2_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -864,7 +880,7 @@ static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp2_qup3_spi_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -877,7 +893,7 @@ static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp2_qup3_i2c_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -891,7 +907,7 @@ static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp2_uart3_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -905,7 +921,7 @@ static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp2_qup4_spi_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -918,7 +934,7 @@ static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp2_qup4_i2c_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -932,7 +948,7 @@ static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp2_uart4_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -946,7 +962,7 @@ static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp2_qup5_spi_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -959,7 +975,7 @@ static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp2_qup5_i2c_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -973,7 +989,7 @@ static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp2_uart5_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -987,7 +1003,7 @@ static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp2_qup6_spi_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -1000,7 +1016,7 @@ static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp2_qup6_i2c_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -1014,7 +1030,7 @@ static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
> > >  	.freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "blsp2_uart6_apps_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -1032,7 +1048,7 @@ static struct clk_rcg2 pdm2_clk_src = {
> > >  	.freq_tbl = ftbl_pdm2_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "pdm2_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -1051,7 +1067,7 @@ static struct clk_rcg2 tsif_ref_clk_src = {
> > >  	.freq_tbl = ftbl_tsif_ref_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "tsif_ref_clk_src",
> > > -		.parent_names = gcc_xo_gpll0_aud_ref_clk,
> > > +		.parent_data = gcc_xo_gpll0_aud_ref_clk,
> > >  		.num_parents = 3,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -1063,7 +1079,7 @@ static struct clk_rcg2 gcc_sleep_clk_src = {
> > >  	.parent_map = gcc_sleep_clk_map,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "gcc_sleep_clk_src",
> > > -		.parent_names = gcc_sleep_clk,
> > > +		.parent_data = gcc_sleep_clk,
> > >  		.num_parents = 1,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -1076,7 +1092,7 @@ static struct clk_rcg2 hmss_rbcpr_clk_src = {
> > >  	.freq_tbl = ftbl_usb30_mock_utmi_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "hmss_rbcpr_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -1088,7 +1104,7 @@ static struct clk_rcg2 hmss_gpll0_clk_src = {
> > >  	.parent_map = gcc_xo_gpll0_map,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "hmss_gpll0_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -1109,7 +1125,7 @@ static struct clk_rcg2 gp1_clk_src = {
> > >  	.freq_tbl = ftbl_gp1_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "gp1_clk_src",
> > > -		.parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
> > > +		.parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
> > >  		.num_parents = 4,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -1123,7 +1139,7 @@ static struct clk_rcg2 gp2_clk_src = {
> > >  	.freq_tbl = ftbl_gp1_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "gp2_clk_src",
> > > -		.parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
> > > +		.parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
> > >  		.num_parents = 4,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -1137,7 +1153,7 @@ static struct clk_rcg2 gp3_clk_src = {
> > >  	.freq_tbl = ftbl_gp1_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "gp3_clk_src",
> > > -		.parent_names = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
> > > +		.parent_data = gcc_xo_gpll0_sleep_clk_gpll0_early_div,
> > >  		.num_parents = 4,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -1156,7 +1172,7 @@ static struct clk_rcg2 pcie_aux_clk_src = {
> > >  	.freq_tbl = ftbl_pcie_aux_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "pcie_aux_clk_src",
> > > -		.parent_names = gcc_xo_sleep_clk,
> > > +		.parent_data = gcc_xo_sleep_clk,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -1177,7 +1193,7 @@ static struct clk_rcg2 ufs_axi_clk_src = {
> > >  	.freq_tbl = ftbl_ufs_axi_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "ufs_axi_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -1197,7 +1213,7 @@ static struct clk_rcg2 ufs_ice_core_clk_src = {
> > >  	.freq_tbl = ftbl_ufs_ice_core_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "ufs_ice_core_clk_src",
> > > -		.parent_names = gcc_xo_gpll0,
> > > +		.parent_data = gcc_xo_gpll0,
> > >  		.num_parents = 2,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -1218,7 +1234,7 @@ static struct clk_rcg2 qspi_ser_clk_src = {
> > >  	.freq_tbl = ftbl_qspi_ser_clk_src,
> > >  	.clkr.hw.init = &(struct clk_init_data){
> > >  		.name = "qspi_ser_clk_src",
> > > -		.parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
> > > +		.parent_data = gcc_xo_gpll0_gpll4_gpll0_early_div,
> > >  		.num_parents = 4,
> > >  		.ops = &clk_rcg2_ops,
> > >  	},
> > > @@ -1231,7 +1247,9 @@ static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_sys_noc_usb3_axi_clk",
> > > -			.parent_names = (const char *[]){ "usb30_master_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&usb30_master_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1246,7 +1264,9 @@ static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_sys_noc_ufs_axi_clk",
> > > -			.parent_names = (const char *[]){ "ufs_axi_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&ufs_axi_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1261,7 +1281,9 @@ static struct clk_branch gcc_periph_noc_usb20_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_periph_noc_usb20_ahb_clk",
> > > -			.parent_names = (const char *[]){ "usb20_master_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&usb20_master_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1276,7 +1298,9 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_mmss_noc_cfg_ahb_clk",
> > > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&config_noc_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1304,7 +1328,9 @@ static struct clk_branch gcc_usb30_master_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_usb30_master_clk",
> > > -			.parent_names = (const char *[]){ "usb30_master_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&usb30_master_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1319,7 +1345,9 @@ static struct clk_branch gcc_usb30_sleep_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_usb30_sleep_clk",
> > > -			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&gcc_sleep_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1334,7 +1362,9 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_usb30_mock_utmi_clk",
> > > -			.parent_names = (const char *[]){ "usb30_mock_utmi_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&usb30_mock_utmi_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1349,7 +1379,9 @@ static struct clk_branch gcc_usb3_phy_aux_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_usb3_phy_aux_clk",
> > > -			.parent_names = (const char *[]){ "usb3_phy_aux_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&usb3_phy_aux_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1365,7 +1397,9 @@ static struct clk_branch gcc_usb3_phy_pipe_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_usb3_phy_pipe_clk",
> > > -			.parent_names = (const char *[]){ "usb3_phy_pipe_clk_src" },
> > > +			.parent_data = &(const struct clk_parent_data){
> > > +				.fw_name = "usb3_phy_pipe_clk_src", .name = "usb3_phy_pipe_clk_src",
> > 
> > Don't forget to add this clock to the DT-bindings.
> > 
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1380,7 +1414,9 @@ static struct clk_branch gcc_usb20_master_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_usb20_master_clk",
> > > -			.parent_names = (const char *[]){ "usb20_master_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&usb20_master_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1395,7 +1431,9 @@ static struct clk_branch gcc_usb20_sleep_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_usb20_sleep_clk",
> > > -			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&gcc_sleep_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1410,7 +1448,9 @@ static struct clk_branch gcc_usb20_mock_utmi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_usb20_mock_utmi_clk",
> > > -			.parent_names = (const char *[]){ "usb20_mock_utmi_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&usb20_mock_utmi_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1425,7 +1465,9 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_usb_phy_cfg_ahb2phy_clk",
> > > -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> > > +			.parent_data = &(const struct clk_parent_data){
> > > +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> > 
> > Don't forget to add this clock to the DT-bindings.
> > 
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1440,7 +1482,9 @@ static struct clk_branch gcc_sdcc1_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_sdcc1_apps_clk",
> > > -			.parent_names = (const char *[]){ "sdcc1_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&sdcc1_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1455,7 +1499,9 @@ static struct clk_branch gcc_sdcc1_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_sdcc1_ahb_clk",
> > > -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> > > +			.parent_data = &(const struct clk_parent_data){
> > > +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1470,7 +1516,9 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_sdcc1_ice_core_clk",
> > > -			.parent_names = (const char *[]){ "sdcc1_ice_core_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&sdcc1_ice_core_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1485,7 +1533,9 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_sdcc2_apps_clk",
> > > -			.parent_names = (const char *[]){ "sdcc2_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&sdcc2_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1500,7 +1550,9 @@ static struct clk_branch gcc_sdcc2_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_sdcc2_ahb_clk",
> > > -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> > > +			.parent_data = &(const struct clk_parent_data){
> > > +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1515,7 +1567,9 @@ static struct clk_branch gcc_sdcc3_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_sdcc3_apps_clk",
> > > -			.parent_names = (const char *[]){ "sdcc3_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&sdcc3_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1530,7 +1584,9 @@ static struct clk_branch gcc_sdcc3_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_sdcc3_ahb_clk",
> > > -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> > > +			.parent_data = &(const struct clk_parent_data){
> > > +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1545,7 +1601,9 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_sdcc4_apps_clk",
> > > -			.parent_names = (const char *[]){ "sdcc4_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&sdcc4_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1560,7 +1618,9 @@ static struct clk_branch gcc_sdcc4_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_sdcc4_ahb_clk",
> > > -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> > > +			.parent_data = &(const struct clk_parent_data){
> > > +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1576,7 +1636,9 @@ static struct clk_branch gcc_blsp1_ahb_clk = {
> > >  		.enable_mask = BIT(17),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp1_ahb_clk",
> > > -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> > > +			.parent_data = &(const struct clk_parent_data){
> > > +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1592,7 +1654,9 @@ static struct clk_branch gcc_blsp1_sleep_clk = {
> > >  		.enable_mask = BIT(16),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp1_sleep_clk",
> > > -			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&gcc_sleep_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1607,7 +1671,9 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp1_qup1_spi_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp1_qup1_spi_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp1_qup1_spi_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1622,7 +1688,9 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp1_qup1_i2c_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp1_qup1_i2c_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp1_qup1_i2c_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1637,7 +1705,9 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp1_uart1_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp1_uart1_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp1_uart1_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1652,7 +1722,9 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp1_qup2_spi_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp1_qup2_spi_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp1_qup2_spi_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1667,7 +1739,9 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp1_qup2_i2c_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp1_qup2_i2c_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp1_qup2_i2c_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1682,7 +1756,9 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp1_uart2_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp1_uart2_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp1_uart2_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1697,7 +1773,9 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp1_qup3_spi_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp1_qup3_spi_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp1_qup3_spi_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1712,7 +1790,9 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp1_qup3_i2c_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp1_qup3_i2c_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp1_qup3_i2c_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1727,7 +1807,9 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp1_uart3_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp1_uart3_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp1_uart3_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1742,7 +1824,9 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp1_qup4_spi_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp1_qup4_spi_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp1_qup4_spi_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1757,7 +1841,9 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp1_qup4_i2c_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp1_qup4_i2c_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp1_qup4_i2c_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1772,7 +1858,9 @@ static struct clk_branch gcc_blsp1_uart4_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp1_uart4_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp1_uart4_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp1_uart4_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1787,7 +1875,9 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp1_qup5_spi_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp1_qup5_spi_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp1_qup5_spi_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1802,7 +1892,9 @@ static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp1_qup5_i2c_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp1_qup5_i2c_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp1_qup5_i2c_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1817,7 +1909,9 @@ static struct clk_branch gcc_blsp1_uart5_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp1_uart5_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp1_uart5_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp1_uart5_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1832,7 +1926,9 @@ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp1_qup6_spi_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp1_qup6_spi_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp1_qup6_spi_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1847,7 +1943,9 @@ static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp1_qup6_i2c_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp1_qup6_i2c_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp1_qup6_i2c_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1862,7 +1960,9 @@ static struct clk_branch gcc_blsp1_uart6_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp1_uart6_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp1_uart6_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp1_uart6_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1878,7 +1978,9 @@ static struct clk_branch gcc_blsp2_ahb_clk = {
> > >  		.enable_mask = BIT(15),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp2_ahb_clk",
> > > -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> > > +			.parent_data = &(const struct clk_parent_data){
> > > +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1894,7 +1996,9 @@ static struct clk_branch gcc_blsp2_sleep_clk = {
> > >  		.enable_mask = BIT(14),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp2_sleep_clk",
> > > -			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&gcc_sleep_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1909,7 +2013,9 @@ static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp2_qup1_spi_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp2_qup1_spi_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp2_qup1_spi_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1924,7 +2030,9 @@ static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp2_qup1_i2c_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp2_qup1_i2c_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp2_qup1_i2c_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1939,7 +2047,9 @@ static struct clk_branch gcc_blsp2_uart1_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp2_uart1_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp2_uart1_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp2_uart1_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1954,7 +2064,9 @@ static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp2_qup2_spi_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp2_qup2_spi_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp2_qup2_spi_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1969,7 +2081,9 @@ static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp2_qup2_i2c_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp2_qup2_i2c_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp2_qup2_i2c_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1984,7 +2098,9 @@ static struct clk_branch gcc_blsp2_uart2_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp2_uart2_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp2_uart2_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp2_uart2_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -1999,7 +2115,9 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp2_qup3_spi_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp2_qup3_spi_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp2_qup3_spi_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2014,7 +2132,9 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp2_qup3_i2c_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp2_qup3_i2c_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp2_qup3_i2c_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2029,7 +2149,9 @@ static struct clk_branch gcc_blsp2_uart3_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp2_uart3_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp2_uart3_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp2_uart3_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2044,7 +2166,9 @@ static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp2_qup4_spi_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp2_qup4_spi_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp2_qup4_spi_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2059,7 +2183,9 @@ static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp2_qup4_i2c_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp2_qup4_i2c_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp2_qup4_i2c_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2074,7 +2200,9 @@ static struct clk_branch gcc_blsp2_uart4_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp2_uart4_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp2_uart4_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp2_uart4_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2089,7 +2217,9 @@ static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp2_qup5_spi_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp2_qup5_spi_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp2_qup5_spi_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2104,7 +2234,9 @@ static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp2_qup5_i2c_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp2_qup5_i2c_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp2_qup5_i2c_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2119,7 +2251,9 @@ static struct clk_branch gcc_blsp2_uart5_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp2_uart5_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp2_uart5_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp2_uart5_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2134,7 +2268,9 @@ static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp2_qup6_spi_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp2_qup6_spi_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp2_qup6_spi_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2149,7 +2285,9 @@ static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp2_qup6_i2c_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp2_qup6_i2c_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp2_qup6_i2c_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2164,7 +2302,9 @@ static struct clk_branch gcc_blsp2_uart6_apps_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_blsp2_uart6_apps_clk",
> > > -			.parent_names = (const char *[]){ "blsp2_uart6_apps_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&blsp2_uart6_apps_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2179,7 +2319,9 @@ static struct clk_branch gcc_pdm_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_pdm_ahb_clk",
> > > -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> > > +			.parent_data = &(const struct clk_parent_data){
> > > +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2194,7 +2336,9 @@ static struct clk_branch gcc_pdm2_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_pdm2_clk",
> > > -			.parent_names = (const char *[]){ "pdm2_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&pdm2_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2210,7 +2354,9 @@ static struct clk_branch gcc_prng_ahb_clk = {
> > >  		.enable_mask = BIT(13),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_prng_ahb_clk",
> > > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&config_noc_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2225,7 +2371,9 @@ static struct clk_branch gcc_tsif_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_tsif_ahb_clk",
> > > -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> > > +			.parent_data = &(const struct clk_parent_data){
> > > +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2240,7 +2388,9 @@ static struct clk_branch gcc_tsif_ref_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_tsif_ref_clk",
> > > -			.parent_names = (const char *[]){ "tsif_ref_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&tsif_ref_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2255,7 +2405,9 @@ static struct clk_branch gcc_tsif_inactivity_timers_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_tsif_inactivity_timers_clk",
> > > -			.parent_names = (const char *[]){ "gcc_sleep_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&gcc_sleep_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2271,7 +2423,9 @@ static struct clk_branch gcc_boot_rom_ahb_clk = {
> > >  		.enable_mask = BIT(10),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_boot_rom_ahb_clk",
> > > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&config_noc_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2299,7 +2453,9 @@ static struct clk_branch gcc_hmss_rbcpr_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_hmss_rbcpr_clk",
> > > -			.parent_names = (const char *[]){ "hmss_rbcpr_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&hmss_rbcpr_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2314,7 +2470,9 @@ static struct clk_branch gcc_gp1_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_gp1_clk",
> > > -			.parent_names = (const char *[]){ "gp1_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&gp1_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2329,7 +2487,9 @@ static struct clk_branch gcc_gp2_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_gp2_clk",
> > > -			.parent_names = (const char *[]){ "gp2_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&gp2_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2344,7 +2504,9 @@ static struct clk_branch gcc_gp3_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_gp3_clk",
> > > -			.parent_names = (const char *[]){ "gp3_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&gp3_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2359,7 +2521,9 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_pcie_0_slv_axi_clk",
> > > -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&system_noc_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2374,7 +2538,9 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_pcie_0_mstr_axi_clk",
> > > -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&system_noc_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2389,7 +2555,9 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_pcie_0_cfg_ahb_clk",
> > > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&config_noc_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2404,7 +2572,9 @@ static struct clk_branch gcc_pcie_0_aux_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_pcie_0_aux_clk",
> > > -			.parent_names = (const char *[]){ "pcie_aux_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&pcie_aux_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2420,7 +2590,9 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_pcie_0_pipe_clk",
> > > -			.parent_names = (const char *[]){ "pcie_0_pipe_clk_src" },
> > > +			.parent_data = &(const struct clk_parent_data){
> > > +				.fw_name = "pcie_0_pipe_clk_src", .name = "pcie_0_pipe_clk_src",
> > 
> > Don't forget to add this clock to the DT-bindings.
> > 
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2435,7 +2607,9 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_pcie_1_slv_axi_clk",
> > > -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&system_noc_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2450,7 +2624,9 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_pcie_1_mstr_axi_clk",
> > > -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&system_noc_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2465,7 +2641,9 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_pcie_1_cfg_ahb_clk",
> > > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&config_noc_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2480,7 +2658,9 @@ static struct clk_branch gcc_pcie_1_aux_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_pcie_1_aux_clk",
> > > -			.parent_names = (const char *[]){ "pcie_aux_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&pcie_aux_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2496,7 +2676,9 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_pcie_1_pipe_clk",
> > > -			.parent_names = (const char *[]){ "pcie_1_pipe_clk_src" },
> > > +			.parent_data = &(const struct clk_parent_data){
> > > +				.fw_name = "pcie_1_pipe_clk_src", .name = "pcie_1_pipe_clk_src",
> > 
> > Don't forget to add this clock to the DT-bindings.
> > 
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2511,7 +2693,9 @@ static struct clk_branch gcc_pcie_2_slv_axi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_pcie_2_slv_axi_clk",
> > > -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&system_noc_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2526,7 +2710,9 @@ static struct clk_branch gcc_pcie_2_mstr_axi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_pcie_2_mstr_axi_clk",
> > > -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&system_noc_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2541,7 +2727,9 @@ static struct clk_branch gcc_pcie_2_cfg_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_pcie_2_cfg_ahb_clk",
> > > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&config_noc_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2556,7 +2744,9 @@ static struct clk_branch gcc_pcie_2_aux_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_pcie_2_aux_clk",
> > > -			.parent_names = (const char *[]){ "pcie_aux_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&pcie_aux_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2572,7 +2762,9 @@ static struct clk_branch gcc_pcie_2_pipe_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_pcie_2_pipe_clk",
> > > -			.parent_names = (const char *[]){ "pcie_2_pipe_clk_src" },
> > > +			.parent_data = &(const struct clk_parent_data){
> > > +				.fw_name = "pcie_2_pipe_clk_src", .name = "pcie_2_pipe_clk_src",
> > 
> > Don't forget to add this clock to the DT-bindings.
> > 
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2587,7 +2779,9 @@ static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_pcie_phy_cfg_ahb_clk",
> > > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&config_noc_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2602,7 +2796,9 @@ static struct clk_branch gcc_pcie_phy_aux_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_pcie_phy_aux_clk",
> > > -			.parent_names = (const char *[]){ "pcie_aux_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&pcie_aux_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2617,7 +2813,9 @@ static struct clk_branch gcc_ufs_axi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_ufs_axi_clk",
> > > -			.parent_names = (const char *[]){ "ufs_axi_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&ufs_axi_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2632,7 +2830,9 @@ static struct clk_branch gcc_ufs_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_ufs_ahb_clk",
> > > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&config_noc_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2645,7 +2845,9 @@ static struct clk_fixed_factor ufs_tx_cfg_clk_src = {
> > >  	.div = 16,
> > >  	.hw.init = &(struct clk_init_data){
> > >  		.name = "ufs_tx_cfg_clk_src",
> > > -		.parent_names = (const char *[]){ "ufs_axi_clk_src" },
> > > +		.parent_hws = (const struct clk_hw*[]){
> > > +			&ufs_axi_clk_src.clkr.hw,
> > > +		},
> > >  		.num_parents = 1,
> > >  		.flags = CLK_SET_RATE_PARENT,
> > >  		.ops = &clk_fixed_factor_ops,
> > > @@ -2659,7 +2861,9 @@ static struct clk_branch gcc_ufs_tx_cfg_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_ufs_tx_cfg_clk",
> > > -			.parent_names = (const char *[]){ "ufs_tx_cfg_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&ufs_tx_cfg_clk_src.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2672,7 +2876,9 @@ static struct clk_fixed_factor ufs_rx_cfg_clk_src = {
> > >  	.div = 16,
> > >  	.hw.init = &(struct clk_init_data){
> > >  		.name = "ufs_rx_cfg_clk_src",
> > > -		.parent_names = (const char *[]){ "ufs_axi_clk_src" },
> > > +		.parent_hws = (const struct clk_hw*[]){
> > > +			&ufs_axi_clk_src.clkr.hw,
> > > +		},
> > >  		.num_parents = 1,
> > >  		.flags = CLK_SET_RATE_PARENT,
> > >  		.ops = &clk_fixed_factor_ops,
> > > @@ -2712,7 +2918,9 @@ static struct clk_branch gcc_ufs_rx_cfg_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_ufs_rx_cfg_clk",
> > > -			.parent_names = (const char *[]){ "ufs_rx_cfg_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&ufs_rx_cfg_clk_src.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2728,7 +2936,9 @@ static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_ufs_tx_symbol_0_clk",
> > > -			.parent_names = (const char *[]){ "ufs_tx_symbol_0_clk_src" },
> > > +			.parent_data = &(const struct clk_parent_data){
> > > +				.fw_name = "ufs_tx_symbol_0_clk_src", .name = "ufs_tx_symbol_0_clk_src",
> > 
> > Don't forget to add this clock to the DT-bindings.
> > 
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2744,7 +2954,9 @@ static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_ufs_rx_symbol_0_clk",
> > > -			.parent_names = (const char *[]){ "ufs_rx_symbol_0_clk_src" },
> > > +			.parent_data = &(const struct clk_parent_data){
> > > +				.fw_name = "ufs_rx_symbol_0_clk_src", .name = "ufs_rx_symbol_0_clk_src",
> > 
> > Don't forget to add this clock to the DT-bindings.
> > 
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2760,7 +2972,9 @@ static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_ufs_rx_symbol_1_clk",
> > > -			.parent_names = (const char *[]){ "ufs_rx_symbol_1_clk_src" },
> > > +			.parent_data = &(const struct clk_parent_data){
> > > +				.fw_name = "ufs_rx_symbol_1_clk_src", .name = "ufs_rx_symbol_1_clk_src",
> > 
> > Don't forget to add this clock to the DT-bindings.
> > 
> > - Marijn
> > 
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2773,7 +2987,9 @@ static struct clk_fixed_factor ufs_ice_core_postdiv_clk_src = {
> > >  	.div = 2,
> > >  	.hw.init = &(struct clk_init_data){
> > >  		.name = "ufs_ice_core_postdiv_clk_src",
> > > -		.parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
> > > +		.parent_hws = (const struct clk_hw*[]){
> > > +			&ufs_ice_core_clk_src.clkr.hw,
> > > +		},
> > >  		.num_parents = 1,
> > >  		.flags = CLK_SET_RATE_PARENT,
> > >  		.ops = &clk_fixed_factor_ops,
> > > @@ -2787,7 +3003,9 @@ static struct clk_branch gcc_ufs_unipro_core_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_ufs_unipro_core_clk",
> > > -			.parent_names = (const char *[]){ "ufs_ice_core_postdiv_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&ufs_ice_core_postdiv_clk_src.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2802,7 +3020,9 @@ static struct clk_branch gcc_ufs_ice_core_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_ufs_ice_core_clk",
> > > -			.parent_names = (const char *[]){ "ufs_ice_core_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&ufs_ice_core_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2841,7 +3061,9 @@ static struct clk_branch gcc_aggre0_snoc_axi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_aggre0_snoc_axi_clk",
> > > -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&system_noc_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2856,7 +3078,9 @@ static struct clk_branch gcc_aggre0_cnoc_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_aggre0_cnoc_ahb_clk",
> > > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&config_noc_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2871,7 +3095,9 @@ static struct clk_branch gcc_smmu_aggre0_axi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_smmu_aggre0_axi_clk",
> > > -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&system_noc_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2886,7 +3112,9 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_smmu_aggre0_ahb_clk",
> > > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&config_noc_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2901,7 +3129,9 @@ static struct clk_branch gcc_aggre2_ufs_axi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_aggre2_ufs_axi_clk",
> > > -			.parent_names = (const char *[]){ "ufs_axi_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&ufs_axi_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2916,7 +3146,9 @@ static struct clk_branch gcc_aggre2_usb3_axi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_aggre2_usb3_axi_clk",
> > > -			.parent_names = (const char *[]){ "usb30_master_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&usb30_master_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2931,7 +3163,9 @@ static struct clk_branch gcc_dcc_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_dcc_ahb_clk",
> > > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&config_noc_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > >  		},
> > > @@ -2945,7 +3179,9 @@ static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",
> > > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&config_noc_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > >  		},
> > > @@ -2959,7 +3195,9 @@ static struct clk_branch gcc_qspi_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_qspi_ahb_clk",
> > > -			.parent_names = (const char *[]){ "periph_noc_clk_src" },
> > > +			.parent_data = &(const struct clk_parent_data){
> > > +				.fw_name = "periph_noc_clk_src", .name = "periph_noc_clk_src",
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -2974,7 +3212,9 @@ static struct clk_branch gcc_qspi_ser_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_qspi_ser_clk",
> > > -			.parent_names = (const char *[]){ "qspi_ser_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&qspi_ser_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.flags = CLK_SET_RATE_PARENT,
> > >  			.ops = &clk_branch2_ops,
> > > @@ -3108,7 +3348,9 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_mss_cfg_ahb_clk",
> > > -			.parent_names = (const char *[]){ "config_noc_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&config_noc_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > >  		},
> > > @@ -3122,7 +3364,9 @@ static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_mss_mnoc_bimc_axi_clk",
> > > -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&system_noc_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > >  		},
> > > @@ -3136,7 +3380,9 @@ static struct clk_branch gcc_mss_snoc_axi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_mss_snoc_axi_clk",
> > > -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&system_noc_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > >  		},
> > > @@ -3150,7 +3396,9 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
> > >  		.enable_mask = BIT(0),
> > >  		.hw.init = &(struct clk_init_data){
> > >  			.name = "gcc_mss_q6_bimc_axi_clk",
> > > -			.parent_names = (const char *[]){ "system_noc_clk_src" },
> > > +			.parent_hws = (const struct clk_hw*[]){
> > > +				&system_noc_clk_src.clkr.hw,
> > > +			},
> > >  			.num_parents = 1,
> > >  			.ops = &clk_branch2_ops,
> > >  		},
> > > -- 
> > > 2.33.0
> > > 

Re: [PATCH 06/11] clk: qcom: camcc-sc7180: use parent_hws instead of parent_data

[Dmitry Baryshkov]

On 09/12/2021 11:11, Stephen Boyd wrote:
> Quoting Dmitry Baryshkov (2021-12-08 09:54:25)
>> If all parents are specified as clk_hw, we can use parent_hws instead of
>> parent_data.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
> 
> Is the code size smaller? Would be nice to add that detail.

The bloat-o-meter reports zero size difference.

> Reviewed-by: Stephen Boyd <sboyd@kernel.org>


-- 
With best wishes
Dmitry