* [PATCH v2 0/3] arm64: dts: qcom: sm8450-hdk: add sound support
@ 2022-11-15 11:00 Krzysztof Kozlowski
2022-11-15 11:00 ` [PATCH v2 1/3] arm64: dts: qcom: sm8450: add GPR node Krzysztof Kozlowski
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Krzysztof Kozlowski @ 2022-11-15 11:00 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel
Cc: Krzysztof Kozlowski
Hi,
Changes since v1
================
1. Patch 2:
- Whitespace cleanups.
- Correct include - do not use deprecated one.
2. Patch 3:
- Sort.
- Add Rb tag.
- Correct include - do not use deprecated one and drop q6asm.h (not used).
Description
===========
Initial work (still partially in progress) adding audio to HDK8450 board.
Working/tested:
- speakers
- one channel of headset
The DTS patches do not have particular dependencies, however they:
1. Use updated ASoC bindings:
https://lore.kernel.org/linux-arm-msm/20221111113547.100442-1-krzysztof.kozlowski@linaro.org/T/#t
2. For full operation need changes in Soundwire and Qualcomm ASoC drivers, not
yet upstreamed:
https://github.com/krzk/linux/commits/wip/sm8450
Booting remoteproc without these changes will report errors, but these are
expected at this stage.
Best regards,
Krzysztof
Srinivas Kandagatla (3):
arm64: dts: qcom: sm8450: add GPR node
arm64: dts: qcom: sm8450: add Soundwire and LPASS
arm64: dts: qcom: sm8450-hdk: add sound support
arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 160 +++++++++++
arch/arm64/boot/dts/qcom/sm8450.dtsi | 335 ++++++++++++++++++++++++
2 files changed, 495 insertions(+)
--
2.34.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v2 1/3] arm64: dts: qcom: sm8450: add GPR node 2022-11-15 11:00 [PATCH v2 0/3] arm64: dts: qcom: sm8450-hdk: add sound support Krzysztof Kozlowski @ 2022-11-15 11:00 ` Krzysztof Kozlowski 2022-11-15 11:02 ` Konrad Dybcio 2022-11-15 11:00 ` [PATCH v2 2/3] arm64: dts: qcom: sm8450: add Soundwire and LPASS Krzysztof Kozlowski 2022-11-15 11:00 ` [PATCH v2 3/3] arm64: dts: qcom: sm8450-hdk: add sound support Krzysztof Kozlowski 2 siblings, 1 reply; 7+ messages in thread From: Krzysztof Kozlowski @ 2022-11-15 11:00 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel Cc: Srinivas Kandagatla, Krzysztof Kozlowski From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Add Generic Packet Router (GPR) device node with ADSP services. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Co-developed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 40 ++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 46f9576f786f..4b0a1eee8bd9 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -13,6 +13,7 @@ #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/interconnect/qcom,sm8450.h> +#include <dt-bindings/soc/qcom,gpr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/thermal/thermal.h> @@ -2134,6 +2135,45 @@ IPCC_MPROC_SIGNAL_GLINK_QMP label = "lpass"; qcom,remote-pid = <2>; + gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "adsp_apps"; + qcom,domain = <GPR_DOMAIN_ID_ADSP>; + qcom,intents = <512 20>; + #address-cells = <1>; + #size-cells = <0>; + + q6apm: service@1 { + reg = <GPR_APM_MODULE_IID>; + compatible = "qcom,q6apm"; + #sound-dai-cells = <0>; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6apmdai: dais { + compatible = "qcom,q6apm-dais"; + iommus = <&apps_smmu 0x1801 0x0>; + }; + + q6apmbedai: bedais { + compatible = "qcom,q6apm-lpass-dais"; + #sound-dai-cells = <1>; + }; + }; + + q6prm: service@2 { + reg = <GPR_PRM_MODULE_IID>; + compatible = "qcom,q6prm"; + qcom,protection-domain = "avs/audio", + "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible = "qcom,q6prm-lpass-clocks"; + #clock-cells = <2>; + }; + }; + }; + fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 1/3] arm64: dts: qcom: sm8450: add GPR node 2022-11-15 11:00 ` [PATCH v2 1/3] arm64: dts: qcom: sm8450: add GPR node Krzysztof Kozlowski @ 2022-11-15 11:02 ` Konrad Dybcio 0 siblings, 0 replies; 7+ messages in thread From: Konrad Dybcio @ 2022-11-15 11:02 UTC (permalink / raw) To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel Cc: Srinivas Kandagatla On 15/11/2022 12:00, Krzysztof Kozlowski wrote: > From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> > > Add Generic Packet Router (GPR) device node with ADSP services. > > Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> > Co-developed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/sm8450.dtsi | 40 ++++++++++++++++++++++++++++ > 1 file changed, 40 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 46f9576f786f..4b0a1eee8bd9 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -13,6 +13,7 @@ > #include <dt-bindings/mailbox/qcom-ipcc.h> > #include <dt-bindings/power/qcom-rpmpd.h> > #include <dt-bindings/interconnect/qcom,sm8450.h> > +#include <dt-bindings/soc/qcom,gpr.h> > #include <dt-bindings/soc/qcom,rpmh-rsc.h> > #include <dt-bindings/thermal/thermal.h> > > @@ -2134,6 +2135,45 @@ IPCC_MPROC_SIGNAL_GLINK_QMP > label = "lpass"; > qcom,remote-pid = <2>; > > + gpr { > + compatible = "qcom,gpr"; > + qcom,glink-channels = "adsp_apps"; > + qcom,domain = <GPR_DOMAIN_ID_ADSP>; > + qcom,intents = <512 20>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + q6apm: service@1 { > + reg = <GPR_APM_MODULE_IID>; > + compatible = "qcom,q6apm"; > + #sound-dai-cells = <0>; > + qcom,protection-domain = "avs/audio", > + "msm/adsp/audio_pd"; > + > + q6apmdai: dais { > + compatible = "qcom,q6apm-dais"; > + iommus = <&apps_smmu 0x1801 0x0>; > + }; > + > + q6apmbedai: bedais { > + compatible = "qcom,q6apm-lpass-dais"; > + #sound-dai-cells = <1>; > + }; > + }; > + > + q6prm: service@2 { > + reg = <GPR_PRM_MODULE_IID>; > + compatible = "qcom,q6prm"; > + qcom,protection-domain = "avs/audio", > + "msm/adsp/audio_pd"; > + > + q6prmcc: clock-controller { > + compatible = "qcom,q6prm-lpass-clocks"; > + #clock-cells = <2>; > + }; > + }; > + }; > + > fastrpc { > compatible = "qcom,fastrpc"; > qcom,glink-channels = "fastrpcglink-apps-dsp"; ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 2/3] arm64: dts: qcom: sm8450: add Soundwire and LPASS 2022-11-15 11:00 [PATCH v2 0/3] arm64: dts: qcom: sm8450-hdk: add sound support Krzysztof Kozlowski 2022-11-15 11:00 ` [PATCH v2 1/3] arm64: dts: qcom: sm8450: add GPR node Krzysztof Kozlowski @ 2022-11-15 11:00 ` Krzysztof Kozlowski 2022-11-15 11:17 ` Konrad Dybcio 2022-11-15 11:00 ` [PATCH v2 3/3] arm64: dts: qcom: sm8450-hdk: add sound support Krzysztof Kozlowski 2 siblings, 1 reply; 7+ messages in thread From: Krzysztof Kozlowski @ 2022-11-15 11:00 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel Cc: Srinivas Kandagatla, Krzysztof Kozlowski From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Add Soundwire controllers, Low Power Audio SubSystem (LPASS) devices and LPASS pin controller. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Co-developed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Changes since v1: 1. Whitespace cleanups. 2. Correct include - do not use deprecated one. --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 295 +++++++++++++++++++++++++++ 1 file changed, 295 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 4b0a1eee8bd9..e80a7d09646f 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -15,6 +15,7 @@ #include <dt-bindings/interconnect/qcom,sm8450.h> #include <dt-bindings/soc/qcom,gpr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> #include <dt-bindings/thermal/thermal.h> / { @@ -2097,6 +2098,212 @@ compute-cb@3 { }; }; + wsa2macro: codec@31e0000 { + compatible = "qcom,sm8450-lpass-wsa-macro"; + reg = <0 0x031e0000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clock-rates = <19200000>, <19200000>; + + #clock-cells = <0>; + clock-output-names = "wsa2-mclk"; + #sound-dai-cells = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&wsa2_swr_active>; + }; + + /* WSA2 */ + swr4: soundwire-controller@31f0000 { + reg = <0 0x031f0000 0 0x2000>; + compatible = "qcom,soundwire-v1.7.0"; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&wsa2macro>; + clock-names = "iface"; + + qcom,din-ports = <2>; + qcom,dout-ports = <6>; + + qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; + qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; + qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; + qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0x01 0xFF 0xFF 0x01 0xFF 0xFF>; + qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; + qcom,ports-lane-control = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; + + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + }; + + rxmacro: codec@3200000 { + compatible = "qcom,sm8450-lpass-rx-macro"; + reg = <0 0x3200000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + + assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clock-rates = <19200000>, <19200000>; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&rx_swr_active>; + }; + + swr1: soundwire-controller@3210000 { + reg = <0 0x3210000 0 0x2000>; + compatible = "qcom,soundwire-v1.7.0"; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rxmacro>; + clock-names = "iface"; + label = "RX"; + qcom,din-ports = <0>; + qcom,dout-ports = <5>; + + qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>; + qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>; + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>; + qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>; + qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; + qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>; + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + }; + + txmacro: codec@3220000 { + compatible = "qcom,sm8450-lpass-tx-macro"; + reg = <0 0x3220000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clock-rates = <19200000>, <19200000>; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&tx_swr_active>; + }; + + wsamacro: codec@3240000 { + compatible = "qcom,sm8450-lpass-wsa-macro"; + reg = <0 0x03240000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&vamacro>; + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + + assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clock-rates = <19200000>, <19200000>; + + #clock-cells = <0>; + clock-output-names = "mclk"; + #sound-dai-cells = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&wsa_swr_active>; + }; + + /* WSA */ + swr0: soundwire-controller@3250000 { + reg = <0 0x03250000 0 0x2000>; + compatible = "qcom,soundwire-v1.7.0"; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&wsamacro>; + clock-names = "iface"; + + qcom,din-ports = <2>; + qcom,dout-ports = <6>; + + qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; + qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; + qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; + qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; + qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; + qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; + qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0x01 0xFF 0xFF 0x01 0xFF 0xFF>; + qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; + qcom,ports-lane-control = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; + qcom,port-offset = <1>; + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + }; + + swr2: soundwire-controller@33b0000 { + reg = <0 0x33b0000 0 0x2000>; + compatible = "qcom,soundwire-v1.7.0"; + interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "core", "wake"; + + clocks = <&vamacro>; + clock-names = "iface"; + label = "TX"; + + qcom,din-ports = <4>; + qcom,dout-ports = <0>; + qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; + qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF>; + qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF>; + qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF>; + qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF>; + qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF>; + qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; + qcom,port-offset = <1>; + #sound-dai-cells = <1>; + #address-cells = <2>; + #size-cells = <0>; + }; + + vamacro: codec@33f0000 { + compatible = "qcom,sm8450-lpass-va-macro"; + reg = <0 0x033f0000 0 0x1000>; + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "mclk", "macro", "dcodec", "npl"; + assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + assigned-clock-rates = <19200000>; + + #clock-cells = <0>; + clock-output-names = "fsgen"; + #sound-dai-cells = <1>; + }; + remoteproc_adsp: remoteproc@30000000 { compatible = "qcom,sm8450-adsp-pas"; reg = <0 0x030000000 0 0x100>; @@ -3030,6 +3237,91 @@ qup_uart20_default: qup-uart20-default-state { }; + lpass_tlmm: pinctrl@3440000{ + compatible = "qcom,sm8450-lpass-lpi-pinctrl"; + reg = <0 0x3440000 0x0 0x20000>, + <0 0x34d0000 0x0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + wsa_swr_active: wsa-swr-active-state { + clk-pins { + pins = "gpio10"; + function = "wsa_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio11"; + function = "wsa_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + tx_swr_active: tx-swr-active-state { + clk-pins { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio1", "gpio2", "gpio14"; + function = "swr_tx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + rx_swr_active: rx-swr-active-state { + clk-pins { + pins = "gpio3"; + function = "swr_rx_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio4", "gpio5"; + function = "swr_rx_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + + wsa2_swr_active: wsa2-swr-active-state { + clk-pins { + pins = "gpio15"; + function = "wsa2_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio16"; + function = "wsa2_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + bias-bus-hold; + }; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; @@ -3507,6 +3799,9 @@ lpass_ag_noc: interconnect@3c40000 { }; }; + sound: sound { + }; + thermal-zones { aoss0-thermal { polling-delay-passive = <0>; -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: qcom: sm8450: add Soundwire and LPASS 2022-11-15 11:00 ` [PATCH v2 2/3] arm64: dts: qcom: sm8450: add Soundwire and LPASS Krzysztof Kozlowski @ 2022-11-15 11:17 ` Konrad Dybcio 2022-11-15 11:19 ` Krzysztof Kozlowski 0 siblings, 1 reply; 7+ messages in thread From: Konrad Dybcio @ 2022-11-15 11:17 UTC (permalink / raw) To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel Cc: Srinivas Kandagatla On 15/11/2022 12:00, Krzysztof Kozlowski wrote: > From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> > > Add Soundwire controllers, Low Power Audio SubSystem (LPASS) devices and > LPASS pin controller. > > Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> > Co-developed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > --- > > Changes since v1: > 1. Whitespace cleanups. > 2. Correct include - do not use deprecated one. > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 295 +++++++++++++++++++++++++++ > 1 file changed, 295 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 4b0a1eee8bd9..e80a7d09646f 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -15,6 +15,7 @@ > #include <dt-bindings/interconnect/qcom,sm8450.h> > #include <dt-bindings/soc/qcom,gpr.h> > #include <dt-bindings/soc/qcom,rpmh-rsc.h> > +#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> > #include <dt-bindings/thermal/thermal.h> > > / { > @@ -2097,6 +2098,212 @@ compute-cb@3 { > }; > }; > > + wsa2macro: codec@31e0000 { > + compatible = "qcom,sm8450-lpass-wsa-macro"; > + reg = <0 0x031e0000 0 0x1000>; > + clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&vamacro>; > + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; > + assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; > + assigned-clock-rates = <19200000>, <19200000>; > + > + #clock-cells = <0>; > + clock-output-names = "wsa2-mclk"; > + #sound-dai-cells = <1>; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&wsa2_swr_active>; > + }; > + > + /* WSA2 */ > + swr4: soundwire-controller@31f0000 { > + reg = <0 0x031f0000 0 0x2000>; > + compatible = "qcom,soundwire-v1.7.0"; > + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&wsa2macro>; > + clock-names = "iface"; > + > + qcom,din-ports = <2>; > + qcom,dout-ports = <6>; > + > + qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; > + qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; > + qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; > + qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; > + qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; > + qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; > + qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0x01 0xFF 0xFF 0x01 0xFF 0xFF>; > + qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; > + qcom,ports-lane-control = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; You didn't normalize the constants to be all-uppercase or all-lowercase. I think lowercase is what's generally used in DTs. The rest looks good though. Konrad > + > + #sound-dai-cells = <1>; > + #address-cells = <2>; > + #size-cells = <0>; > + }; > + > + rxmacro: codec@3200000 { > + compatible = "qcom,sm8450-lpass-rx-macro"; > + reg = <0 0x3200000 0 0x1000>; > + clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&vamacro>; > + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; > + > + assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; > + assigned-clock-rates = <19200000>, <19200000>; > + > + #clock-cells = <0>; > + clock-output-names = "mclk"; > + #sound-dai-cells = <1>; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&rx_swr_active>; > + }; > + > + swr1: soundwire-controller@3210000 { > + reg = <0 0x3210000 0 0x2000>; > + compatible = "qcom,soundwire-v1.7.0"; > + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&rxmacro>; > + clock-names = "iface"; > + label = "RX"; > + qcom,din-ports = <0>; > + qcom,dout-ports = <5>; > + > + qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1F 0x1F 0x07 0x00>; > + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; > + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; > + qcom,ports-hstart = /bits/ 8 <0xFF 0x03 0xFF 0xFF 0xFF>; > + qcom,ports-hstop = /bits/ 8 <0xFF 0x06 0xFF 0xFF 0xFF>; > + qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xFF 0xFF>; > + qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0x00 0x01 0xFF 0xFF>; > + qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; > + qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0x00>; > + #sound-dai-cells = <1>; > + #address-cells = <2>; > + #size-cells = <0>; > + }; > + > + txmacro: codec@3220000 { > + compatible = "qcom,sm8450-lpass-tx-macro"; > + reg = <0 0x3220000 0 0x1000>; > + clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&vamacro>; > + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; > + assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; > + assigned-clock-rates = <19200000>, <19200000>; > + > + #clock-cells = <0>; > + clock-output-names = "mclk"; > + #sound-dai-cells = <1>; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&tx_swr_active>; > + }; > + > + wsamacro: codec@3240000 { > + compatible = "qcom,sm8450-lpass-wsa-macro"; > + reg = <0 0x03240000 0 0x1000>; > + clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&vamacro>; > + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; > + > + assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; > + assigned-clock-rates = <19200000>, <19200000>; > + > + #clock-cells = <0>; > + clock-output-names = "mclk"; > + #sound-dai-cells = <1>; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&wsa_swr_active>; > + }; > + > + /* WSA */ > + swr0: soundwire-controller@3250000 { > + reg = <0 0x03250000 0 0x2000>; > + compatible = "qcom,soundwire-v1.7.0"; > + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&wsamacro>; > + clock-names = "iface"; > + > + qcom,din-ports = <2>; > + qcom,dout-ports = <6>; > + > + qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; > + qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; > + qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; > + qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; > + qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; > + qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; > + qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0x01 0xFF 0xFF 0x01 0xFF 0xFF>; > + qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; > + qcom,ports-lane-control = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; > + qcom,port-offset = <1>; > + #sound-dai-cells = <1>; > + #address-cells = <2>; > + #size-cells = <0>; > + }; > + > + swr2: soundwire-controller@33b0000 { > + reg = <0 0x33b0000 0 0x2000>; > + compatible = "qcom,soundwire-v1.7.0"; > + interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "core", "wake"; > + > + clocks = <&vamacro>; > + clock-names = "iface"; > + label = "TX"; > + > + qcom,din-ports = <4>; > + qcom,dout-ports = <0>; > + qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; > + qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; > + qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; > + qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0xFF 0xFF>; > + qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF>; > + qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF>; > + qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF>; > + qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF>; > + qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; > + qcom,port-offset = <1>; > + #sound-dai-cells = <1>; > + #address-cells = <2>; > + #size-cells = <0>; > + }; > + > + vamacro: codec@33f0000 { > + compatible = "qcom,sm8450-lpass-va-macro"; > + reg = <0 0x033f0000 0 0x1000>; > + clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; > + clock-names = "mclk", "macro", "dcodec", "npl"; > + assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; > + assigned-clock-rates = <19200000>; > + > + #clock-cells = <0>; > + clock-output-names = "fsgen"; > + #sound-dai-cells = <1>; > + }; > + > remoteproc_adsp: remoteproc@30000000 { > compatible = "qcom,sm8450-adsp-pas"; > reg = <0 0x030000000 0 0x100>; > @@ -3030,6 +3237,91 @@ qup_uart20_default: qup-uart20-default-state { > > }; > > + lpass_tlmm: pinctrl@3440000{ > + compatible = "qcom,sm8450-lpass-lpi-pinctrl"; > + reg = <0 0x3440000 0x0 0x20000>, > + <0 0x34d0000 0x0 0x10000>; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&lpass_tlmm 0 0 23>; > + > + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, > + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; > + clock-names = "core", "audio"; > + > + wsa_swr_active: wsa-swr-active-state { > + clk-pins { > + pins = "gpio10"; > + function = "wsa_swr_clk"; > + drive-strength = <2>; > + slew-rate = <1>; > + bias-disable; > + }; > + > + data-pins { > + pins = "gpio11"; > + function = "wsa_swr_data"; > + drive-strength = <2>; > + slew-rate = <1>; > + bias-bus-hold; > + }; > + }; > + > + tx_swr_active: tx-swr-active-state { > + clk-pins { > + pins = "gpio0"; > + function = "swr_tx_clk"; > + drive-strength = <2>; > + slew-rate = <1>; > + bias-disable; > + }; > + > + data-pins { > + pins = "gpio1", "gpio2", "gpio14"; > + function = "swr_tx_data"; > + drive-strength = <2>; > + slew-rate = <1>; > + bias-bus-hold; > + }; > + }; > + > + rx_swr_active: rx-swr-active-state { > + clk-pins { > + pins = "gpio3"; > + function = "swr_rx_clk"; > + drive-strength = <2>; > + slew-rate = <1>; > + bias-disable; > + }; > + > + data-pins { > + pins = "gpio4", "gpio5"; > + function = "swr_rx_data"; > + drive-strength = <2>; > + slew-rate = <1>; > + bias-bus-hold; > + }; > + }; > + > + wsa2_swr_active: wsa2-swr-active-state { > + clk-pins { > + pins = "gpio15"; > + function = "wsa2_swr_clk"; > + drive-strength = <2>; > + slew-rate = <1>; > + bias-disable; > + }; > + > + data-pins { > + pins = "gpio16"; > + function = "wsa2_swr_data"; > + drive-strength = <2>; > + slew-rate = <1>; > + bias-bus-hold; > + }; > + }; > + }; > + > apps_smmu: iommu@15000000 { > compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; > reg = <0 0x15000000 0 0x100000>; > @@ -3507,6 +3799,9 @@ lpass_ag_noc: interconnect@3c40000 { > }; > }; > > + sound: sound { > + }; > + > thermal-zones { > aoss0-thermal { > polling-delay-passive = <0>; ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 2/3] arm64: dts: qcom: sm8450: add Soundwire and LPASS 2022-11-15 11:17 ` Konrad Dybcio @ 2022-11-15 11:19 ` Krzysztof Kozlowski 0 siblings, 0 replies; 7+ messages in thread From: Krzysztof Kozlowski @ 2022-11-15 11:19 UTC (permalink / raw) To: Konrad Dybcio, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel Cc: Srinivas Kandagatla On 15/11/2022 12:17, Konrad Dybcio wrote: > > > On 15/11/2022 12:00, Krzysztof Kozlowski wrote: >> From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> >> >> Add Soundwire controllers, Low Power Audio SubSystem (LPASS) devices and >> LPASS pin controller. >> >> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> >> Co-developed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> >> >> --- >> >> Changes since v1: >> 1. Whitespace cleanups. >> 2. Correct include - do not use deprecated one. >> --- >> arch/arm64/boot/dts/qcom/sm8450.dtsi | 295 +++++++++++++++++++++++++++ >> 1 file changed, 295 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi >> index 4b0a1eee8bd9..e80a7d09646f 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi >> @@ -15,6 +15,7 @@ >> #include <dt-bindings/interconnect/qcom,sm8450.h> >> #include <dt-bindings/soc/qcom,gpr.h> >> #include <dt-bindings/soc/qcom,rpmh-rsc.h> >> +#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> >> #include <dt-bindings/thermal/thermal.h> >> >> / { >> @@ -2097,6 +2098,212 @@ compute-cb@3 { >> }; >> }; >> >> + wsa2macro: codec@31e0000 { >> + compatible = "qcom,sm8450-lpass-wsa-macro"; >> + reg = <0 0x031e0000 0 0x1000>; >> + clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, >> + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, >> + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, >> + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, >> + <&vamacro>; >> + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; >> + assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, >> + <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; >> + assigned-clock-rates = <19200000>, <19200000>; >> + >> + #clock-cells = <0>; >> + clock-output-names = "wsa2-mclk"; >> + #sound-dai-cells = <1>; >> + >> + pinctrl-names = "default"; >> + pinctrl-0 = <&wsa2_swr_active>; >> + }; >> + >> + /* WSA2 */ >> + swr4: soundwire-controller@31f0000 { >> + reg = <0 0x031f0000 0 0x2000>; >> + compatible = "qcom,soundwire-v1.7.0"; >> + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&wsa2macro>; >> + clock-names = "iface"; >> + >> + qcom,din-ports = <2>; >> + qcom,dout-ports = <6>; >> + >> + qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; >> + qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; >> + qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; >> + qcom,ports-hstart = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; >> + qcom,ports-hstop = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; >> + qcom,ports-word-length = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; >> + qcom,ports-block-pack-mode = /bits/ 8 <0xFF 0xFF 0x01 0xFF 0xFF 0x01 0xFF 0xFF>; >> + qcom,ports-block-group-count = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; >> + qcom,ports-lane-control = /bits/ 8 <0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF>; > You didn't normalize the constants to be all-uppercase or all-lowercase. > I think lowercase is what's generally used in DTs. > > The rest looks good though. Uh, yeah, you said it last time. Sorry, I missed to implement it. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 3/3] arm64: dts: qcom: sm8450-hdk: add sound support 2022-11-15 11:00 [PATCH v2 0/3] arm64: dts: qcom: sm8450-hdk: add sound support Krzysztof Kozlowski 2022-11-15 11:00 ` [PATCH v2 1/3] arm64: dts: qcom: sm8450: add GPR node Krzysztof Kozlowski 2022-11-15 11:00 ` [PATCH v2 2/3] arm64: dts: qcom: sm8450: add Soundwire and LPASS Krzysztof Kozlowski @ 2022-11-15 11:00 ` Krzysztof Kozlowski 2 siblings, 0 replies; 7+ messages in thread From: Krzysztof Kozlowski @ 2022-11-15 11:00 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel Cc: Srinivas Kandagatla, Krzysztof Kozlowski From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Add sound support to SM8450 HDK board. Tested setup so far is only two speakers (working) and head-phones (only one channel working). Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Co-developed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- Changes since v1: 1. Sort. 2. Correct include - do not use deprecated one and drop q6asm.h (not used). --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 160 ++++++++++++++++++++++++ 1 file changed, 160 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 4d75f9db08c2..baff71c0c680 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -6,6 +6,7 @@ /dts-v1/; #include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> #include "sm8450.dtsi" / { @@ -406,6 +407,147 @@ &sdhc_2 { status = "okay"; }; +&soc { + wcd938x: codec { + compatible = "qcom,wcd9380-codec"; + + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,micbias4-microvolt = <1800000>; + qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>; + qcom,mbhc-headset-vthreshold-microvolt = <1700000>; + qcom,mbhc-headphone-vthreshold-microvolt = <50000>; + qcom,rx-device = <&wcd_rx>; + qcom,tx-device = <&wcd_tx>; + + reset-gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <1>; + + vdd-buck-supply = <&vreg_s10b_1p8>; + vdd-rxtx-supply = <&vreg_s10b_1p8>; + vdd-io-supply = <&vreg_s10b_1p8>; + vdd-mic-bias-supply = <&vreg_bob>; + }; +}; + +&sound { + compatible = "qcom,sm8450-sndcard"; + model = "SM8450-HDK"; + audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC1", "MIC BIAS1", + "AMIC2", "MIC BIAS2", + "AMIC3", "MIC BIAS3", + "AMIC4", "MIC BIAS3", + "AMIC5", "MIC BIAS4"; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wcd-playback-dai-link { + link-name = "WCD Playback"; + cpu { + sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&wcd938x 0>, <&swr1 0>, <&rxmacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + wsa-dai-link { + link-name = "WSA Playback"; + cpu { + sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + codec { + sound-dai = <&left_spkr>, <&right_spkr>, <&swr0 0>, <&wsamacro 0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + va-dai-link { + link-name = "VA Capture"; + cpu { + sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; +}; + +&swr0 { + right_spkr: speaker@0,1{ + compatible = "sdw10217020200"; + reg = <0 1>; + pinctrl-names = "default"; + pinctrl-0 = <&spkr_1_sd_n_active>; + powerdown-gpios = <&tlmm 1 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrRight"; + #thermal-sensor-cells = <0>; + vdd-supply = <&vreg_s10b_1p8>; + }; + + left_spkr: speaker@0,2{ + compatible = "sdw10217020200"; + reg = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&spkr_2_sd_n_active>; + powerdown-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + sound-name-prefix = "SpkrLeft"; + #thermal-sensor-cells = <0>; + vdd-supply = <&vreg_s10b_1p8>; + }; +}; + +&swr1 { + status = "okay"; + + wcd_rx: codec@0,4 { + compatible = "sdw20217010d00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 2 3 4 5>; + }; +}; + +&swr2 { + status = "okay"; + + wcd_tx: codec@0,3 { + compatible = "sdw20217010d00"; + reg = <0 3>; + /* ports: adc1_2, adc3_4, dmic0_3_mbhc, dmic4_7 */ + qcom,tx-port-mapping = <1 1 2 3>; + }; +}; + &tlmm { gpio-reserved-ranges = <28 4>, <36 4>; @@ -461,3 +603,21 @@ &usb_1_qmpphy { vdda-phy-supply = <&vreg_l6b_1p2>; vdda-pll-supply = <&vreg_l1b_0p91>; }; + +&tlmm { + spkr_1_sd_n_active: spkr-1-sd-n-active-state { + pins = "gpio1"; + function = "gpio"; + drive-strength = <4>; + bias-disable; + output-low; + }; + + spkr_2_sd_n_active: spkr-2-sd-n-active-state { + pins = "gpio89"; + function = "gpio"; + drive-strength = <4>; + bias-disable; + output-low; + }; +}; -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-11-15 11:20 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-11-15 11:00 [PATCH v2 0/3] arm64: dts: qcom: sm8450-hdk: add sound support Krzysztof Kozlowski 2022-11-15 11:00 ` [PATCH v2 1/3] arm64: dts: qcom: sm8450: add GPR node Krzysztof Kozlowski 2022-11-15 11:02 ` Konrad Dybcio 2022-11-15 11:00 ` [PATCH v2 2/3] arm64: dts: qcom: sm8450: add Soundwire and LPASS Krzysztof Kozlowski 2022-11-15 11:17 ` Konrad Dybcio 2022-11-15 11:19 ` Krzysztof Kozlowski 2022-11-15 11:00 ` [PATCH v2 3/3] arm64: dts: qcom: sm8450-hdk: add sound support Krzysztof Kozlowski
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