[PATCH v2 1/8] drm/msm/dpu: Wire up DSC mask for active CTL configuration

From: Marijn Suijten <marijn.suijten@somainline.org>
To: phone-devel@vger.kernel.org, Rob Clark <robdclark@gmail.com>,
	Abhinav Kumar <quic_abhinavk@quicinc.com>,
	Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
	Vinod Koul <vkoul@kernel.org>
Cc: ~postmarketos/upstreaming@lists.sr.ht,
	"AngeloGioacchino Del Regno"
	<angelogioacchino.delregno@somainline.org>,
	"Konrad Dybcio" <konrad.dybcio@somainline.org>,
	"Martin Botka" <martin.botka@somainline.org>,
	"Jami Kettunen" <jami.kettunen@somainline.org>,
	"Marijn Suijten" <marijn.suijten@somainline.org>,
	"Sean Paul" <sean@poorly.run>, "David Airlie" <airlied@gmail.com>,
	"Daniel Vetter" <daniel@ffwll.ch>,
	"Stephen Boyd" <swboyd@chromium.org>,
	"Bjorn Andersson" <andersson@kernel.org>,
	"Jessica Zhang" <quic_jesszhan@quicinc.com>,
	"Ville Syrjälä" <ville.syrjala@linux.intel.com>,
	"Kuogee Hsieh" <quic_khsieh@quicinc.com>,
	"Jani Nikula" <jani.nikula@intel.com>,
	sunliming <sunliming@kylinos.cn>,
	"Sam Ravnborg" <sam@ravnborg.org>,
	"Haowen Bai" <baihaowen@meizu.com>,
	"Konrad Dybcio" <konrad.dybcio@linaro.org>,
	"Loic Poulain" <loic.poulain@linaro.org>,
	"Vinod Polimera" <quic_vpolimer@quicinc.com>,
	"Douglas Anderson" <dianders@chromium.org>,
	"Vladimir Lypak" <vladimir.lypak@gmail.com>,
	linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
	freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org
Subject: [PATCH v2 1/8] drm/msm/dpu: Wire up DSC mask for active CTL configuration
Date: Thu, 22 Dec 2022 00:19:36 +0100	[thread overview]
Message-ID: <20221221231943.1961117-2-marijn.suijten@somainline.org> (raw)
In-Reply-To: <20221221231943.1961117-1-marijn.suijten@somainline.org>

Active CTLs have to configure what DSC block(s) have to be enabled, and
what DSC block(s) have to be flushed; this value was initialized to zero
resulting in the necessary register writes to never happen (or would
write zero otherwise).  This seems to have gotten lost in the DSC v4->v5
series while refactoring how the combination with merge_3d was handled.

Fixes: 58dca9810749 ("drm/msm/disp/dpu1: Add support for DSC in encoder")
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 1 +
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index ae28b2b93e69..35791f93c33d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -61,6 +61,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
 	intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD;
 	intf_cfg.stream_sel = cmd_enc->stream_sel;
 	intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
+	intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
 	ctl->ops.setup_intf_cfg(ctl, &intf_cfg);
 
 	/* setup which pp blk will connect to this intf */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index 0f71e8fe7be7..9ee3a7306a5f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -274,6 +274,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
 	intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID;
 	intf_cfg.stream_sel = 0; /* Don't care value for video mode */
 	intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
+	intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
 	if (phys_enc->hw_pp->merge_3d)
 		intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
 
-- 
2.39.0

