From: Stephen Boyd <swboyd@chromium.org>
To: Lina Iyer <ilina@codeaurora.org>
Cc: Rob Herring <robh@kernel.org>,
evgreen@chromium.org, linus.walleij@linaro.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
bjorn.andersson@linaro.org, mkshah@codeaurora.org,
linux-gpio@vger.kernel.org, rnayak@codeaurora.org,
devicetree@vger.kernel.org, maz@kernel.org, sibis@codeaurora.org
Subject: Re: [PATCH RFC 05/14] dt-bindings/interrupt-controller: pdc: add SPI config register
Date: Fri, 20 Sep 2019 15:20:25 -0700 [thread overview]
Message-ID: <5d8550aa.1c69fb81.39edc.83fc@mx.google.com> (raw)
In-Reply-To: <20190917215020.GA15853@codeaurora.org>
Quoting Lina Iyer (2019-09-17 14:50:20)
> On Fri, Sep 13 2019 at 13:53 -0600, Lina Iyer wrote:
> >On Thu, Sep 05 2019 at 18:03 -0600, Stephen Boyd wrote:
> >>Quoting Lina Iyer (2019-09-03 10:07:22)
> >>>On Mon, Sep 02 2019 at 07:58 -0600, Marc Zyngier wrote:
> >>>>On 02/09/2019 14:38, Rob Herring wrote:
> >>>>> On Thu, Aug 29, 2019 at 12:11:54PM -0600, Lina Iyer wrote:
> >>>These are not GIC registers but located on the PDC interface to the GIC.
> >>>They may or may not be secure access controlled, depending on the SoC.
> >>>
> >>
> >>It looks like it falls under this "mailbox" device which is really the
> >>catch all bucket for bits with no home besides they're related to the
> >>apps CPUs/subsystem.
> >>
> >Thanks for pointing to this.
> >> apss_shared: mailbox@17990000 {
> >> compatible = "qcom,sdm845-apss-shared";
> >> reg = <0 0x17990000 0 0x1000>;
> >But this doesn't seem correct. The registers in this page are all not
> >mailbox door bell registers. We should restrict the space allocated to
> >the mbox to 0xC or something, definitely, not the whole page. They all
> >cannot be treated as a mailbox registers.
Well the binding is already done and this is the compatible string for
this node and register region. Sounds like this node is a mailbox plus
some more stuff in the same page.
> >> #mbox-cells = <1>;
> >> };
> >>
> >>Can you point to this node with a phandle and then parse the reg
> >>property out of it to use in the scm readl/writel APIs? Maybe it can be
> >>a two cell property with <&apps_shared 0xf0> to indicate the offset to
> >>the registers to read/write? In non-secure mode presumably we need to
> >>also write these registers? Good news is that there's a regmap for this
> >>driver already, so maybe that can be acquired from the pdc driver.
> >>
> >The register space collection seems to be mix of different types of
> >application processor registers that should probably not be grouped up
> >under one subsystem. A single regmap doesn't seem correct either.
Why isn't a single regmap correct? The PDC driver should be able to use
it to read/write into this register space. The lock on the regmap will
need to be changed to a raw lock though for RT. Otherwise it looks OK to
me.
next prev parent reply other threads:[~2019-09-20 22:20 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-29 18:11 [PATCH RFC 00/14] qcom: support wakeup capable GPIOs Lina Iyer
2019-08-29 18:11 ` [PATCH RFC 01/14] irqdomain: add bus token DOMAIN_BUS_WAKEUP Lina Iyer
2019-08-29 18:11 ` [PATCH RFC 02/14] drivers: irqchip: pdc: Do not toggle IRQ_ENABLE during mask/unmask Lina Iyer
2019-09-06 0:39 ` Stephen Boyd
2019-09-11 16:15 ` Lina Iyer
2019-09-20 22:22 ` Stephen Boyd
2019-09-20 22:31 ` Lina Iyer
2019-08-29 18:11 ` [PATCH RFC 03/14] drivers: irqchip: add PDC irqdomain for wakeup capable GPIOs Lina Iyer
2019-08-30 14:50 ` Marc Zyngier
2019-08-30 15:58 ` Lina Iyer
2019-09-02 8:21 ` Marc Zyngier
2019-09-03 22:51 ` Stephen Boyd
2019-08-29 18:11 ` [PATCH RFC 04/14] of: irq: document properties for wakeup interrupt parent Lina Iyer
2019-09-02 13:38 ` Rob Herring
2019-08-29 18:11 ` [PATCH RFC 05/14] dt-bindings/interrupt-controller: pdc: add SPI config register Lina Iyer
2019-09-02 13:38 ` Rob Herring
2019-09-02 13:53 ` Marc Zyngier
2019-09-03 17:07 ` Lina Iyer
2019-09-06 0:03 ` Stephen Boyd
2019-09-13 19:53 ` Lina Iyer
2019-09-17 21:50 ` Lina Iyer
2019-09-20 22:20 ` Stephen Boyd [this message]
2019-09-23 6:11 ` Sibi Sankar
[not found] ` <CACRpkdaReFzjb_hcDbQwqMX+whzscLpeZpJPHKqOo+9tANzemA@mail.gmail.com>
2019-09-11 15:19 ` Lina Iyer
2019-08-29 18:11 ` [PATCH RFC 06/14] drivers: irqchip: pdc: additionally set type in SPI config registers Lina Iyer
2019-09-06 0:22 ` Stephen Boyd
2019-08-29 18:11 ` [PATCH RFC 07/14] genirq: Introduce irq_chip_get/set_parent_state calls Lina Iyer
2019-09-06 0:35 ` Stephen Boyd
2019-08-29 18:11 ` [PATCH RFC 08/14] drivers: irqchip: pdc: Add irqchip set/get state calls Lina Iyer
2019-09-06 0:09 ` Stephen Boyd
2019-08-29 18:11 ` [PATCH RFC 09/14] drivers: pinctrl: msm: fix use of deprecated gpiolib APIs Lina Iyer
2019-09-06 0:11 ` Stephen Boyd
2019-09-11 10:19 ` Linus Walleij
2019-09-11 16:16 ` Lina Iyer
2019-08-29 18:11 ` [PATCH RFC 10/14] drivers: pinctrl: msm: setup GPIO chip in hierarchy Lina Iyer
2019-08-29 18:12 ` [PATCH RFC 11/14] drivers: pinctrl: sdm845: add PDC wakeup interrupt map for GPIOs Lina Iyer
2019-09-06 0:24 ` Stephen Boyd
2019-08-29 18:12 ` [PATCH RFC 12/14] arm64: dts: qcom: add PDC interrupt controller for SDM845 Lina Iyer
2019-09-09 11:26 ` Maulik Shah
2019-08-29 18:12 ` [PATCH RFC 13/14] arm64: dts: qcom: setup PDC as the wakeup parent for TLMM on SDM845 Lina Iyer
2019-08-29 18:12 ` [PATCH RFC 14/14] arm64: defconfig: enable PDC interrupt controller for Qualcomm SDM845 Lina Iyer
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