From: Marc Gonzalez <marc.w.gonzalez@free.fr>
To: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Cc: MSM <linux-arm-msm@vger.kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: Relax CPU features sanity checking on heterogeneous architectures
Date: Fri, 11 Oct 2019 11:19:33 +0200 [thread overview]
Message-ID: <7ef16e2a-b35c-0807-67be-c56dadb6fa66@free.fr> (raw)
In-Reply-To: <b3606e76af42f7ecf65b1bfc2a5ed30a@codeaurora.org>
On 11/10/2019 07:49, Sai Prakash Ranjan wrote:
> diff --git a/arch/arm64/kernel/cpufeature.c
> b/arch/arm64/kernel/cpufeature.c
> index cabebf1a7976..207197692caa 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -164,8 +164,8 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[]
> = {
> S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
> ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
> /* Linux doesn't care about the EL3 */
> ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
> ID_AA64PFR0_EL3_SHIFT, 4, 0),
> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE,
> ID_AA64PFR0_EL2_SHIFT, 4, 0),
> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE,
> ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
> ID_AA64PFR0_EL2_SHIFT, 4, 0),
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
> ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE,
> ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
> ARM64_FTR_END,
> };
> @@ -345,10 +345,10 @@ static const struct arm64_ftr_bits
> ftr_generic_32bits[] = {
> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4,
> 0),
> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4,
> 0),
> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4,
> 0),
> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4,
> 0),
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 12, 4,
> 0),
> ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
> - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 4, 4,
> 0),
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 0, 4,
> 0),
> ARM64_FTR_END,
> };
Hello Sai,
Could you configure your webmail client to not wrap "long" lines?
Wrapping might break the patch, and the kernel logs would look better
in their original form.
Regards.
next prev parent reply other threads:[~2019-10-11 9:19 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-11 5:49 Relax CPU features sanity checking on heterogeneous architectures Sai Prakash Ranjan
2019-10-11 9:19 ` Marc Gonzalez [this message]
2019-10-11 9:57 ` Sai Prakash Ranjan
2019-10-11 10:50 ` Mark Rutland
2019-10-11 11:09 ` Marc Gonzalez
2019-10-11 13:33 ` Sai Prakash Ranjan
2019-10-11 13:17 ` Sai Prakash Ranjan
2019-10-11 13:34 ` Marc Zyngier
2019-10-11 13:40 ` Sai Prakash Ranjan
2019-10-17 20:00 ` Stephen Boyd
2019-10-18 7:20 ` Marc Zyngier
2019-10-18 14:33 ` Stephen Boyd
2019-10-18 16:40 ` Marc Zyngier
2019-10-18 10:18 ` Sai Prakash Ranjan
2019-10-11 13:33 ` Marc Zyngier
2019-10-11 13:54 ` Mark Rutland
2019-10-11 14:06 ` Marc Zyngier
2019-10-17 21:39 ` Jeremy Linton
2019-10-18 9:01 ` Catalin Marinas
2020-01-20 2:47 ` Sai Prakash Ranjan
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