Re: Relax CPU features sanity checking on heterogeneous architectures

From: Marc Zyngier <maz@kernel.org>
To: Stephen Boyd <swboyd@chromium.org>
Cc: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>,
	Mark Rutland <mark.rutland@arm.com>, <rnayak@codeaurora.org>,
	<suzuki.poulose@arm.com>, <catalin.marinas@arm.com>,
	linux-arm-kernel <linux-arm-kernel-bounces@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <jeremy.linton@arm.com>,
	<bjorn.andersson@linaro.org>, <linux-arm-msm@vger.kernel.org>,
	<andrew.murray@arm.com>, <will@kernel.org>, <dave.martin@arm.com>,
	<linux-arm-kernel@lists.infradead.org>, <marc.w.gonzalez@free.fr>
Subject: Re: Relax CPU features sanity checking on heterogeneous architectures
Date: Fri, 18 Oct 2019 08:20:56 +0100	[thread overview]
Message-ID: <c9285391dbbe936d3f242bdd0d226b93@www.loen.fr> (raw)
In-Reply-To: <5da8c868.1c69fb81.ae709.97ff@mx.google.com>

On 2019-10-17 21:00, Stephen Boyd wrote:
> Quoting Sai Prakash Ranjan (2019-10-11 06:40:13)
>> On 2019-10-11 19:04, Marc Zyngier wrote:
>> > On Fri, 11 Oct 2019 18:47:39 +0530
>> > Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> wrote:
>> >
>> >> Hi Mark,
>> >>
>> >> Thanks a lot for the detailed explanations, I did have a look at 
>> all
>> >> the variations before posting this.
>> >>
>> >> On 2019-10-11 16:20, Mark Rutland wrote:
>> >> > Hi,
>> >> >
>> >> > On Fri, Oct 11, 2019 at 11:19:00AM +0530, Sai Prakash Ranjan 
>> wrote:
>> >> >> On latest QCOM SoCs like SM8150 and SC7180 with big.LITTLE 
>> arch, below
>> >> >> warnings are observed during bootup of big cpu cores.
>> >> >
>> >> > For reference, which CPUs are in those SoCs?
>> >> >
>> >>
>> >> SM8150 is based on Cortex-A55(little cores) and Cortex-A76(big 
>> cores).
>> >> I'm afraid I cannot give details about SC7180 yet.
>> >>
>> >> >> SM8150:
>> >> >> >> [    0.271177] CPU features: SANITY CHECK: Unexpected 
>> variation in
>> >> >> SYS_ID_AA64PFR0_EL1. Boot CPU: 0x00000011112222, CPU4: >> 
>> 0x00000011111112
>> >> >
>> >> > The differing fields are EL3, EL2, and EL1: the boot CPU 
>> supports
>> >> > AArch64 and AArch32 at those exception levels, while the 
>> secondary only
>> >> > supports AArch64.
>> >> >
>> >> > Do we handle this variation in KVM?
>> >>
>> >> We do not support KVM.
>> >
>> > Mainline does. You don't get to pick and choose what is supported 
>> or
>> > not.
>> >
>>
>> Ok thats good.
>>
>
> I want KVM on sc7180. How do I get it? Is something going to not 
> work?

If this SoC is anythinig like SM8150, 32bit guests will be hit and 
miss,
depending on the CPU your guest runs on, or is migrated to. We need to
either drop capabilities from the 32bit-capable CPU, or prevent the
non-32bit capable CPU from booting if a 32bit guest has been started.

You just have to hope that the kernel is entered at EL2, and that QC's
"value add" has been moved somewhere else...

         M.
-- 
Jazz is not dead. It just smells funny...