From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Tao Zhang <quic_taozha@quicinc.com>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Konrad Dybcio <konradybcio@gmail.com>,
Mike Leach <mike.leach@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Jinlong Mao <quic_jinlmao@quicinc.com>,
Leo Yan <leo.yan@linaro.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Tingwei Zhang <quic_tingweiz@quicinc.com>,
Yuanfang Zhang <quic_yuanfang@quicinc.com>,
Trilok Soni <quic_tsoni@quicinc.com>,
Hao Zhang <quic_hazha@quicinc.com>,
linux-arm-msm@vger.kernel.org, andersson@kernel.org
Subject: Re: [PATCH v4 07/11] coresight-tpdm: Add nodes for dsb edge control
Date: Fri, 2 Jun 2023 10:00:16 +0100 [thread overview]
Message-ID: <e82d7387-a299-20e5-3176-dce20966a10b@arm.com> (raw)
In-Reply-To: <a2bd3bbf-5512-971a-95a1-3220f31814a2@arm.com>
On 02/06/2023 09:45, Suzuki K Poulose wrote:
> On 02/06/2023 09:21, Tao Zhang wrote:
>>
>> On 6/1/2023 8:14 PM, Suzuki K Poulose wrote:
>>> On 27/04/2023 10:00, Tao Zhang wrote:
>>>> Add the nodes to set value for DSB edge control and DSB edge
>>>> control mask. Each DSB subunit TPDM has maximum of n(n<16) EDCR
>>>> resgisters to configure edge control. DSB edge detection control
>>>> 00: Rising edge detection
>>>> 01: Falling edge detection
>>>> 10: Rising and falling edge detection (toggle detection)
>>>> And each DSB subunit TPDM has maximum of m(m<8) ECDMR registers to
>>>> configure mask. Eight 32 bit registers providing DSB interface
>>>> edge detection mask control.
>>>>
>>>> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
>>>> ---
>>>> .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 32 +++++
>>>> drivers/hwtracing/coresight/coresight-tpdm.c | 135
>>>> ++++++++++++++++++++-
>>>> drivers/hwtracing/coresight/coresight-tpdm.h | 21 ++++
>>>> 3 files changed, 187 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git
>>>> a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
>>>> b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
>>>> index 348e167..a57f000 100644
>>>> --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
>>>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
>>>> @@ -60,3 +60,35 @@ Description:
>>>> Bit[3] : Set to 0 for low performance mode.
>>>> Set to 1 for high performance mode.
>>>> Bit[4:8] : Select byte lane for high performance mode.
>>>> +
>>>> +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge_ctrl
>>>> +Date: March 2023
>>>> +KernelVersion 6.3
>>>> +Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao
>>>> Zhang (QUIC) <quic_taozha@quicinc.com>
>>>> +Description:
>>>> + Read/Write a set of the edge control registers of the DSB
>>>> + in TPDM.
>>>> +
>>>> + Expected format is the following:
>>>> + <integer1> <integer2> <integer3>
>>>> +
>>>> + Where:
>>>> + <integer1> : Start EDCR register number
>>>> + <integer2> : End EDCR register number
>>>> + <integer3> : The value need to be written
>>>> +
>>>> +What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge_ctrl_mask
>>>> +Date: March 2023
>>>> +KernelVersion 6.3
>>>> +Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao
>>>> Zhang (QUIC) <quic_taozha@quicinc.com>
>>>> +Description:
>>>> + Read/Write a set of the edge control mask registers of the
>>>> + DSB in TPDM.
>>>> +
>>>> + Expected format is the following:
>>>> + <integer1> <integer2> <integer3>
>>>> +
>>>> + Where:
>>>> + <integer1> : Start EDCMR register number
>>>> + <integer2> : End EDCMR register number
>>>> + <integer3> : The value need to be written
>>>> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c
>>>> b/drivers/hwtracing/coresight/coresight-tpdm.c
>>>> index 1bacaa5..a40e458 100644
>>>> --- a/drivers/hwtracing/coresight/coresight-tpdm.c
>>>> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c
>>>> @@ -80,7 +80,14 @@ static void set_trigger_type(struct tpdm_drvdata
>>>> *drvdata, u32 *val)
>>>> static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)
>>>> {
>>>> - u32 val;
>>>> + u32 val, i;
>>>> +
>>>> + for (i = 0; i < TPDM_DSB_MAX_EDCR; i++)
>>>> + writel_relaxed(drvdata->dsb->edge_ctrl[i],
>>>> + drvdata->base + TPDM_DSB_EDCR(i));
>>>> + for (i = 0; i < TPDM_DSB_MAX_EDCMR; i++)
>>>> + writel_relaxed(drvdata->dsb->edge_ctrl_mask[i],
>>>> + drvdata->base + TPDM_DSB_EDCMR(i));
>>>
>>> Do all TPDM DSBs have MAX_EDCR registers ? Or some have less than that ?
>>> If it is latter, do we need special care to avoid writing to inexistent
>>> registers ?
>>>
>> You are right, not all DSB TPDMs have MAX_EDCR registers. In our
>> design, the inexistent register addresses
>>
>> are not occupied and safe for accessing.
Does the TRM for the component say so ? Or is it by luck ? If the spec
says it is RAZ/WriteIgnore, then we could keep the code as it is,
with a comment. Otherwise, we could add a DT property. So please get
this clarified with the H/W designers.
Suzuki
next prev parent reply other threads:[~2023-06-02 9:00 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-27 9:00 [PATCH v4 00/11] Add support to configure TPDM DSB subunit Tao Zhang
2023-04-27 9:00 ` [PATCH v4 01/11] dt-bindings: arm: Add support for DSB element size Tao Zhang
2023-04-27 12:59 ` Rob Herring
2023-04-27 9:00 ` [PATCH v4 02/11] coresight-tpda: Add DSB dataset support Tao Zhang
2023-05-23 10:07 ` Suzuki K Poulose
2023-05-23 14:48 ` Suzuki K Poulose
2023-05-25 7:20 ` Tao Zhang
2023-05-25 7:16 ` Tao Zhang
2023-05-25 9:08 ` Suzuki K Poulose
2023-05-26 3:22 ` Tao Zhang
2023-04-27 9:00 ` [PATCH v4 03/11] coresight-tpdm: Initialize DSB subunit configuration Tao Zhang
2023-05-23 13:42 ` Suzuki K Poulose
2023-05-25 8:12 ` Tao Zhang
2023-05-25 9:09 ` Suzuki K Poulose
2023-05-26 3:46 ` Tao Zhang
2023-04-27 9:00 ` [PATCH v4 04/11] coresight-tpdm: Add reset node to TPDM node Tao Zhang
2023-05-23 14:53 ` Suzuki K Poulose
2023-05-25 8:36 ` Tao Zhang
2023-04-27 9:00 ` [PATCH v4 05/11] coresight-tpdm: Add nodes to set trigger timestamp and type Tao Zhang
2023-06-01 9:05 ` Suzuki K Poulose
2023-06-02 2:29 ` Tao Zhang
2023-04-27 9:00 ` [PATCH v4 06/11] coresight-tpdm: Add node to set dsb programming mode Tao Zhang
2023-06-01 9:23 ` Suzuki K Poulose
2023-06-02 2:58 ` Tao Zhang
2023-06-02 8:25 ` Suzuki K Poulose
2023-06-02 8:31 ` Tao Zhang
2023-04-27 9:00 ` [PATCH v4 07/11] coresight-tpdm: Add nodes for dsb edge control Tao Zhang
2023-06-01 12:14 ` Suzuki K Poulose
2023-06-02 8:21 ` Tao Zhang
2023-06-02 8:45 ` Suzuki K Poulose
2023-06-02 9:00 ` Suzuki K Poulose [this message]
2023-06-05 9:12 ` Tao Zhang
2023-06-02 14:38 ` Tao Zhang
2023-06-02 16:05 ` Suzuki K Poulose
2023-04-27 9:00 ` [PATCH v4 08/11] coresight-tpdm: Add nodes to configure pattern match output Tao Zhang
2023-06-01 13:28 ` Suzuki K Poulose
2023-06-02 8:29 ` Tao Zhang
2023-04-27 9:00 ` [PATCH v4 09/11] coresight-tpdm: Add nodes for timestamp request Tao Zhang
2023-06-05 10:19 ` Suzuki K Poulose
2023-06-06 10:55 ` Tao Zhang
2023-04-27 9:00 ` [PATCH v4 10/11] dt-bindings: arm: Add support for DSB MSR register Tao Zhang
2023-04-27 9:00 ` [PATCH v4 11/11] coresight-tpdm: Add nodes for dsb msr support Tao Zhang
2023-06-05 10:24 ` Suzuki K Poulose
2023-06-06 12:45 ` Tao Zhang
2023-04-27 16:53 ` [PATCH v4 00/11] Add support to configure TPDM DSB subunit Suzuki K Poulose
[not found] ` <725b6ccd-ff70-a3d2-fe44-797c0509e643@quicinc.com>
2023-06-01 8:17 ` Tao Zhang
2023-06-01 8:36 ` Suzuki K Poulose
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