* [PATCH V9 0/4] Add S4 SoC PLL and Peripheral clock
@ 2023-05-17 7:02 Yu Tu
2023-05-17 7:02 ` [PATCH V9 1/4] dt-bindings: clock: document Amlogic S4 SoC PLL clock controller Yu Tu
` (3 more replies)
0 siblings, 4 replies; 15+ messages in thread
From: Yu Tu @ 2023-05-17 7:02 UTC (permalink / raw)
To: linux-clk, linux-arm-kernel, linux-amlogic, linux-kernel,
devicetree, Rob Herring, Neil Armstrong, Jerome Brunet,
Kevin Hilman, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Conor Dooley, Martin Blumenstingl
Cc: kelvin.zhang, qi.duan, Yu Tu
1. Add S4 SoC PLL and Peripheral clock controller dt-bindings.
2. Add PLL and Peripheral clock controller driver for S4 SOC.
Yu Tu (4):
dt-bindings: clock: document Amlogic S4 SoC PLL clock controller
dt-bindings: clock: document Amlogic S4 SoC peripherals clock
controller
clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver
clk: meson: s4: add support for Amlogic S4 SoC peripheral clock
controller
V8 -> V9: Add patch 0001/0002 dt-bindings tag. Suggested by Krzysztof.
V7 -> V8:
1. Change patch 0001/0002 dt-bindings title description, remove "meson".
Suggested by Dmitry, Neil.
2. Change patch 0003/0004 clocks comment, format and clock flags suggested by
Dmitry, Neil, Jerome.
V6 -> V7: Change send patch series as well change format and clock flags
suggested by Jerome. Change dt-bindings suggested by Krzysztof.
V5 -> V6: Change send patch series, as well change format and clock flags.
V4 -> V5: change format and clock flags and adjust the patch series
as suggested by Jerome.
V3 -> V4: change format and clock flags.
V2 -> V3: Use two clock controller.
V1 -> V2: Change format as discussed in the email.
Link:https://lore.kernel.org/linux-amlogic/20230516064736.10270-1-yu.tu@amlogic.com/
.../clock/amlogic,s4-peripherals-clkc.yaml | 97 +
.../bindings/clock/amlogic,s4-pll-clkc.yaml | 50 +
MAINTAINERS | 1 +
drivers/clk/meson/Kconfig | 25 +
drivers/clk/meson/Makefile | 2 +
drivers/clk/meson/s4-peripherals.c | 3830 +++++++++++++++++
drivers/clk/meson/s4-peripherals.h | 217 +
drivers/clk/meson/s4-pll.c | 907 ++++
drivers/clk/meson/s4-pll.h | 87 +
.../clock/amlogic,s4-peripherals-clkc.h | 131 +
.../dt-bindings/clock/amlogic,s4-pll-clkc.h | 30 +
11 files changed, 5377 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,s4-peripherals-clkc.yaml
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml
create mode 100644 drivers/clk/meson/s4-peripherals.c
create mode 100644 drivers/clk/meson/s4-peripherals.h
create mode 100644 drivers/clk/meson/s4-pll.c
create mode 100644 drivers/clk/meson/s4-pll.h
create mode 100644 include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h
create mode 100644 include/dt-bindings/clock/amlogic,s4-pll-clkc.h
base-commit: ac9a78681b921877518763ba0e89202254349d1b
--
2.33.1
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH V9 1/4] dt-bindings: clock: document Amlogic S4 SoC PLL clock controller
2023-05-17 7:02 [PATCH V9 0/4] Add S4 SoC PLL and Peripheral clock Yu Tu
@ 2023-05-17 7:02 ` Yu Tu
2023-05-17 7:02 ` [PATCH V9 2/4] dt-bindings: clock: document Amlogic S4 SoC peripherals " Yu Tu
` (2 subsequent siblings)
3 siblings, 0 replies; 15+ messages in thread
From: Yu Tu @ 2023-05-17 7:02 UTC (permalink / raw)
To: linux-clk, linux-arm-kernel, linux-amlogic, linux-kernel,
devicetree, Rob Herring, Neil Armstrong, Jerome Brunet,
Kevin Hilman, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Conor Dooley, Martin Blumenstingl
Cc: kelvin.zhang, qi.duan, Yu Tu, Rob Herring
Add the S4 PLL clock controller dt-bindings in the s4 SoC family.
Signed-off-by: Yu Tu <yu.tu@amlogic.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/clock/amlogic,s4-pll-clkc.yaml | 50 +++++++++++++++++++
MAINTAINERS | 1 +
.../dt-bindings/clock/amlogic,s4-pll-clkc.h | 30 +++++++++++
3 files changed, 81 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml
create mode 100644 include/dt-bindings/clock/amlogic,s4-pll-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml
new file mode 100644
index 000000000000..242cceb5033a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,s4-pll-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic S serials PLL Clock Controller
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Yu Tu <yu.tu@amlogic.com>
+
+properties:
+ compatible:
+ const: amlogic,s4-pll-clkc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: xtal
+
+ "#clock-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ clkc_pll: clock-controller@fe008000 {
+ compatible = "amlogic,s4-pll-clkc";
+ reg = <0xfe008000 0x1e8>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ #clock-cells = <1>;
+ };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 7e0b87d5aa2e..09422aa49f61 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1888,6 +1888,7 @@ L: linux-amlogic@lists.infradead.org
S: Maintained
F: Documentation/devicetree/bindings/clock/amlogic*
F: drivers/clk/meson/
+F: include/dt-bindings/clock/amlogic*
F: include/dt-bindings/clock/gxbb*
F: include/dt-bindings/clock/meson*
diff --git a/include/dt-bindings/clock/amlogic,s4-pll-clkc.h b/include/dt-bindings/clock/amlogic,s4-pll-clkc.h
new file mode 100644
index 000000000000..1dcdedb1a6dd
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,s4-pll-clkc.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
+ * Author: Yu Tu <yu.tu@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H
+#define _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H
+
+/*
+ * CLKID index values
+ */
+
+#define CLKID_FIXED_PLL 1
+#define CLKID_FCLK_DIV2 3
+#define CLKID_FCLK_DIV3 5
+#define CLKID_FCLK_DIV4 7
+#define CLKID_FCLK_DIV5 9
+#define CLKID_FCLK_DIV7 11
+#define CLKID_FCLK_DIV2P5 13
+#define CLKID_GP0_PLL 15
+#define CLKID_HIFI_PLL 17
+#define CLKID_HDMI_PLL 20
+#define CLKID_MPLL_50M 22
+#define CLKID_MPLL0 25
+#define CLKID_MPLL1 27
+#define CLKID_MPLL2 29
+#define CLKID_MPLL3 31
+
+#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H */
--
2.33.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH V9 2/4] dt-bindings: clock: document Amlogic S4 SoC peripherals clock controller
2023-05-17 7:02 [PATCH V9 0/4] Add S4 SoC PLL and Peripheral clock Yu Tu
2023-05-17 7:02 ` [PATCH V9 1/4] dt-bindings: clock: document Amlogic S4 SoC PLL clock controller Yu Tu
@ 2023-05-17 7:02 ` Yu Tu
2023-05-17 7:02 ` [PATCH V9 3/4] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver Yu Tu
[not found] ` <20230517070215.28463-5-yu.tu@amlogic.com>
3 siblings, 0 replies; 15+ messages in thread
From: Yu Tu @ 2023-05-17 7:02 UTC (permalink / raw)
To: linux-clk, linux-arm-kernel, linux-amlogic, linux-kernel,
devicetree, Rob Herring, Neil Armstrong, Jerome Brunet,
Kevin Hilman, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Conor Dooley, Martin Blumenstingl
Cc: kelvin.zhang, qi.duan, Yu Tu, Rob Herring
Add the S4 peripherals clock controller dt-bindings in the s4 SoC
family.
Signed-off-by: Yu Tu <yu.tu@amlogic.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../clock/amlogic,s4-peripherals-clkc.yaml | 97 +++++++++++++
.../clock/amlogic,s4-peripherals-clkc.h | 131 ++++++++++++++++++
2 files changed, 228 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,s4-peripherals-clkc.yaml
create mode 100644 include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,s4-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,s4-peripherals-clkc.yaml
new file mode 100644
index 000000000000..6f825c9613a2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,s4-peripherals-clkc.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,s4-peripherals-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic S serials Peripherals Clock Controller
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Yu Tu <yu.tu@amlogic.com>
+
+properties:
+ compatible:
+ const: amlogic,s4-peripherals-clkc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: input fixed pll div2
+ - description: input fixed pll div2p5
+ - description: input fixed pll div3
+ - description: input fixed pll div4
+ - description: input fixed pll div5
+ - description: input fixed pll div7
+ - description: input hifi pll
+ - description: input gp0 pll
+ - description: input mpll0
+ - description: input mpll1
+ - description: input mpll2
+ - description: input mpll3
+ - description: input hdmi pll
+ - description: input oscillator (usually at 24MHz)
+ - description: input external 32kHz reference (optional)
+
+ clock-names:
+ items:
+ - const: fclk_div2
+ - const: fclk_div2p5
+ - const: fclk_div3
+ - const: fclk_div4
+ - const: fclk_div5
+ - const: fclk_div7
+ - const: hifi_pll
+ - const: gp0_pll
+ - const: mpll0
+ - const: mpll1
+ - const: mpll2
+ - const: mpll3
+ - const: hdmi_pll
+ - const: xtal
+ - const: ext_32k
+
+ "#clock-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h>
+
+ clkc_periphs: clock-controller@fe000000 {
+ compatible = "amlogic,s4-peripherals-clkc";
+ reg = <0xfe000000 0x49c>;
+ clocks = <&clkc_pll 3>,
+ <&clkc_pll 13>,
+ <&clkc_pll 5>,
+ <&clkc_pll 7>,
+ <&clkc_pll 9>,
+ <&clkc_pll 11>,
+ <&clkc_pll 17>,
+ <&clkc_pll 15>,
+ <&clkc_pll 25>,
+ <&clkc_pll 27>,
+ <&clkc_pll 29>,
+ <&clkc_pll 31>,
+ <&clkc_pll 20>,
+ <&xtal>,
+ <&ext_32k>;
+ clock-names = "fclk_div2", "fclk_div2p5", "fclk_div3", "fclk_div4",
+ "fclk_div5", "fclk_div7", "hifi_pll", "gp0_pll",
+ "mpll0", "mpll1", "mpll2", "mpll3", "hdmi_pll", "xtal",
+ "ext_32k";
+ #clock-cells = <1>;
+ };
+...
diff --git a/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h
new file mode 100644
index 000000000000..131b35759eff
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
+ * Author: Yu Tu <yu.tu@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H
+#define _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H
+
+/*
+ * CLKID index values
+ */
+
+#define CLKID_RTC 4
+#define CLKID_SYS_CLK_B 7
+#define CLKID_SYS_CLK_A 10
+#define CLKID_SYS 11
+#define CLKID_CECA_32K_CLKOUT 16
+#define CLKID_CECB_32K_CLKOUT 21
+#define CLKID_SC 24
+#define CLKID_12_24M_CLK_SEL 27
+#define CLKID_VID_PLL 30
+#define CLKID_VCLK 37
+#define CLKID_VCLK2 38
+#define CLKID_VCLK_DIV1 39
+#define CLKID_VCLK2_DIV1 44
+#define CLKID_VCLK_DIV2 49
+#define CLKID_VCLK_DIV4 50
+#define CLKID_VCLK_DIV6 51
+#define CLKID_VCLK_DIV12 52
+#define CLKID_VCLK2_DIV2 53
+#define CLKID_VCLK2_DIV4 54
+#define CLKID_VCLK2_DIV6 55
+#define CLKID_VCLK2_DIV12 56
+#define CLKID_CTS_ENCI 61
+#define CLKID_CTS_ENCP 62
+#define CLKID_CTS_VDAC 63
+#define CLKID_HDMI 67
+#define CLKID_TS 69
+#define CLKID_MALI_0 72
+#define CLKID_MALI_1 75
+#define CLKID_MALI_SEL 76
+#define CLKID_VDEC_P0 79
+#define CLKID_VDEC_P1 82
+#define CLKID_VDEC_SEL 83
+#define CLKID_HEVCF_P0 86
+#define CLKID_HEVCF_P1 89
+#define CLKID_HEVCF_SEL 90
+#define CLKID_VPU_0 93
+#define CLKID_VPU_1 96
+#define CLKID_VPU 97
+#define CLKID_VPU_CLKB_TMP 100
+#define CLKID_VPU_CLKB 102
+#define CLKID_VPU_CLKC_P0 105
+#define CLKID_VPU_CLKC_P1 108
+#define CLKID_VPU_CLKC_SEL 109
+#define CLKID_VAPB_0 112
+#define CLKID_VAPB_1 115
+#define CLKID_VAPB 116
+#define CLKID_GE2D 117
+#define CLKID_VDIN_MEAS 120
+#define CLKID_SD_EMMC_C 123
+#define CLKID_SD_EMMC_A 126
+#define CLKID_SD_EMMC_B 129
+#define CLKID_SPICC0_EN 132
+#define CLKID_PWM_A 135
+#define CLKID_PWM_B 138
+#define CLKID_PWM_C 141
+#define CLKID_PWM_D 144
+#define CLKID_PWM_E 147
+#define CLKID_PWM_F 150
+#define CLKID_PWM_G 153
+#define CLKID_PWM_H 156
+#define CLKID_PWM_I 159
+#define CLKID_PWM_J 162
+#define CLKID_SARADC 165
+#define CLKID_GEN 168
+#define CLKID_DDR 169
+#define CLKID_DOS 170
+#define CLKID_ETHPHY 171
+#define CLKID_MALI 172
+#define CLKID_AOCPU 173
+#define CLKID_AUCPU 174
+#define CLKID_CEC 175
+#define CLKID_SDEMMC_A 176
+#define CLKID_SDEMMC_B 177
+#define CLKID_NAND 178
+#define CLKID_SMARTCARD 179
+#define CLKID_ACODEC 180
+#define CLKID_SPIFC 181
+#define CLKID_MSR 182
+#define CLKID_IR_CTRL 183
+#define CLKID_AUDIO 184
+#define CLKID_ETH 185
+#define CLKID_UART_A 186
+#define CLKID_UART_B 187
+#define CLKID_UART_C 188
+#define CLKID_UART_D 189
+#define CLKID_UART_E 190
+#define CLKID_AIFIFO 191
+#define CLKID_TS_DDR 192
+#define CLKID_TS_PLL 193
+#define CLKID_G2D 194
+#define CLKID_SPICC0 195
+#define CLKID_SPICC1 196
+#define CLKID_USB 197
+#define CLKID_I2C_M_A 198
+#define CLKID_I2C_M_B 199
+#define CLKID_I2C_M_C 200
+#define CLKID_I2C_M_D 201
+#define CLKID_I2C_M_E 202
+#define CLKID_HDMITX_APB 203
+#define CLKID_I2C_S_A 204
+#define CLKID_USB1_TO_DDR 205
+#define CLKID_HDCP22 206
+#define CLKID_MMC_APB 207
+#define CLKID_RSA 208
+#define CLKID_CPU_DEBUG 209
+#define CLKID_VPU_INTR 210
+#define CLKID_DEMOD 211
+#define CLKID_SAR_ADC 212
+#define CLKID_GIC 213
+#define CLKID_PWM_AB 214
+#define CLKID_PWM_CD 215
+#define CLKID_PWM_EF 216
+#define CLKID_PWM_GH 217
+#define CLKID_PWM_IJ 218
+#define CLKID_HDCP22_ESMCLK 221
+#define CLKID_HDCP22_SKPCLK 224
+
+#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H */
--
2.33.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH V9 3/4] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver
2023-05-17 7:02 [PATCH V9 0/4] Add S4 SoC PLL and Peripheral clock Yu Tu
2023-05-17 7:02 ` [PATCH V9 1/4] dt-bindings: clock: document Amlogic S4 SoC PLL clock controller Yu Tu
2023-05-17 7:02 ` [PATCH V9 2/4] dt-bindings: clock: document Amlogic S4 SoC peripherals " Yu Tu
@ 2023-05-17 7:02 ` Yu Tu
2023-06-06 14:02 ` Jerome Brunet
2023-06-06 14:34 ` Jerome Brunet
[not found] ` <20230517070215.28463-5-yu.tu@amlogic.com>
3 siblings, 2 replies; 15+ messages in thread
From: Yu Tu @ 2023-05-17 7:02 UTC (permalink / raw)
To: linux-clk, linux-arm-kernel, linux-amlogic, linux-kernel,
devicetree, Rob Herring, Neil Armstrong, Jerome Brunet,
Kevin Hilman, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Conor Dooley, Martin Blumenstingl
Cc: kelvin.zhang, qi.duan, Yu Tu
Add the S4 PLL clock controller driver in the s4 SoC family.
Signed-off-by: Yu Tu <yu.tu@amlogic.com>
---
drivers/clk/meson/Kconfig | 13 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/s4-pll.c | 907 +++++++++++++++++++++++++++++++++++++
drivers/clk/meson/s4-pll.h | 87 ++++
4 files changed, 1008 insertions(+)
create mode 100644 drivers/clk/meson/s4-pll.c
create mode 100644 drivers/clk/meson/s4-pll.h
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index fc002c155bc3..a663c90a3f3b 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -115,4 +115,17 @@ config COMMON_CLK_G12A
help
Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
devices, aka g12a. Say Y if you want peripherals to work.
+
+config COMMON_CLK_S4_PLL
+ tristate "S4 SoC PLL clock controllers support"
+ depends on ARM64
+ default y
+ select COMMON_CLK_MESON_MPLL
+ select COMMON_CLK_MESON_PLL
+ select COMMON_CLK_MESON_REGMAP
+ help
+ Support for the pll clock controller on Amlogic S805X2 and S905Y4 devices,
+ aka s4. Amlogic S805X2 and S905Y4 devices include AQ222 and AQ229.
+ Say Y if you want the board to work, because plls are the parent of most
+ peripherals.
endmenu
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 6eca2a406ee3..376f49cc13f1 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
+obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o
diff --git a/drivers/clk/meson/s4-pll.c b/drivers/clk/meson/s4-pll.c
new file mode 100644
index 000000000000..c70a33586bcd
--- /dev/null
+++ b/drivers/clk/meson/s4-pll.c
@@ -0,0 +1,907 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic Meson-S4 PLL Clock Controller Driver
+ *
+ * Copyright (c) 2021 Amlogic, inc.
+ * Author: Yu Tu <yu.tu@amlogic.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mpll.h"
+#include "clk-pll.h"
+#include "clk-regmap.h"
+#include "s4-pll.h"
+
+static DEFINE_SPINLOCK(meson_clk_lock);
+
+static struct clk_regmap s4_fixed_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = ANACTRL_FIXPLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = ANACTRL_FIXPLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = ANACTRL_FIXPLL_CTRL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .frac = {
+ .reg_off = ANACTRL_FIXPLL_CTRL1,
+ .shift = 0,
+ .width = 17,
+ },
+ .l = {
+ .reg_off = ANACTRL_FIXPLL_CTRL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = ANACTRL_FIXPLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fixed_pll_dco",
+ /*
+ * This clock is a fixed value (4GHz) that is initialized by ROMcode.
+ * This clock won't ever change at runtime.
+ * The chip design determines that this clock cannot be changed after
+ * initialization. To prevent system crash caused by changing
+ * fixed related register in kernel phase. This register is not
+ * writable in the kernel phase.
+ * So we use ro_ops.
+ */
+ .ops = &meson_clk_pll_ro_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xtal", }
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap s4_fixed_pll = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = ANACTRL_FIXPLL_CTRL0,
+ .shift = 16,
+ .width = 2,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fixed_pll",
+ /*
+ * This clock is a fixed value (2GHz) that is initialized by ROMcode.
+ * For more information, please refer to s4_fixed_pll_dco.
+ */
+ .ops = &clk_regmap_divider_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_fixed_pll_dco.hw
+ },
+ .num_parents = 1,
+ /*
+ * This clock won't ever change at runtime so
+ * CLK_SET_RATE_PARENT is not required
+ */
+ },
+};
+
+static struct clk_fixed_factor s4_fclk_div2_div = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div2_div",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap s4_fclk_div2 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = ANACTRL_FIXPLL_CTRL1,
+ .bit_idx = 24,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div2",
+ /*
+ * This clock is a fixed value (1GHz) that is initialized by ROMcode.
+ * For more information, please refer to s4_fixed_pll_dco.
+ */
+ .ops = &clk_regmap_gate_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_fclk_div2_div.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor s4_fclk_div3_div = {
+ .mult = 1,
+ .div = 3,
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div3_div",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap s4_fclk_div3 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = ANACTRL_FIXPLL_CTRL1,
+ .bit_idx = 20,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div3",
+ /*
+ * For more information, please refer to s4_fixed_pll_dco.
+ */
+ .ops = &clk_regmap_gate_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_fclk_div3_div.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor s4_fclk_div4_div = {
+ .mult = 1,
+ .div = 4,
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div4_div",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap s4_fclk_div4 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = ANACTRL_FIXPLL_CTRL1,
+ .bit_idx = 21,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div4",
+ /*
+ * For more information, please refer to s4_fixed_pll_dco.
+ */
+ .ops = &clk_regmap_gate_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_fclk_div4_div.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor s4_fclk_div5_div = {
+ .mult = 1,
+ .div = 5,
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div5_div",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap s4_fclk_div5 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = ANACTRL_FIXPLL_CTRL1,
+ .bit_idx = 22,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div5",
+ /*
+ * For more information, please refer to s4_fixed_pll_dco.
+ */
+ .ops = &clk_regmap_gate_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_fclk_div5_div.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor s4_fclk_div7_div = {
+ .mult = 1,
+ .div = 7,
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div7_div",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap s4_fclk_div7 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = ANACTRL_FIXPLL_CTRL1,
+ .bit_idx = 23,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div7",
+ /*
+ * For more information, please refer to s4_fixed_pll_dco.
+ */
+ .ops = &clk_regmap_gate_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_fclk_div7_div.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_fixed_factor s4_fclk_div2p5_div = {
+ .mult = 2,
+ .div = 5,
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div2p5_div",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_fixed_pll.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap s4_fclk_div2p5 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = ANACTRL_FIXPLL_CTRL1,
+ .bit_idx = 25,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fclk_div2p5",
+ /*
+ * For more information, please refer to s4_fixed_pll_dco.
+ */
+ .ops = &clk_regmap_gate_ro_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_fclk_div2p5_div.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct pll_mult_range s4_gp0_pll_mult_range = {
+ .min = 125,
+ .max = 250,
+};
+
+/*
+ * Internal gp0 pll emulation configuration parameters
+ */
+static const struct reg_sequence s4_gp0_init_regs[] = {
+ { .reg = ANACTRL_GP0PLL_CTRL1, .def = 0x00000000 },
+ { .reg = ANACTRL_GP0PLL_CTRL2, .def = 0x00000000 },
+ { .reg = ANACTRL_GP0PLL_CTRL3, .def = 0x48681c00 },
+ { .reg = ANACTRL_GP0PLL_CTRL4, .def = 0x88770290 },
+ { .reg = ANACTRL_GP0PLL_CTRL5, .def = 0x39272000 },
+ { .reg = ANACTRL_GP0PLL_CTRL6, .def = 0x56540000 }
+};
+
+static struct clk_regmap s4_gp0_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = ANACTRL_GP0PLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = ANACTRL_GP0PLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = ANACTRL_GP0PLL_CTRL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .frac = {
+ .reg_off = ANACTRL_GP0PLL_CTRL1,
+ .shift = 0,
+ .width = 17,
+ },
+ .l = {
+ .reg_off = ANACTRL_GP0PLL_CTRL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = ANACTRL_GP0PLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .range = &s4_gp0_pll_mult_range,
+ .init_regs = s4_gp0_init_regs,
+ .init_count = ARRAY_SIZE(s4_gp0_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "gp0_pll_dco",
+ .ops = &meson_clk_pll_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xtal", }
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap s4_gp0_pll = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = ANACTRL_GP0PLL_CTRL0,
+ .shift = 16,
+ .width = 3,
+ .flags = (CLK_DIVIDER_POWER_OF_TWO |
+ CLK_DIVIDER_ROUND_CLOSEST),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "gp0_pll",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_gp0_pll_dco.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+/*
+ * Internal hifi pll emulation configuration parameters
+ */
+static const struct reg_sequence s4_hifi_init_regs[] = {
+ { .reg = ANACTRL_HIFIPLL_CTRL1, .def = 0x00010e56 },
+ { .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00000000 },
+ { .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x6a285c00 },
+ { .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x65771290 },
+ { .reg = ANACTRL_HIFIPLL_CTRL5, .def = 0x39272000 },
+ { .reg = ANACTRL_HIFIPLL_CTRL6, .def = 0x56540000 }
+};
+
+static struct clk_regmap s4_hifi_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .frac = {
+ .reg_off = ANACTRL_HIFIPLL_CTRL1,
+ .shift = 0,
+ .width = 17,
+ },
+ .l = {
+ .reg_off = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .range = &s4_gp0_pll_mult_range,
+ .init_regs = s4_hifi_init_regs,
+ .init_count = ARRAY_SIZE(s4_hifi_init_regs),
+ .flags = CLK_MESON_PLL_ROUND_CLOSEST,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "hifi_pll_dco",
+ .ops = &meson_clk_pll_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xtal", }
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap s4_hifi_pll = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 16,
+ .width = 2,
+ .flags = (CLK_DIVIDER_POWER_OF_TWO |
+ CLK_DIVIDER_ROUND_CLOSEST),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "hifi_pll",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_hifi_pll_dco.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap s4_hdmi_pll_dco = {
+ .data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = ANACTRL_HDMIPLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg_off = ANACTRL_HDMIPLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg_off = ANACTRL_HDMIPLL_CTRL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .frac = {
+ .reg_off = ANACTRL_HDMIPLL_CTRL1,
+ .shift = 0,
+ .width = 17,
+ },
+ .l = {
+ .reg_off = ANACTRL_HDMIPLL_CTRL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg_off = ANACTRL_HDMIPLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .range = &s4_gp0_pll_mult_range,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "hdmi_pll_dco",
+ .ops = &meson_clk_pll_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xtal", }
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap s4_hdmi_pll_od = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = ANACTRL_HDMIPLL_CTRL0,
+ .shift = 16,
+ .width = 4,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "hdmi_pll_od",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_hdmi_pll_dco.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap s4_hdmi_pll = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = ANACTRL_HDMIPLL_CTRL0,
+ .shift = 20,
+ .width = 2,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "hdmi_pll",
+ .ops = &clk_regmap_divider_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_hdmi_pll_od.hw
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_fixed_factor s4_mpll_50m_div = {
+ .mult = 1,
+ .div = 80,
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll_50m_div",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_fixed_pll_dco.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap s4_mpll_50m = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = ANACTRL_FIXPLL_CTRL3,
+ .mask = 0x1,
+ .shift = 5,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll_50m",
+ .ops = &clk_regmap_mux_ro_ops,
+ .parent_data = (const struct clk_parent_data []) {
+ { .fw_name = "xtal", },
+ { .hw = &s4_mpll_50m_div.hw },
+ },
+ .num_parents = 2,
+ },
+};
+
+static struct clk_fixed_factor s4_mpll_prediv = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll_prediv",
+ .ops = &clk_fixed_factor_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_fixed_pll_dco.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static const struct reg_sequence s4_mpll0_init_regs[] = {
+ { .reg = ANACTRL_MPLL_CTRL2, .def = 0x40000033 }
+};
+
+static struct clk_regmap s4_mpll0_div = {
+ .data = &(struct meson_clk_mpll_data){
+ .sdm = {
+ .reg_off = ANACTRL_MPLL_CTRL1,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg_off = ANACTRL_MPLL_CTRL1,
+ .shift = 30,
+ .width = 1,
+ },
+ .n2 = {
+ .reg_off = ANACTRL_MPLL_CTRL1,
+ .shift = 20,
+ .width = 9,
+ },
+ .ssen = {
+ .reg_off = ANACTRL_MPLL_CTRL1,
+ .shift = 29,
+ .width = 1,
+ },
+ .lock = &meson_clk_lock,
+ .init_regs = s4_mpll0_init_regs,
+ .init_count = ARRAY_SIZE(s4_mpll0_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll0_div",
+ .ops = &meson_clk_mpll_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_mpll_prediv.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap s4_mpll0 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = ANACTRL_MPLL_CTRL1,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll0",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) { &s4_mpll0_div.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct reg_sequence s4_mpll1_init_regs[] = {
+ { .reg = ANACTRL_MPLL_CTRL4, .def = 0x40000033 }
+};
+
+static struct clk_regmap s4_mpll1_div = {
+ .data = &(struct meson_clk_mpll_data){
+ .sdm = {
+ .reg_off = ANACTRL_MPLL_CTRL3,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg_off = ANACTRL_MPLL_CTRL3,
+ .shift = 30,
+ .width = 1,
+ },
+ .n2 = {
+ .reg_off = ANACTRL_MPLL_CTRL3,
+ .shift = 20,
+ .width = 9,
+ },
+ .ssen = {
+ .reg_off = ANACTRL_MPLL_CTRL3,
+ .shift = 29,
+ .width = 1,
+ },
+ .lock = &meson_clk_lock,
+ .init_regs = s4_mpll1_init_regs,
+ .init_count = ARRAY_SIZE(s4_mpll1_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll1_div",
+ .ops = &meson_clk_mpll_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_mpll_prediv.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap s4_mpll1 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = ANACTRL_MPLL_CTRL3,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll1",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) { &s4_mpll1_div.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct reg_sequence s4_mpll2_init_regs[] = {
+ { .reg = ANACTRL_MPLL_CTRL6, .def = 0x40000033 }
+};
+
+static struct clk_regmap s4_mpll2_div = {
+ .data = &(struct meson_clk_mpll_data){
+ .sdm = {
+ .reg_off = ANACTRL_MPLL_CTRL5,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg_off = ANACTRL_MPLL_CTRL5,
+ .shift = 30,
+ .width = 1,
+ },
+ .n2 = {
+ .reg_off = ANACTRL_MPLL_CTRL5,
+ .shift = 20,
+ .width = 9,
+ },
+ .ssen = {
+ .reg_off = ANACTRL_MPLL_CTRL5,
+ .shift = 29,
+ .width = 1,
+ },
+ .lock = &meson_clk_lock,
+ .init_regs = s4_mpll2_init_regs,
+ .init_count = ARRAY_SIZE(s4_mpll2_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll2_div",
+ .ops = &meson_clk_mpll_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_mpll_prediv.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap s4_mpll2 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = ANACTRL_MPLL_CTRL5,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll2",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) { &s4_mpll2_div.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static const struct reg_sequence s4_mpll3_init_regs[] = {
+ { .reg = ANACTRL_MPLL_CTRL8, .def = 0x40000033 }
+};
+
+static struct clk_regmap s4_mpll3_div = {
+ .data = &(struct meson_clk_mpll_data){
+ .sdm = {
+ .reg_off = ANACTRL_MPLL_CTRL7,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg_off = ANACTRL_MPLL_CTRL7,
+ .shift = 30,
+ .width = 1,
+ },
+ .n2 = {
+ .reg_off = ANACTRL_MPLL_CTRL7,
+ .shift = 20,
+ .width = 9,
+ },
+ .ssen = {
+ .reg_off = ANACTRL_MPLL_CTRL7,
+ .shift = 29,
+ .width = 1,
+ },
+ .lock = &meson_clk_lock,
+ .init_regs = s4_mpll3_init_regs,
+ .init_count = ARRAY_SIZE(s4_mpll3_init_regs),
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll3_div",
+ .ops = &meson_clk_mpll_ops,
+ .parent_hws = (const struct clk_hw *[]) {
+ &s4_mpll_prediv.hw
+ },
+ .num_parents = 1,
+ },
+};
+
+static struct clk_regmap s4_mpll3 = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = ANACTRL_MPLL_CTRL7,
+ .bit_idx = 31,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "mpll3",
+ .ops = &clk_regmap_gate_ops,
+ .parent_hws = (const struct clk_hw *[]) { &s4_mpll3_div.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+/* Array of all clocks provided by this provider */
+static struct clk_hw_onecell_data s4_pll_hw_onecell_data = {
+ .hws = {
+ [CLKID_FIXED_PLL_DCO] = &s4_fixed_pll_dco.hw,
+ [CLKID_FIXED_PLL] = &s4_fixed_pll.hw,
+ [CLKID_FCLK_DIV2_DIV] = &s4_fclk_div2_div.hw,
+ [CLKID_FCLK_DIV2] = &s4_fclk_div2.hw,
+ [CLKID_FCLK_DIV3_DIV] = &s4_fclk_div3_div.hw,
+ [CLKID_FCLK_DIV3] = &s4_fclk_div3.hw,
+ [CLKID_FCLK_DIV4_DIV] = &s4_fclk_div4_div.hw,
+ [CLKID_FCLK_DIV4] = &s4_fclk_div4.hw,
+ [CLKID_FCLK_DIV5_DIV] = &s4_fclk_div5_div.hw,
+ [CLKID_FCLK_DIV5] = &s4_fclk_div5.hw,
+ [CLKID_FCLK_DIV7_DIV] = &s4_fclk_div7_div.hw,
+ [CLKID_FCLK_DIV7] = &s4_fclk_div7.hw,
+ [CLKID_FCLK_DIV2P5_DIV] = &s4_fclk_div2p5_div.hw,
+ [CLKID_FCLK_DIV2P5] = &s4_fclk_div2p5.hw,
+ [CLKID_GP0_PLL_DCO] = &s4_gp0_pll_dco.hw,
+ [CLKID_GP0_PLL] = &s4_gp0_pll.hw,
+ [CLKID_HIFI_PLL_DCO] = &s4_hifi_pll_dco.hw,
+ [CLKID_HIFI_PLL] = &s4_hifi_pll.hw,
+ [CLKID_HDMI_PLL_DCO] = &s4_hdmi_pll_dco.hw,
+ [CLKID_HDMI_PLL_OD] = &s4_hdmi_pll_od.hw,
+ [CLKID_HDMI_PLL] = &s4_hdmi_pll.hw,
+ [CLKID_MPLL_50M_DIV] = &s4_mpll_50m_div.hw,
+ [CLKID_MPLL_50M] = &s4_mpll_50m.hw,
+ [CLKID_MPLL_PREDIV] = &s4_mpll_prediv.hw,
+ [CLKID_MPLL0_DIV] = &s4_mpll0_div.hw,
+ [CLKID_MPLL0] = &s4_mpll0.hw,
+ [CLKID_MPLL1_DIV] = &s4_mpll1_div.hw,
+ [CLKID_MPLL1] = &s4_mpll1.hw,
+ [CLKID_MPLL2_DIV] = &s4_mpll2_div.hw,
+ [CLKID_MPLL2] = &s4_mpll2.hw,
+ [CLKID_MPLL3_DIV] = &s4_mpll3_div.hw,
+ [CLKID_MPLL3] = &s4_mpll3.hw,
+ [NR_PLL_CLKS] = NULL
+ },
+ .num = NR_PLL_CLKS,
+};
+
+static struct clk_regmap *const s4_pll_clk_regmaps[] = {
+ &s4_fixed_pll_dco,
+ &s4_fixed_pll,
+ &s4_fclk_div2,
+ &s4_fclk_div3,
+ &s4_fclk_div4,
+ &s4_fclk_div5,
+ &s4_fclk_div7,
+ &s4_fclk_div2p5,
+ &s4_gp0_pll_dco,
+ &s4_gp0_pll,
+ &s4_hifi_pll_dco,
+ &s4_hifi_pll,
+ &s4_hdmi_pll_dco,
+ &s4_hdmi_pll_od,
+ &s4_hdmi_pll,
+ &s4_mpll_50m,
+ &s4_mpll0_div,
+ &s4_mpll0,
+ &s4_mpll1_div,
+ &s4_mpll1,
+ &s4_mpll2_div,
+ &s4_mpll2,
+ &s4_mpll3_div,
+ &s4_mpll3,
+};
+
+static const struct reg_sequence s4_init_regs[] = {
+ { .reg = ANACTRL_MPLL_CTRL0, .def = 0x00000543 },
+};
+
+static struct regmap_config clkc_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
+static int meson_s4_pll_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct regmap *regmap;
+ void __iomem *base;
+ int ret, i;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ regmap = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ ret = regmap_multi_reg_write(regmap, s4_init_regs, ARRAY_SIZE(s4_init_regs));
+ if (ret) {
+ dev_err(dev, "Failed to init registers\n");
+ return ret;
+ }
+
+ /* Populate regmap for the regmap backed clocks */
+ for (i = 0; i < ARRAY_SIZE(s4_pll_clk_regmaps); i++)
+ s4_pll_clk_regmaps[i]->map = regmap;
+
+ for (i = 0; i < s4_pll_hw_onecell_data.num; i++) {
+ /* array might be sparse */
+ if (!s4_pll_hw_onecell_data.hws[i])
+ continue;
+
+ ret = devm_clk_hw_register(dev, s4_pll_hw_onecell_data.hws[i]);
+ if (ret) {
+ dev_err(dev, "Clock registration failed\n");
+ return ret;
+ }
+ }
+
+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+ &s4_pll_hw_onecell_data);
+}
+
+static const struct of_device_id clkc_match_table[] = {
+ {
+ .compatible = "amlogic,s4-pll-clkc",
+ },
+ {}
+};
+
+static struct platform_driver s4_driver = {
+ .probe = meson_s4_pll_probe,
+ .driver = {
+ .name = "s4-pll-clkc",
+ .of_match_table = clkc_match_table,
+ },
+};
+
+module_platform_driver(s4_driver);
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/meson/s4-pll.h b/drivers/clk/meson/s4-pll.h
new file mode 100644
index 000000000000..021d9f8b2b30
--- /dev/null
+++ b/drivers/clk/meson/s4-pll.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2021 Amlogic, inc.
+ * Author: Yu Tu <yu.tu@amlogic.com>
+ */
+
+#ifndef __MESON_S4_PLL_H__
+#define __MESON_S4_PLL_H__
+
+/* ANA_CTRL - Registers */
+
+#define ANACTRL_FIXPLL_CTRL0 0x040
+#define ANACTRL_FIXPLL_CTRL1 0x044
+#define ANACTRL_FIXPLL_CTRL2 0x048
+#define ANACTRL_FIXPLL_CTRL3 0x04c
+#define ANACTRL_FIXPLL_CTRL4 0x050
+#define ANACTRL_FIXPLL_CTRL5 0x054
+#define ANACTRL_FIXPLL_CTRL6 0x058
+#define ANACTRL_FIXPLL_STS 0x05c
+#define ANACTRL_GP0PLL_CTRL0 0x080
+#define ANACTRL_GP0PLL_CTRL1 0x084
+#define ANACTRL_GP0PLL_CTRL2 0x088
+#define ANACTRL_GP0PLL_CTRL3 0x08c
+#define ANACTRL_GP0PLL_CTRL4 0x090
+#define ANACTRL_GP0PLL_CTRL5 0x094
+#define ANACTRL_GP0PLL_CTRL6 0x098
+#define ANACTRL_GP0PLL_STS 0x09c
+#define ANACTRL_HIFIPLL_CTRL0 0x100
+#define ANACTRL_HIFIPLL_CTRL1 0x104
+#define ANACTRL_HIFIPLL_CTRL2 0x108
+#define ANACTRL_HIFIPLL_CTRL3 0x10c
+#define ANACTRL_HIFIPLL_CTRL4 0x110
+#define ANACTRL_HIFIPLL_CTRL5 0x114
+#define ANACTRL_HIFIPLL_CTRL6 0x118
+#define ANACTRL_HIFIPLL_STS 0x11c
+#define ANACTRL_MPLL_CTRL0 0x180
+#define ANACTRL_MPLL_CTRL1 0x184
+#define ANACTRL_MPLL_CTRL2 0x188
+#define ANACTRL_MPLL_CTRL3 0x18c
+#define ANACTRL_MPLL_CTRL4 0x190
+#define ANACTRL_MPLL_CTRL5 0x194
+#define ANACTRL_MPLL_CTRL6 0x198
+#define ANACTRL_MPLL_CTRL7 0x19c
+#define ANACTRL_MPLL_CTRL8 0x1a0
+#define ANACTRL_MPLL_STS 0x1a4
+#define ANACTRL_HDMIPLL_CTRL0 0x1c0
+#define ANACTRL_HDMIPLL_CTRL1 0x1c4
+#define ANACTRL_HDMIPLL_CTRL2 0x1c8
+#define ANACTRL_HDMIPLL_CTRL3 0x1cc
+#define ANACTRL_HDMIPLL_CTRL4 0x1d0
+#define ANACTRL_HDMIPLL_CTRL5 0x1d4
+#define ANACTRL_HDMIPLL_CTRL6 0x1d8
+#define ANACTRL_HDMIPLL_STS 0x1dc
+#define ANACTRL_HDMIPLL_VLOCK 0x1e4
+
+/*
+ * CLKID index values
+ *
+ * These indices are entirely contrived and do not map onto the hardware.
+ * It has now been decided to expose everything by default in the DT header:
+ * include/dt-bindings/clock/amlogic,s4-pll-clkc.h. Only the clocks ids we don't
+ * want to expose, such as the internal muxes and dividers of composite clocks,
+ * will remain defined here.
+ */
+#define CLKID_FIXED_PLL_DCO 0
+#define CLKID_FCLK_DIV2_DIV 2
+#define CLKID_FCLK_DIV3_DIV 4
+#define CLKID_FCLK_DIV4_DIV 6
+#define CLKID_FCLK_DIV5_DIV 8
+#define CLKID_FCLK_DIV7_DIV 10
+#define CLKID_FCLK_DIV2P5_DIV 12
+#define CLKID_GP0_PLL_DCO 14
+#define CLKID_HIFI_PLL_DCO 16
+#define CLKID_HDMI_PLL_DCO 18
+#define CLKID_HDMI_PLL_OD 19
+#define CLKID_MPLL_50M_DIV 21
+#define CLKID_MPLL_PREDIV 23
+#define CLKID_MPLL0_DIV 24
+#define CLKID_MPLL1_DIV 26
+#define CLKID_MPLL2_DIV 28
+#define CLKID_MPLL3_DIV 30
+
+#define NR_PLL_CLKS 32
+/* include the CLKIDs that have been made part of the DT binding */
+#include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
+
+#endif /* __MESON_S4_PLL_H__ */
--
2.33.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH V9 3/4] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver
2023-05-17 7:02 ` [PATCH V9 3/4] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver Yu Tu
@ 2023-06-06 14:02 ` Jerome Brunet
2023-06-08 2:54 ` Yu Tu
2023-06-06 14:34 ` Jerome Brunet
1 sibling, 1 reply; 15+ messages in thread
From: Jerome Brunet @ 2023-06-06 14:02 UTC (permalink / raw)
To: Yu Tu, linux-clk, linux-arm-kernel, linux-amlogic, linux-kernel,
devicetree, Rob Herring, Neil Armstrong, Kevin Hilman,
Michael Turquette, Stephen Boyd, Krzysztof Kozlowski,
Conor Dooley, Martin Blumenstingl
Cc: kelvin.zhang, qi.duan
On Wed 17 May 2023 at 15:02, Yu Tu <yu.tu@amlogic.com> wrote:
> Add the S4 PLL clock controller driver in the s4 SoC family.
>
> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
> ---
> drivers/clk/meson/Kconfig | 13 +
> drivers/clk/meson/Makefile | 1 +
> drivers/clk/meson/s4-pll.c | 907 +++++++++++++++++++++++++++++++++++++
> drivers/clk/meson/s4-pll.h | 87 ++++
> 4 files changed, 1008 insertions(+)
> create mode 100644 drivers/clk/meson/s4-pll.c
> create mode 100644 drivers/clk/meson/s4-pll.h
>
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index fc002c155bc3..a663c90a3f3b 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -115,4 +115,17 @@ config COMMON_CLK_G12A
> help
> Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
> devices, aka g12a. Say Y if you want peripherals to work.
> +
> +config COMMON_CLK_S4_PLL
> + tristate "S4 SoC PLL clock controllers support"
> + depends on ARM64
> + default y
> + select COMMON_CLK_MESON_MPLL
> + select COMMON_CLK_MESON_PLL
> + select COMMON_CLK_MESON_REGMAP
> + help
> + Support for the pll clock controller on Amlogic S805X2 and S905Y4 devices,
> + aka s4. Amlogic S805X2 and S905Y4 devices include AQ222 and AQ229.
> + Say Y if you want the board to work, because plls are the parent of most
> + peripherals.
> endmenu
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index 6eca2a406ee3..376f49cc13f1 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -19,3 +19,4 @@ obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
> obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
> obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
> obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
> +obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o
> diff --git a/drivers/clk/meson/s4-pll.c b/drivers/clk/meson/s4-pll.c
> new file mode 100644
> index 000000000000..c70a33586bcd
> --- /dev/null
> +++ b/drivers/clk/meson/s4-pll.c
> @@ -0,0 +1,907 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Amlogic Meson-S4 PLL Clock Controller Driver
> + *
> + * Copyright (c) 2021 Amlogic, inc.
> + * Author: Yu Tu <yu.tu@amlogic.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mpll.h"
> +#include "clk-pll.h"
> +#include "clk-regmap.h"
> +#include "s4-pll.h"
> +
> +static DEFINE_SPINLOCK(meson_clk_lock);
> +
> +static struct clk_regmap s4_fixed_pll_dco = {
> + .data = &(struct meson_clk_pll_data){
> + .en = {
> + .reg_off = ANACTRL_FIXPLL_CTRL0,
> + .shift = 28,
> + .width = 1,
> + },
> + .m = {
> + .reg_off = ANACTRL_FIXPLL_CTRL0,
> + .shift = 0,
> + .width = 8,
> + },
> + .n = {
> + .reg_off = ANACTRL_FIXPLL_CTRL0,
> + .shift = 10,
> + .width = 5,
> + },
> + .frac = {
> + .reg_off = ANACTRL_FIXPLL_CTRL1,
> + .shift = 0,
> + .width = 17,
> + },
> + .l = {
> + .reg_off = ANACTRL_FIXPLL_CTRL0,
> + .shift = 31,
> + .width = 1,
> + },
> + .rst = {
> + .reg_off = ANACTRL_FIXPLL_CTRL0,
> + .shift = 29,
> + .width = 1,
> + },
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fixed_pll_dco",
> + /*
> + * This clock is a fixed value (4GHz) that is initialized by ROMcode.
Really, isn't it the bl2 doing that ?
> + * This clock won't ever change at runtime.
> + * The chip design determines that this clock cannot be changed after
> + * initialization. To prevent system crash caused by changing
> + * fixed related register in kernel phase. This register is not
> + * writable in the kernel phase.
> + * So we use ro_ops.
> + */
This explanation is good but we don't need mutliple copy/paste or
"please refer" for the same thing. That is very verbose (I think I
already commented on this previously)
Just make one comment block, that clearly explain your intent and that
it applies to the fixed_pll group
> + .ops = &meson_clk_pll_ro_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .fw_name = "xtal", }
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_fixed_pll = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = ANACTRL_FIXPLL_CTRL0,
> + .shift = 16,
> + .width = 2,
> + .flags = CLK_DIVIDER_POWER_OF_TWO,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fixed_pll",
> + /*
> + * This clock is a fixed value (2GHz) that is initialized by ROMcode.
> + * For more information, please refer to s4_fixed_pll_dco.
> + */
> + .ops = &clk_regmap_divider_ro_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fixed_pll_dco.hw
> + },
> + .num_parents = 1,
> + /*
> + * This clock won't ever change at runtime so
> + * CLK_SET_RATE_PARENT is not required
> + */
> + },
> +};
> +
> +static struct clk_fixed_factor s4_fclk_div2_div = {
> + .mult = 1,
> + .div = 2,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div2_div",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_fclk_div2 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_FIXPLL_CTRL1,
> + .bit_idx = 24,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div2",
> + /*
> + * This clock is a fixed value (1GHz) that is initialized by ROMcode.
> + * For more information, please refer to s4_fixed_pll_dco.
> + */
> + .ops = &clk_regmap_gate_ro_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fclk_div2_div.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_fixed_factor s4_fclk_div3_div = {
> + .mult = 1,
> + .div = 3,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div3_div",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_fclk_div3 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_FIXPLL_CTRL1,
> + .bit_idx = 20,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div3",
> + /*
> + * For more information, please refer to s4_fixed_pll_dco.
> + */
> + .ops = &clk_regmap_gate_ro_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fclk_div3_div.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_fixed_factor s4_fclk_div4_div = {
> + .mult = 1,
> + .div = 4,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div4_div",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_fclk_div4 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_FIXPLL_CTRL1,
> + .bit_idx = 21,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div4",
> + /*
> + * For more information, please refer to s4_fixed_pll_dco.
> + */
While div2 and div3 got an explanation from previous SoCs, they others -
like div4/div7/etc ... - have been able to cope with rw ops so far.
Why is the S4 different for all these clocks ?
Requiring RO ops (or fishy clock flags) is usually a sign that a clock
is used without an appropriate driver.
> + .ops = &clk_regmap_gate_ro_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fclk_div4_div.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_fixed_factor s4_fclk_div5_div = {
> + .mult = 1,
> + .div = 5,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div5_div",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_fclk_div5 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_FIXPLL_CTRL1,
> + .bit_idx = 22,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div5",
> + /*
> + * For more information, please refer to s4_fixed_pll_dco.
> + */
> + .ops = &clk_regmap_gate_ro_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fclk_div5_div.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_fixed_factor s4_fclk_div7_div = {
> + .mult = 1,
> + .div = 7,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div7_div",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_fclk_div7 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_FIXPLL_CTRL1,
> + .bit_idx = 23,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div7",
> + /*
> + * For more information, please refer to s4_fixed_pll_dco.
> + */
> + .ops = &clk_regmap_gate_ro_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fclk_div7_div.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_fixed_factor s4_fclk_div2p5_div = {
> + .mult = 2,
> + .div = 5,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div2p5_div",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fixed_pll.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_fclk_div2p5 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_FIXPLL_CTRL1,
> + .bit_idx = 25,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div2p5",
> + /*
> + * For more information, please refer to s4_fixed_pll_dco.
> + */
> + .ops = &clk_regmap_gate_ro_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fclk_div2p5_div.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static const struct pll_mult_range s4_gp0_pll_mult_range = {
> + .min = 125,
> + .max = 250,
> +};
> +
> +/*
> + * Internal gp0 pll emulation configuration parameters
> + */
> +static const struct reg_sequence s4_gp0_init_regs[] = {
> + { .reg = ANACTRL_GP0PLL_CTRL1, .def = 0x00000000 },
> + { .reg = ANACTRL_GP0PLL_CTRL2, .def = 0x00000000 },
> + { .reg = ANACTRL_GP0PLL_CTRL3, .def = 0x48681c00 },
> + { .reg = ANACTRL_GP0PLL_CTRL4, .def = 0x88770290 },
> + { .reg = ANACTRL_GP0PLL_CTRL5, .def = 0x39272000 },
> + { .reg = ANACTRL_GP0PLL_CTRL6, .def = 0x56540000 }
> +};
> +
> +static struct clk_regmap s4_gp0_pll_dco = {
> + .data = &(struct meson_clk_pll_data){
> + .en = {
> + .reg_off = ANACTRL_GP0PLL_CTRL0,
> + .shift = 28,
> + .width = 1,
> + },
> + .m = {
> + .reg_off = ANACTRL_GP0PLL_CTRL0,
> + .shift = 0,
> + .width = 8,
> + },
> + .n = {
> + .reg_off = ANACTRL_GP0PLL_CTRL0,
> + .shift = 10,
> + .width = 5,
> + },
> + .frac = {
> + .reg_off = ANACTRL_GP0PLL_CTRL1,
> + .shift = 0,
> + .width = 17,
> + },
> + .l = {
> + .reg_off = ANACTRL_GP0PLL_CTRL0,
> + .shift = 31,
> + .width = 1,
> + },
> + .rst = {
> + .reg_off = ANACTRL_GP0PLL_CTRL0,
> + .shift = 29,
> + .width = 1,
> + },
> + .range = &s4_gp0_pll_mult_range,
> + .init_regs = s4_gp0_init_regs,
> + .init_count = ARRAY_SIZE(s4_gp0_init_regs),
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "gp0_pll_dco",
> + .ops = &meson_clk_pll_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .fw_name = "xtal", }
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_gp0_pll = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = ANACTRL_GP0PLL_CTRL0,
> + .shift = 16,
> + .width = 3,
> + .flags = (CLK_DIVIDER_POWER_OF_TWO |
> + CLK_DIVIDER_ROUND_CLOSEST),
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "gp0_pll",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_gp0_pll_dco.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +/*
> + * Internal hifi pll emulation configuration parameters
> + */
> +static const struct reg_sequence s4_hifi_init_regs[] = {
> + { .reg = ANACTRL_HIFIPLL_CTRL1, .def = 0x00010e56 },
> + { .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00000000 },
> + { .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x6a285c00 },
> + { .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x65771290 },
> + { .reg = ANACTRL_HIFIPLL_CTRL5, .def = 0x39272000 },
> + { .reg = ANACTRL_HIFIPLL_CTRL6, .def = 0x56540000 }
> +};
> +
> +static struct clk_regmap s4_hifi_pll_dco = {
> + .data = &(struct meson_clk_pll_data){
> + .en = {
> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
> + .shift = 28,
> + .width = 1,
> + },
> + .m = {
> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
> + .shift = 0,
> + .width = 8,
> + },
> + .n = {
> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
> + .shift = 10,
> + .width = 5,
> + },
> + .frac = {
> + .reg_off = ANACTRL_HIFIPLL_CTRL1,
> + .shift = 0,
> + .width = 17,
> + },
> + .l = {
> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
> + .shift = 31,
> + .width = 1,
> + },
> + .rst = {
> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
> + .shift = 29,
> + .width = 1,
> + },
> + .range = &s4_gp0_pll_mult_range,
> + .init_regs = s4_hifi_init_regs,
> + .init_count = ARRAY_SIZE(s4_hifi_init_regs),
> + .flags = CLK_MESON_PLL_ROUND_CLOSEST,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "hifi_pll_dco",
> + .ops = &meson_clk_pll_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .fw_name = "xtal", }
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_hifi_pll = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = ANACTRL_HIFIPLL_CTRL0,
> + .shift = 16,
> + .width = 2,
> + .flags = (CLK_DIVIDER_POWER_OF_TWO |
> + CLK_DIVIDER_ROUND_CLOSEST),
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "hifi_pll",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_hifi_pll_dco.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap s4_hdmi_pll_dco = {
> + .data = &(struct meson_clk_pll_data){
> + .en = {
> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
> + .shift = 28,
> + .width = 1,
> + },
> + .m = {
> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
> + .shift = 0,
> + .width = 8,
> + },
> + .n = {
> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
> + .shift = 10,
> + .width = 5,
> + },
> + .frac = {
> + .reg_off = ANACTRL_HDMIPLL_CTRL1,
> + .shift = 0,
> + .width = 17,
> + },
> + .l = {
> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
> + .shift = 31,
> + .width = 1,
> + },
> + .rst = {
> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
> + .shift = 29,
> + .width = 1,
> + },
> + .range = &s4_gp0_pll_mult_range,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "hdmi_pll_dco",
> + .ops = &meson_clk_pll_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .fw_name = "xtal", }
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_hdmi_pll_od = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = ANACTRL_HDMIPLL_CTRL0,
> + .shift = 16,
> + .width = 4,
> + .flags = CLK_DIVIDER_POWER_OF_TWO,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "hdmi_pll_od",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_hdmi_pll_dco.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap s4_hdmi_pll = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = ANACTRL_HDMIPLL_CTRL0,
> + .shift = 20,
> + .width = 2,
> + .flags = CLK_DIVIDER_POWER_OF_TWO,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "hdmi_pll",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_hdmi_pll_od.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_fixed_factor s4_mpll_50m_div = {
> + .mult = 1,
> + .div = 80,
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll_50m_div",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fixed_pll_dco.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_mpll_50m = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = ANACTRL_FIXPLL_CTRL3,
> + .mask = 0x1,
> + .shift = 5,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll_50m",
> + .ops = &clk_regmap_mux_ro_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .fw_name = "xtal", },
> + { .hw = &s4_mpll_50m_div.hw },
> + },
> + .num_parents = 2,
> + },
> +};
> +
> +static struct clk_fixed_factor s4_mpll_prediv = {
> + .mult = 1,
> + .div = 2,
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll_prediv",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fixed_pll_dco.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static const struct reg_sequence s4_mpll0_init_regs[] = {
> + { .reg = ANACTRL_MPLL_CTRL2, .def = 0x40000033 }
> +};
> +
> +static struct clk_regmap s4_mpll0_div = {
> + .data = &(struct meson_clk_mpll_data){
> + .sdm = {
> + .reg_off = ANACTRL_MPLL_CTRL1,
> + .shift = 0,
> + .width = 14,
> + },
> + .sdm_en = {
> + .reg_off = ANACTRL_MPLL_CTRL1,
> + .shift = 30,
> + .width = 1,
> + },
> + .n2 = {
> + .reg_off = ANACTRL_MPLL_CTRL1,
> + .shift = 20,
> + .width = 9,
> + },
> + .ssen = {
> + .reg_off = ANACTRL_MPLL_CTRL1,
> + .shift = 29,
> + .width = 1,
> + },
> + .lock = &meson_clk_lock,
> + .init_regs = s4_mpll0_init_regs,
> + .init_count = ARRAY_SIZE(s4_mpll0_init_regs),
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll0_div",
> + .ops = &meson_clk_mpll_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_mpll_prediv.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_mpll0 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_MPLL_CTRL1,
> + .bit_idx = 31,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll0",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) { &s4_mpll0_div.hw },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static const struct reg_sequence s4_mpll1_init_regs[] = {
> + { .reg = ANACTRL_MPLL_CTRL4, .def = 0x40000033 }
> +};
> +
> +static struct clk_regmap s4_mpll1_div = {
> + .data = &(struct meson_clk_mpll_data){
> + .sdm = {
> + .reg_off = ANACTRL_MPLL_CTRL3,
> + .shift = 0,
> + .width = 14,
> + },
> + .sdm_en = {
> + .reg_off = ANACTRL_MPLL_CTRL3,
> + .shift = 30,
> + .width = 1,
> + },
> + .n2 = {
> + .reg_off = ANACTRL_MPLL_CTRL3,
> + .shift = 20,
> + .width = 9,
> + },
> + .ssen = {
> + .reg_off = ANACTRL_MPLL_CTRL3,
> + .shift = 29,
> + .width = 1,
> + },
> + .lock = &meson_clk_lock,
> + .init_regs = s4_mpll1_init_regs,
> + .init_count = ARRAY_SIZE(s4_mpll1_init_regs),
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll1_div",
> + .ops = &meson_clk_mpll_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_mpll_prediv.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_mpll1 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_MPLL_CTRL3,
> + .bit_idx = 31,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll1",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) { &s4_mpll1_div.hw },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static const struct reg_sequence s4_mpll2_init_regs[] = {
> + { .reg = ANACTRL_MPLL_CTRL6, .def = 0x40000033 }
> +};
> +
> +static struct clk_regmap s4_mpll2_div = {
> + .data = &(struct meson_clk_mpll_data){
> + .sdm = {
> + .reg_off = ANACTRL_MPLL_CTRL5,
> + .shift = 0,
> + .width = 14,
> + },
> + .sdm_en = {
> + .reg_off = ANACTRL_MPLL_CTRL5,
> + .shift = 30,
> + .width = 1,
> + },
> + .n2 = {
> + .reg_off = ANACTRL_MPLL_CTRL5,
> + .shift = 20,
> + .width = 9,
> + },
> + .ssen = {
> + .reg_off = ANACTRL_MPLL_CTRL5,
> + .shift = 29,
> + .width = 1,
> + },
> + .lock = &meson_clk_lock,
> + .init_regs = s4_mpll2_init_regs,
> + .init_count = ARRAY_SIZE(s4_mpll2_init_regs),
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll2_div",
> + .ops = &meson_clk_mpll_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_mpll_prediv.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_mpll2 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_MPLL_CTRL5,
> + .bit_idx = 31,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll2",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) { &s4_mpll2_div.hw },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static const struct reg_sequence s4_mpll3_init_regs[] = {
> + { .reg = ANACTRL_MPLL_CTRL8, .def = 0x40000033 }
> +};
> +
> +static struct clk_regmap s4_mpll3_div = {
> + .data = &(struct meson_clk_mpll_data){
> + .sdm = {
> + .reg_off = ANACTRL_MPLL_CTRL7,
> + .shift = 0,
> + .width = 14,
> + },
> + .sdm_en = {
> + .reg_off = ANACTRL_MPLL_CTRL7,
> + .shift = 30,
> + .width = 1,
> + },
> + .n2 = {
> + .reg_off = ANACTRL_MPLL_CTRL7,
> + .shift = 20,
> + .width = 9,
> + },
> + .ssen = {
> + .reg_off = ANACTRL_MPLL_CTRL7,
> + .shift = 29,
> + .width = 1,
> + },
> + .lock = &meson_clk_lock,
> + .init_regs = s4_mpll3_init_regs,
> + .init_count = ARRAY_SIZE(s4_mpll3_init_regs),
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll3_div",
> + .ops = &meson_clk_mpll_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_mpll_prediv.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_mpll3 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_MPLL_CTRL7,
> + .bit_idx = 31,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll3",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) { &s4_mpll3_div.hw },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +/* Array of all clocks provided by this provider */
> +static struct clk_hw_onecell_data s4_pll_hw_onecell_data = {
> + .hws = {
> + [CLKID_FIXED_PLL_DCO] = &s4_fixed_pll_dco.hw,
> + [CLKID_FIXED_PLL] = &s4_fixed_pll.hw,
> + [CLKID_FCLK_DIV2_DIV] = &s4_fclk_div2_div.hw,
> + [CLKID_FCLK_DIV2] = &s4_fclk_div2.hw,
> + [CLKID_FCLK_DIV3_DIV] = &s4_fclk_div3_div.hw,
> + [CLKID_FCLK_DIV3] = &s4_fclk_div3.hw,
> + [CLKID_FCLK_DIV4_DIV] = &s4_fclk_div4_div.hw,
> + [CLKID_FCLK_DIV4] = &s4_fclk_div4.hw,
> + [CLKID_FCLK_DIV5_DIV] = &s4_fclk_div5_div.hw,
> + [CLKID_FCLK_DIV5] = &s4_fclk_div5.hw,
> + [CLKID_FCLK_DIV7_DIV] = &s4_fclk_div7_div.hw,
> + [CLKID_FCLK_DIV7] = &s4_fclk_div7.hw,
> + [CLKID_FCLK_DIV2P5_DIV] = &s4_fclk_div2p5_div.hw,
> + [CLKID_FCLK_DIV2P5] = &s4_fclk_div2p5.hw,
> + [CLKID_GP0_PLL_DCO] = &s4_gp0_pll_dco.hw,
> + [CLKID_GP0_PLL] = &s4_gp0_pll.hw,
> + [CLKID_HIFI_PLL_DCO] = &s4_hifi_pll_dco.hw,
> + [CLKID_HIFI_PLL] = &s4_hifi_pll.hw,
> + [CLKID_HDMI_PLL_DCO] = &s4_hdmi_pll_dco.hw,
> + [CLKID_HDMI_PLL_OD] = &s4_hdmi_pll_od.hw,
> + [CLKID_HDMI_PLL] = &s4_hdmi_pll.hw,
> + [CLKID_MPLL_50M_DIV] = &s4_mpll_50m_div.hw,
> + [CLKID_MPLL_50M] = &s4_mpll_50m.hw,
> + [CLKID_MPLL_PREDIV] = &s4_mpll_prediv.hw,
> + [CLKID_MPLL0_DIV] = &s4_mpll0_div.hw,
> + [CLKID_MPLL0] = &s4_mpll0.hw,
> + [CLKID_MPLL1_DIV] = &s4_mpll1_div.hw,
> + [CLKID_MPLL1] = &s4_mpll1.hw,
> + [CLKID_MPLL2_DIV] = &s4_mpll2_div.hw,
> + [CLKID_MPLL2] = &s4_mpll2.hw,
> + [CLKID_MPLL3_DIV] = &s4_mpll3_div.hw,
> + [CLKID_MPLL3] = &s4_mpll3.hw,
> + [NR_PLL_CLKS] = NULL
> + },
> + .num = NR_PLL_CLKS,
> +};
> +
> +static struct clk_regmap *const s4_pll_clk_regmaps[] = {
> + &s4_fixed_pll_dco,
> + &s4_fixed_pll,
> + &s4_fclk_div2,
> + &s4_fclk_div3,
> + &s4_fclk_div4,
> + &s4_fclk_div5,
> + &s4_fclk_div7,
> + &s4_fclk_div2p5,
> + &s4_gp0_pll_dco,
> + &s4_gp0_pll,
> + &s4_hifi_pll_dco,
> + &s4_hifi_pll,
> + &s4_hdmi_pll_dco,
> + &s4_hdmi_pll_od,
> + &s4_hdmi_pll,
> + &s4_mpll_50m,
> + &s4_mpll0_div,
> + &s4_mpll0,
> + &s4_mpll1_div,
> + &s4_mpll1,
> + &s4_mpll2_div,
> + &s4_mpll2,
> + &s4_mpll3_div,
> + &s4_mpll3,
> +};
> +
> +static const struct reg_sequence s4_init_regs[] = {
> + { .reg = ANACTRL_MPLL_CTRL0, .def = 0x00000543 },
> +};
> +
> +static struct regmap_config clkc_regmap_config = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> +};
> +
> +static int meson_s4_pll_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct regmap *regmap;
> + void __iomem *base;
> + int ret, i;
> +
> + base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + regmap = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + ret = regmap_multi_reg_write(regmap, s4_init_regs, ARRAY_SIZE(s4_init_regs));
> + if (ret) {
> + dev_err(dev, "Failed to init registers\n");
> + return ret;
> + }
> +
> + /* Populate regmap for the regmap backed clocks */
> + for (i = 0; i < ARRAY_SIZE(s4_pll_clk_regmaps); i++)
> + s4_pll_clk_regmaps[i]->map = regmap;
> +
> + for (i = 0; i < s4_pll_hw_onecell_data.num; i++) {
> + /* array might be sparse */
> + if (!s4_pll_hw_onecell_data.hws[i])
> + continue;
> +
> + ret = devm_clk_hw_register(dev, s4_pll_hw_onecell_data.hws[i]);
> + if (ret) {
> + dev_err(dev, "Clock registration failed\n");
> + return ret;
> + }
> + }
> +
> + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> + &s4_pll_hw_onecell_data);
> +}
> +
> +static const struct of_device_id clkc_match_table[] = {
> + {
> + .compatible = "amlogic,s4-pll-clkc",
> + },
> + {}
> +};
> +
> +static struct platform_driver s4_driver = {
> + .probe = meson_s4_pll_probe,
> + .driver = {
> + .name = "s4-pll-clkc",
> + .of_match_table = clkc_match_table,
> + },
> +};
> +
> +module_platform_driver(s4_driver);
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/clk/meson/s4-pll.h b/drivers/clk/meson/s4-pll.h
> new file mode 100644
> index 000000000000..021d9f8b2b30
> --- /dev/null
> +++ b/drivers/clk/meson/s4-pll.h
> @@ -0,0 +1,87 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2021 Amlogic, inc.
> + * Author: Yu Tu <yu.tu@amlogic.com>
> + */
> +
> +#ifndef __MESON_S4_PLL_H__
> +#define __MESON_S4_PLL_H__
> +
> +/* ANA_CTRL - Registers */
> +
> +#define ANACTRL_FIXPLL_CTRL0 0x040
> +#define ANACTRL_FIXPLL_CTRL1 0x044
> +#define ANACTRL_FIXPLL_CTRL2 0x048
> +#define ANACTRL_FIXPLL_CTRL3 0x04c
> +#define ANACTRL_FIXPLL_CTRL4 0x050
> +#define ANACTRL_FIXPLL_CTRL5 0x054
> +#define ANACTRL_FIXPLL_CTRL6 0x058
> +#define ANACTRL_FIXPLL_STS 0x05c
> +#define ANACTRL_GP0PLL_CTRL0 0x080
> +#define ANACTRL_GP0PLL_CTRL1 0x084
> +#define ANACTRL_GP0PLL_CTRL2 0x088
> +#define ANACTRL_GP0PLL_CTRL3 0x08c
> +#define ANACTRL_GP0PLL_CTRL4 0x090
> +#define ANACTRL_GP0PLL_CTRL5 0x094
> +#define ANACTRL_GP0PLL_CTRL6 0x098
> +#define ANACTRL_GP0PLL_STS 0x09c
> +#define ANACTRL_HIFIPLL_CTRL0 0x100
> +#define ANACTRL_HIFIPLL_CTRL1 0x104
> +#define ANACTRL_HIFIPLL_CTRL2 0x108
> +#define ANACTRL_HIFIPLL_CTRL3 0x10c
> +#define ANACTRL_HIFIPLL_CTRL4 0x110
> +#define ANACTRL_HIFIPLL_CTRL5 0x114
> +#define ANACTRL_HIFIPLL_CTRL6 0x118
> +#define ANACTRL_HIFIPLL_STS 0x11c
> +#define ANACTRL_MPLL_CTRL0 0x180
> +#define ANACTRL_MPLL_CTRL1 0x184
> +#define ANACTRL_MPLL_CTRL2 0x188
> +#define ANACTRL_MPLL_CTRL3 0x18c
> +#define ANACTRL_MPLL_CTRL4 0x190
> +#define ANACTRL_MPLL_CTRL5 0x194
> +#define ANACTRL_MPLL_CTRL6 0x198
> +#define ANACTRL_MPLL_CTRL7 0x19c
> +#define ANACTRL_MPLL_CTRL8 0x1a0
> +#define ANACTRL_MPLL_STS 0x1a4
> +#define ANACTRL_HDMIPLL_CTRL0 0x1c0
> +#define ANACTRL_HDMIPLL_CTRL1 0x1c4
> +#define ANACTRL_HDMIPLL_CTRL2 0x1c8
> +#define ANACTRL_HDMIPLL_CTRL3 0x1cc
> +#define ANACTRL_HDMIPLL_CTRL4 0x1d0
> +#define ANACTRL_HDMIPLL_CTRL5 0x1d4
> +#define ANACTRL_HDMIPLL_CTRL6 0x1d8
> +#define ANACTRL_HDMIPLL_STS 0x1dc
> +#define ANACTRL_HDMIPLL_VLOCK 0x1e4
> +
> +/*
> + * CLKID index values
> + *
> + * These indices are entirely contrived and do not map onto the hardware.
> + * It has now been decided to expose everything by default in the DT header:
> + * include/dt-bindings/clock/amlogic,s4-pll-clkc.h. Only the clocks ids we don't
> + * want to expose, such as the internal muxes and dividers of composite clocks,
> + * will remain defined here.
> + */
> +#define CLKID_FIXED_PLL_DCO 0
> +#define CLKID_FCLK_DIV2_DIV 2
> +#define CLKID_FCLK_DIV3_DIV 4
> +#define CLKID_FCLK_DIV4_DIV 6
> +#define CLKID_FCLK_DIV5_DIV 8
> +#define CLKID_FCLK_DIV7_DIV 10
> +#define CLKID_FCLK_DIV2P5_DIV 12
> +#define CLKID_GP0_PLL_DCO 14
> +#define CLKID_HIFI_PLL_DCO 16
> +#define CLKID_HDMI_PLL_DCO 18
> +#define CLKID_HDMI_PLL_OD 19
> +#define CLKID_MPLL_50M_DIV 21
> +#define CLKID_MPLL_PREDIV 23
> +#define CLKID_MPLL0_DIV 24
> +#define CLKID_MPLL1_DIV 26
> +#define CLKID_MPLL2_DIV 28
> +#define CLKID_MPLL3_DIV 30
> +
> +#define NR_PLL_CLKS 32
> +/* include the CLKIDs that have been made part of the DT binding */
> +#include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
> +
> +#endif /* __MESON_S4_PLL_H__ */
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH V9 3/4] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver
2023-05-17 7:02 ` [PATCH V9 3/4] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver Yu Tu
2023-06-06 14:02 ` Jerome Brunet
@ 2023-06-06 14:34 ` Jerome Brunet
2023-06-08 2:29 ` Yu Tu
1 sibling, 1 reply; 15+ messages in thread
From: Jerome Brunet @ 2023-06-06 14:34 UTC (permalink / raw)
To: Yu Tu, linux-clk, linux-arm-kernel, linux-amlogic, linux-kernel,
devicetree, Rob Herring, Neil Armstrong, Kevin Hilman,
Michael Turquette, Stephen Boyd, Krzysztof Kozlowski,
Conor Dooley, Martin Blumenstingl
Cc: kelvin.zhang, qi.duan
On Wed 17 May 2023 at 15:02, Yu Tu <yu.tu@amlogic.com> wrote:
> Add the S4 PLL clock controller driver in the s4 SoC family.
>
> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
> ---
> drivers/clk/meson/Kconfig | 13 +
> drivers/clk/meson/Makefile | 1 +
> drivers/clk/meson/s4-pll.c | 907 +++++++++++++++++++++++++++++++++++++
> drivers/clk/meson/s4-pll.h | 87 ++++
> 4 files changed, 1008 insertions(+)
> create mode 100644 drivers/clk/meson/s4-pll.c
> create mode 100644 drivers/clk/meson/s4-pll.h
>
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index fc002c155bc3..a663c90a3f3b 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -115,4 +115,17 @@ config COMMON_CLK_G12A
> help
> Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
> devices, aka g12a. Say Y if you want peripherals to work.
> +
> +config COMMON_CLK_S4_PLL
> + tristate "S4 SoC PLL clock controllers support"
> + depends on ARM64
> + default y
> + select COMMON_CLK_MESON_MPLL
> + select COMMON_CLK_MESON_PLL
> + select COMMON_CLK_MESON_REGMAP
> + help
> + Support for the pll clock controller on Amlogic S805X2 and S905Y4 devices,
> + aka s4. Amlogic S805X2 and S905Y4 devices include AQ222 and AQ229.
I'm confused, what are the AQ222 and AQ229 ? are those SoC or boards
like your reference designs ?
If those are boards, it should not be mentionned here
Also, what about the S905X4 ? is it another SoC family ?
> + Say Y if you want the board to work, because plls are the parent of most
> + peripherals.
> endmenu
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index 6eca2a406ee3..376f49cc13f1 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -19,3 +19,4 @@ obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
> obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
> obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
> obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
> +obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o
> diff --git a/drivers/clk/meson/s4-pll.c b/drivers/clk/meson/s4-pll.c
> new file mode 100644
> index 000000000000..c70a33586bcd
> --- /dev/null
> +++ b/drivers/clk/meson/s4-pll.c
> @@ -0,0 +1,907 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Amlogic Meson-S4 PLL Clock Controller Driver
> + *
> + * Copyright (c) 2021 Amlogic, inc.
> + * Author: Yu Tu <yu.tu@amlogic.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-mpll.h"
> +#include "clk-pll.h"
> +#include "clk-regmap.h"
> +#include "s4-pll.h"
> +
> +static DEFINE_SPINLOCK(meson_clk_lock);
> +
> +static struct clk_regmap s4_fixed_pll_dco = {
> + .data = &(struct meson_clk_pll_data){
> + .en = {
> + .reg_off = ANACTRL_FIXPLL_CTRL0,
> + .shift = 28,
> + .width = 1,
> + },
> + .m = {
> + .reg_off = ANACTRL_FIXPLL_CTRL0,
> + .shift = 0,
> + .width = 8,
> + },
> + .n = {
> + .reg_off = ANACTRL_FIXPLL_CTRL0,
> + .shift = 10,
> + .width = 5,
> + },
> + .frac = {
> + .reg_off = ANACTRL_FIXPLL_CTRL1,
> + .shift = 0,
> + .width = 17,
> + },
> + .l = {
> + .reg_off = ANACTRL_FIXPLL_CTRL0,
> + .shift = 31,
> + .width = 1,
> + },
> + .rst = {
> + .reg_off = ANACTRL_FIXPLL_CTRL0,
> + .shift = 29,
> + .width = 1,
> + },
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fixed_pll_dco",
> + /*
> + * This clock is a fixed value (4GHz) that is initialized by ROMcode.
> + * This clock won't ever change at runtime.
> + * The chip design determines that this clock cannot be changed after
> + * initialization. To prevent system crash caused by changing
> + * fixed related register in kernel phase. This register is not
> + * writable in the kernel phase.
> + * So we use ro_ops.
> + */
> + .ops = &meson_clk_pll_ro_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .fw_name = "xtal", }
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_fixed_pll = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = ANACTRL_FIXPLL_CTRL0,
> + .shift = 16,
> + .width = 2,
> + .flags = CLK_DIVIDER_POWER_OF_TWO,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fixed_pll",
> + /*
> + * This clock is a fixed value (2GHz) that is initialized by ROMcode.
> + * For more information, please refer to s4_fixed_pll_dco.
> + */
> + .ops = &clk_regmap_divider_ro_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fixed_pll_dco.hw
> + },
> + .num_parents = 1,
> + /*
> + * This clock won't ever change at runtime so
> + * CLK_SET_RATE_PARENT is not required
> + */
> + },
> +};
> +
> +static struct clk_fixed_factor s4_fclk_div2_div = {
> + .mult = 1,
> + .div = 2,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div2_div",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_fclk_div2 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_FIXPLL_CTRL1,
> + .bit_idx = 24,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div2",
> + /*
> + * This clock is a fixed value (1GHz) that is initialized by ROMcode.
> + * For more information, please refer to s4_fixed_pll_dco.
> + */
> + .ops = &clk_regmap_gate_ro_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fclk_div2_div.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_fixed_factor s4_fclk_div3_div = {
> + .mult = 1,
> + .div = 3,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div3_div",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_fclk_div3 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_FIXPLL_CTRL1,
> + .bit_idx = 20,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div3",
> + /*
> + * For more information, please refer to s4_fixed_pll_dco.
> + */
> + .ops = &clk_regmap_gate_ro_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fclk_div3_div.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_fixed_factor s4_fclk_div4_div = {
> + .mult = 1,
> + .div = 4,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div4_div",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_fclk_div4 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_FIXPLL_CTRL1,
> + .bit_idx = 21,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div4",
> + /*
> + * For more information, please refer to s4_fixed_pll_dco.
> + */
> + .ops = &clk_regmap_gate_ro_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fclk_div4_div.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_fixed_factor s4_fclk_div5_div = {
> + .mult = 1,
> + .div = 5,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div5_div",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_fclk_div5 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_FIXPLL_CTRL1,
> + .bit_idx = 22,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div5",
> + /*
> + * For more information, please refer to s4_fixed_pll_dco.
> + */
> + .ops = &clk_regmap_gate_ro_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fclk_div5_div.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_fixed_factor s4_fclk_div7_div = {
> + .mult = 1,
> + .div = 7,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div7_div",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_fclk_div7 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_FIXPLL_CTRL1,
> + .bit_idx = 23,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div7",
> + /*
> + * For more information, please refer to s4_fixed_pll_dco.
> + */
> + .ops = &clk_regmap_gate_ro_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fclk_div7_div.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_fixed_factor s4_fclk_div2p5_div = {
> + .mult = 2,
> + .div = 5,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div2p5_div",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fixed_pll.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_fclk_div2p5 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_FIXPLL_CTRL1,
> + .bit_idx = 25,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div2p5",
> + /*
> + * For more information, please refer to s4_fixed_pll_dco.
> + */
> + .ops = &clk_regmap_gate_ro_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fclk_div2p5_div.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static const struct pll_mult_range s4_gp0_pll_mult_range = {
> + .min = 125,
> + .max = 250,
> +};
> +
> +/*
> + * Internal gp0 pll emulation configuration parameters
> + */
> +static const struct reg_sequence s4_gp0_init_regs[] = {
> + { .reg = ANACTRL_GP0PLL_CTRL1, .def = 0x00000000 },
> + { .reg = ANACTRL_GP0PLL_CTRL2, .def = 0x00000000 },
> + { .reg = ANACTRL_GP0PLL_CTRL3, .def = 0x48681c00 },
> + { .reg = ANACTRL_GP0PLL_CTRL4, .def = 0x88770290 },
> + { .reg = ANACTRL_GP0PLL_CTRL5, .def = 0x39272000 },
> + { .reg = ANACTRL_GP0PLL_CTRL6, .def = 0x56540000 }
> +};
> +
> +static struct clk_regmap s4_gp0_pll_dco = {
> + .data = &(struct meson_clk_pll_data){
> + .en = {
> + .reg_off = ANACTRL_GP0PLL_CTRL0,
> + .shift = 28,
> + .width = 1,
> + },
> + .m = {
> + .reg_off = ANACTRL_GP0PLL_CTRL0,
> + .shift = 0,
> + .width = 8,
> + },
> + .n = {
> + .reg_off = ANACTRL_GP0PLL_CTRL0,
> + .shift = 10,
> + .width = 5,
> + },
> + .frac = {
> + .reg_off = ANACTRL_GP0PLL_CTRL1,
> + .shift = 0,
> + .width = 17,
> + },
> + .l = {
> + .reg_off = ANACTRL_GP0PLL_CTRL0,
> + .shift = 31,
> + .width = 1,
> + },
> + .rst = {
> + .reg_off = ANACTRL_GP0PLL_CTRL0,
> + .shift = 29,
> + .width = 1,
> + },
> + .range = &s4_gp0_pll_mult_range,
> + .init_regs = s4_gp0_init_regs,
> + .init_count = ARRAY_SIZE(s4_gp0_init_regs),
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "gp0_pll_dco",
> + .ops = &meson_clk_pll_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .fw_name = "xtal", }
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_gp0_pll = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = ANACTRL_GP0PLL_CTRL0,
> + .shift = 16,
> + .width = 3,
> + .flags = (CLK_DIVIDER_POWER_OF_TWO |
> + CLK_DIVIDER_ROUND_CLOSEST),
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "gp0_pll",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_gp0_pll_dco.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +/*
> + * Internal hifi pll emulation configuration parameters
> + */
> +static const struct reg_sequence s4_hifi_init_regs[] = {
> + { .reg = ANACTRL_HIFIPLL_CTRL1, .def = 0x00010e56 },
> + { .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00000000 },
> + { .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x6a285c00 },
> + { .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x65771290 },
> + { .reg = ANACTRL_HIFIPLL_CTRL5, .def = 0x39272000 },
> + { .reg = ANACTRL_HIFIPLL_CTRL6, .def = 0x56540000 }
> +};
> +
> +static struct clk_regmap s4_hifi_pll_dco = {
> + .data = &(struct meson_clk_pll_data){
> + .en = {
> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
> + .shift = 28,
> + .width = 1,
> + },
> + .m = {
> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
> + .shift = 0,
> + .width = 8,
> + },
> + .n = {
> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
> + .shift = 10,
> + .width = 5,
> + },
> + .frac = {
> + .reg_off = ANACTRL_HIFIPLL_CTRL1,
> + .shift = 0,
> + .width = 17,
> + },
> + .l = {
> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
> + .shift = 31,
> + .width = 1,
> + },
> + .rst = {
> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
> + .shift = 29,
> + .width = 1,
> + },
> + .range = &s4_gp0_pll_mult_range,
> + .init_regs = s4_hifi_init_regs,
> + .init_count = ARRAY_SIZE(s4_hifi_init_regs),
> + .flags = CLK_MESON_PLL_ROUND_CLOSEST,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "hifi_pll_dco",
> + .ops = &meson_clk_pll_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .fw_name = "xtal", }
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_hifi_pll = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = ANACTRL_HIFIPLL_CTRL0,
> + .shift = 16,
> + .width = 2,
> + .flags = (CLK_DIVIDER_POWER_OF_TWO |
> + CLK_DIVIDER_ROUND_CLOSEST),
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "hifi_pll",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_hifi_pll_dco.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap s4_hdmi_pll_dco = {
> + .data = &(struct meson_clk_pll_data){
> + .en = {
> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
> + .shift = 28,
> + .width = 1,
> + },
> + .m = {
> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
> + .shift = 0,
> + .width = 8,
> + },
> + .n = {
> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
> + .shift = 10,
> + .width = 5,
> + },
> + .frac = {
> + .reg_off = ANACTRL_HDMIPLL_CTRL1,
> + .shift = 0,
> + .width = 17,
> + },
> + .l = {
> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
> + .shift = 31,
> + .width = 1,
> + },
> + .rst = {
> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
> + .shift = 29,
> + .width = 1,
> + },
> + .range = &s4_gp0_pll_mult_range,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "hdmi_pll_dco",
> + .ops = &meson_clk_pll_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .fw_name = "xtal", }
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_hdmi_pll_od = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = ANACTRL_HDMIPLL_CTRL0,
> + .shift = 16,
> + .width = 4,
> + .flags = CLK_DIVIDER_POWER_OF_TWO,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "hdmi_pll_od",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_hdmi_pll_dco.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap s4_hdmi_pll = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = ANACTRL_HDMIPLL_CTRL0,
> + .shift = 20,
> + .width = 2,
> + .flags = CLK_DIVIDER_POWER_OF_TWO,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "hdmi_pll",
> + .ops = &clk_regmap_divider_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_hdmi_pll_od.hw
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_fixed_factor s4_mpll_50m_div = {
> + .mult = 1,
> + .div = 80,
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll_50m_div",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fixed_pll_dco.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_mpll_50m = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = ANACTRL_FIXPLL_CTRL3,
> + .mask = 0x1,
> + .shift = 5,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll_50m",
> + .ops = &clk_regmap_mux_ro_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .fw_name = "xtal", },
> + { .hw = &s4_mpll_50m_div.hw },
> + },
> + .num_parents = 2,
> + },
> +};
> +
> +static struct clk_fixed_factor s4_mpll_prediv = {
> + .mult = 1,
> + .div = 2,
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll_prediv",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fixed_pll_dco.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static const struct reg_sequence s4_mpll0_init_regs[] = {
> + { .reg = ANACTRL_MPLL_CTRL2, .def = 0x40000033 }
> +};
> +
> +static struct clk_regmap s4_mpll0_div = {
> + .data = &(struct meson_clk_mpll_data){
> + .sdm = {
> + .reg_off = ANACTRL_MPLL_CTRL1,
> + .shift = 0,
> + .width = 14,
> + },
> + .sdm_en = {
> + .reg_off = ANACTRL_MPLL_CTRL1,
> + .shift = 30,
> + .width = 1,
> + },
> + .n2 = {
> + .reg_off = ANACTRL_MPLL_CTRL1,
> + .shift = 20,
> + .width = 9,
> + },
> + .ssen = {
> + .reg_off = ANACTRL_MPLL_CTRL1,
> + .shift = 29,
> + .width = 1,
> + },
> + .lock = &meson_clk_lock,
> + .init_regs = s4_mpll0_init_regs,
> + .init_count = ARRAY_SIZE(s4_mpll0_init_regs),
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll0_div",
> + .ops = &meson_clk_mpll_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_mpll_prediv.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_mpll0 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_MPLL_CTRL1,
> + .bit_idx = 31,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll0",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) { &s4_mpll0_div.hw },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static const struct reg_sequence s4_mpll1_init_regs[] = {
> + { .reg = ANACTRL_MPLL_CTRL4, .def = 0x40000033 }
> +};
> +
> +static struct clk_regmap s4_mpll1_div = {
> + .data = &(struct meson_clk_mpll_data){
> + .sdm = {
> + .reg_off = ANACTRL_MPLL_CTRL3,
> + .shift = 0,
> + .width = 14,
> + },
> + .sdm_en = {
> + .reg_off = ANACTRL_MPLL_CTRL3,
> + .shift = 30,
> + .width = 1,
> + },
> + .n2 = {
> + .reg_off = ANACTRL_MPLL_CTRL3,
> + .shift = 20,
> + .width = 9,
> + },
> + .ssen = {
> + .reg_off = ANACTRL_MPLL_CTRL3,
> + .shift = 29,
> + .width = 1,
> + },
> + .lock = &meson_clk_lock,
> + .init_regs = s4_mpll1_init_regs,
> + .init_count = ARRAY_SIZE(s4_mpll1_init_regs),
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll1_div",
> + .ops = &meson_clk_mpll_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_mpll_prediv.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_mpll1 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_MPLL_CTRL3,
> + .bit_idx = 31,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll1",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) { &s4_mpll1_div.hw },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static const struct reg_sequence s4_mpll2_init_regs[] = {
> + { .reg = ANACTRL_MPLL_CTRL6, .def = 0x40000033 }
> +};
> +
> +static struct clk_regmap s4_mpll2_div = {
> + .data = &(struct meson_clk_mpll_data){
> + .sdm = {
> + .reg_off = ANACTRL_MPLL_CTRL5,
> + .shift = 0,
> + .width = 14,
> + },
> + .sdm_en = {
> + .reg_off = ANACTRL_MPLL_CTRL5,
> + .shift = 30,
> + .width = 1,
> + },
> + .n2 = {
> + .reg_off = ANACTRL_MPLL_CTRL5,
> + .shift = 20,
> + .width = 9,
> + },
> + .ssen = {
> + .reg_off = ANACTRL_MPLL_CTRL5,
> + .shift = 29,
> + .width = 1,
> + },
> + .lock = &meson_clk_lock,
> + .init_regs = s4_mpll2_init_regs,
> + .init_count = ARRAY_SIZE(s4_mpll2_init_regs),
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll2_div",
> + .ops = &meson_clk_mpll_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_mpll_prediv.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_mpll2 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_MPLL_CTRL5,
> + .bit_idx = 31,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll2",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) { &s4_mpll2_div.hw },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static const struct reg_sequence s4_mpll3_init_regs[] = {
> + { .reg = ANACTRL_MPLL_CTRL8, .def = 0x40000033 }
> +};
> +
> +static struct clk_regmap s4_mpll3_div = {
> + .data = &(struct meson_clk_mpll_data){
> + .sdm = {
> + .reg_off = ANACTRL_MPLL_CTRL7,
> + .shift = 0,
> + .width = 14,
> + },
> + .sdm_en = {
> + .reg_off = ANACTRL_MPLL_CTRL7,
> + .shift = 30,
> + .width = 1,
> + },
> + .n2 = {
> + .reg_off = ANACTRL_MPLL_CTRL7,
> + .shift = 20,
> + .width = 9,
> + },
> + .ssen = {
> + .reg_off = ANACTRL_MPLL_CTRL7,
> + .shift = 29,
> + .width = 1,
> + },
> + .lock = &meson_clk_lock,
> + .init_regs = s4_mpll3_init_regs,
> + .init_count = ARRAY_SIZE(s4_mpll3_init_regs),
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll3_div",
> + .ops = &meson_clk_mpll_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_mpll_prediv.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_mpll3 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_MPLL_CTRL7,
> + .bit_idx = 31,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll3",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) { &s4_mpll3_div.hw },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +/* Array of all clocks provided by this provider */
> +static struct clk_hw_onecell_data s4_pll_hw_onecell_data = {
> + .hws = {
> + [CLKID_FIXED_PLL_DCO] = &s4_fixed_pll_dco.hw,
> + [CLKID_FIXED_PLL] = &s4_fixed_pll.hw,
> + [CLKID_FCLK_DIV2_DIV] = &s4_fclk_div2_div.hw,
> + [CLKID_FCLK_DIV2] = &s4_fclk_div2.hw,
> + [CLKID_FCLK_DIV3_DIV] = &s4_fclk_div3_div.hw,
> + [CLKID_FCLK_DIV3] = &s4_fclk_div3.hw,
> + [CLKID_FCLK_DIV4_DIV] = &s4_fclk_div4_div.hw,
> + [CLKID_FCLK_DIV4] = &s4_fclk_div4.hw,
> + [CLKID_FCLK_DIV5_DIV] = &s4_fclk_div5_div.hw,
> + [CLKID_FCLK_DIV5] = &s4_fclk_div5.hw,
> + [CLKID_FCLK_DIV7_DIV] = &s4_fclk_div7_div.hw,
> + [CLKID_FCLK_DIV7] = &s4_fclk_div7.hw,
> + [CLKID_FCLK_DIV2P5_DIV] = &s4_fclk_div2p5_div.hw,
> + [CLKID_FCLK_DIV2P5] = &s4_fclk_div2p5.hw,
> + [CLKID_GP0_PLL_DCO] = &s4_gp0_pll_dco.hw,
> + [CLKID_GP0_PLL] = &s4_gp0_pll.hw,
> + [CLKID_HIFI_PLL_DCO] = &s4_hifi_pll_dco.hw,
> + [CLKID_HIFI_PLL] = &s4_hifi_pll.hw,
> + [CLKID_HDMI_PLL_DCO] = &s4_hdmi_pll_dco.hw,
> + [CLKID_HDMI_PLL_OD] = &s4_hdmi_pll_od.hw,
> + [CLKID_HDMI_PLL] = &s4_hdmi_pll.hw,
> + [CLKID_MPLL_50M_DIV] = &s4_mpll_50m_div.hw,
> + [CLKID_MPLL_50M] = &s4_mpll_50m.hw,
> + [CLKID_MPLL_PREDIV] = &s4_mpll_prediv.hw,
> + [CLKID_MPLL0_DIV] = &s4_mpll0_div.hw,
> + [CLKID_MPLL0] = &s4_mpll0.hw,
> + [CLKID_MPLL1_DIV] = &s4_mpll1_div.hw,
> + [CLKID_MPLL1] = &s4_mpll1.hw,
> + [CLKID_MPLL2_DIV] = &s4_mpll2_div.hw,
> + [CLKID_MPLL2] = &s4_mpll2.hw,
> + [CLKID_MPLL3_DIV] = &s4_mpll3_div.hw,
> + [CLKID_MPLL3] = &s4_mpll3.hw,
> + [NR_PLL_CLKS] = NULL
> + },
> + .num = NR_PLL_CLKS,
> +};
> +
> +static struct clk_regmap *const s4_pll_clk_regmaps[] = {
> + &s4_fixed_pll_dco,
> + &s4_fixed_pll,
> + &s4_fclk_div2,
> + &s4_fclk_div3,
> + &s4_fclk_div4,
> + &s4_fclk_div5,
> + &s4_fclk_div7,
> + &s4_fclk_div2p5,
> + &s4_gp0_pll_dco,
> + &s4_gp0_pll,
> + &s4_hifi_pll_dco,
> + &s4_hifi_pll,
> + &s4_hdmi_pll_dco,
> + &s4_hdmi_pll_od,
> + &s4_hdmi_pll,
> + &s4_mpll_50m,
> + &s4_mpll0_div,
> + &s4_mpll0,
> + &s4_mpll1_div,
> + &s4_mpll1,
> + &s4_mpll2_div,
> + &s4_mpll2,
> + &s4_mpll3_div,
> + &s4_mpll3,
> +};
> +
> +static const struct reg_sequence s4_init_regs[] = {
> + { .reg = ANACTRL_MPLL_CTRL0, .def = 0x00000543 },
> +};
> +
> +static struct regmap_config clkc_regmap_config = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> +};
> +
> +static int meson_s4_pll_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct regmap *regmap;
> + void __iomem *base;
> + int ret, i;
> +
> + base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + regmap = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + ret = regmap_multi_reg_write(regmap, s4_init_regs, ARRAY_SIZE(s4_init_regs));
> + if (ret) {
> + dev_err(dev, "Failed to init registers\n");
> + return ret;
> + }
> +
> + /* Populate regmap for the regmap backed clocks */
> + for (i = 0; i < ARRAY_SIZE(s4_pll_clk_regmaps); i++)
> + s4_pll_clk_regmaps[i]->map = regmap;
> +
> + for (i = 0; i < s4_pll_hw_onecell_data.num; i++) {
> + /* array might be sparse */
> + if (!s4_pll_hw_onecell_data.hws[i])
> + continue;
> +
> + ret = devm_clk_hw_register(dev, s4_pll_hw_onecell_data.hws[i]);
> + if (ret) {
> + dev_err(dev, "Clock registration failed\n");
> + return ret;
> + }
> + }
> +
> + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
> + &s4_pll_hw_onecell_data);
> +}
> +
> +static const struct of_device_id clkc_match_table[] = {
> + {
> + .compatible = "amlogic,s4-pll-clkc",
> + },
> + {}
> +};
> +
> +static struct platform_driver s4_driver = {
> + .probe = meson_s4_pll_probe,
> + .driver = {
> + .name = "s4-pll-clkc",
> + .of_match_table = clkc_match_table,
> + },
> +};
> +
> +module_platform_driver(s4_driver);
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/clk/meson/s4-pll.h b/drivers/clk/meson/s4-pll.h
> new file mode 100644
> index 000000000000..021d9f8b2b30
> --- /dev/null
> +++ b/drivers/clk/meson/s4-pll.h
> @@ -0,0 +1,87 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2021 Amlogic, inc.
> + * Author: Yu Tu <yu.tu@amlogic.com>
> + */
> +
> +#ifndef __MESON_S4_PLL_H__
> +#define __MESON_S4_PLL_H__
> +
> +/* ANA_CTRL - Registers */
> +
> +#define ANACTRL_FIXPLL_CTRL0 0x040
> +#define ANACTRL_FIXPLL_CTRL1 0x044
> +#define ANACTRL_FIXPLL_CTRL2 0x048
> +#define ANACTRL_FIXPLL_CTRL3 0x04c
> +#define ANACTRL_FIXPLL_CTRL4 0x050
> +#define ANACTRL_FIXPLL_CTRL5 0x054
> +#define ANACTRL_FIXPLL_CTRL6 0x058
> +#define ANACTRL_FIXPLL_STS 0x05c
> +#define ANACTRL_GP0PLL_CTRL0 0x080
> +#define ANACTRL_GP0PLL_CTRL1 0x084
> +#define ANACTRL_GP0PLL_CTRL2 0x088
> +#define ANACTRL_GP0PLL_CTRL3 0x08c
> +#define ANACTRL_GP0PLL_CTRL4 0x090
> +#define ANACTRL_GP0PLL_CTRL5 0x094
> +#define ANACTRL_GP0PLL_CTRL6 0x098
> +#define ANACTRL_GP0PLL_STS 0x09c
> +#define ANACTRL_HIFIPLL_CTRL0 0x100
> +#define ANACTRL_HIFIPLL_CTRL1 0x104
> +#define ANACTRL_HIFIPLL_CTRL2 0x108
> +#define ANACTRL_HIFIPLL_CTRL3 0x10c
> +#define ANACTRL_HIFIPLL_CTRL4 0x110
> +#define ANACTRL_HIFIPLL_CTRL5 0x114
> +#define ANACTRL_HIFIPLL_CTRL6 0x118
> +#define ANACTRL_HIFIPLL_STS 0x11c
> +#define ANACTRL_MPLL_CTRL0 0x180
> +#define ANACTRL_MPLL_CTRL1 0x184
> +#define ANACTRL_MPLL_CTRL2 0x188
> +#define ANACTRL_MPLL_CTRL3 0x18c
> +#define ANACTRL_MPLL_CTRL4 0x190
> +#define ANACTRL_MPLL_CTRL5 0x194
> +#define ANACTRL_MPLL_CTRL6 0x198
> +#define ANACTRL_MPLL_CTRL7 0x19c
> +#define ANACTRL_MPLL_CTRL8 0x1a0
> +#define ANACTRL_MPLL_STS 0x1a4
> +#define ANACTRL_HDMIPLL_CTRL0 0x1c0
> +#define ANACTRL_HDMIPLL_CTRL1 0x1c4
> +#define ANACTRL_HDMIPLL_CTRL2 0x1c8
> +#define ANACTRL_HDMIPLL_CTRL3 0x1cc
> +#define ANACTRL_HDMIPLL_CTRL4 0x1d0
> +#define ANACTRL_HDMIPLL_CTRL5 0x1d4
> +#define ANACTRL_HDMIPLL_CTRL6 0x1d8
> +#define ANACTRL_HDMIPLL_STS 0x1dc
> +#define ANACTRL_HDMIPLL_VLOCK 0x1e4
> +
> +/*
> + * CLKID index values
> + *
> + * These indices are entirely contrived and do not map onto the hardware.
> + * It has now been decided to expose everything by default in the DT header:
> + * include/dt-bindings/clock/amlogic,s4-pll-clkc.h. Only the clocks ids we don't
> + * want to expose, such as the internal muxes and dividers of composite clocks,
> + * will remain defined here.
> + */
> +#define CLKID_FIXED_PLL_DCO 0
> +#define CLKID_FCLK_DIV2_DIV 2
> +#define CLKID_FCLK_DIV3_DIV 4
> +#define CLKID_FCLK_DIV4_DIV 6
> +#define CLKID_FCLK_DIV5_DIV 8
> +#define CLKID_FCLK_DIV7_DIV 10
> +#define CLKID_FCLK_DIV2P5_DIV 12
> +#define CLKID_GP0_PLL_DCO 14
> +#define CLKID_HIFI_PLL_DCO 16
> +#define CLKID_HDMI_PLL_DCO 18
> +#define CLKID_HDMI_PLL_OD 19
> +#define CLKID_MPLL_50M_DIV 21
> +#define CLKID_MPLL_PREDIV 23
> +#define CLKID_MPLL0_DIV 24
> +#define CLKID_MPLL1_DIV 26
> +#define CLKID_MPLL2_DIV 28
> +#define CLKID_MPLL3_DIV 30
> +
> +#define NR_PLL_CLKS 32
> +/* include the CLKIDs that have been made part of the DT binding */
> +#include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
> +
> +#endif /* __MESON_S4_PLL_H__ */
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH V9 4/4] clk: meson: s4: add support for Amlogic S4 SoC peripheral clock controller
[not found] ` <1jwn0g39t2.fsf@starbuckisacylon.baylibre.com>
@ 2023-06-06 15:38 ` Dmitry Rokosov
2023-06-08 3:26 ` Yu Tu
0 siblings, 1 reply; 15+ messages in thread
From: Dmitry Rokosov @ 2023-06-06 15:38 UTC (permalink / raw)
To: Yu Tu
Cc: Jerome Brunet, linux-clk, linux-arm-kernel, linux-amlogic,
linux-kernel, devicetree, Rob Herring, Neil Armstrong,
Kevin Hilman, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Conor Dooley, Martin Blumenstingl,
kelvin.zhang, qi.duan
Hello Yu,
On Tue, Jun 06, 2023 at 04:38:15PM +0200, Jerome Brunet wrote:
>
> On Wed 17 May 2023 at 15:02, Yu Tu <yu.tu@amlogic.com> wrote:
>
> > Add the peripherals clock controller driver in the s4 SoC family.
> >
> > Signed-off-by: Yu Tu <yu.tu@amlogic.com>
> > ---
> > drivers/clk/meson/Kconfig | 12 +
> > drivers/clk/meson/Makefile | 1 +
> > drivers/clk/meson/s4-peripherals.c | 3830 ++++++++++++++++++++++++++++
> > drivers/clk/meson/s4-peripherals.h | 217 ++
> > 4 files changed, 4060 insertions(+)
> > create mode 100644 drivers/clk/meson/s4-peripherals.c
> > create mode 100644 drivers/clk/meson/s4-peripherals.h
> >
> > diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> > index a663c90a3f3b..a6eb9fa15c74 100644
> > --- a/drivers/clk/meson/Kconfig
> > +++ b/drivers/clk/meson/Kconfig
> > @@ -128,4 +128,16 @@ config COMMON_CLK_S4_PLL
> > aka s4. Amlogic S805X2 and S905Y4 devices include AQ222 and AQ229.
> > Say Y if you want the board to work, because plls are the parent of most
> > peripherals.
> > +
> > +config COMMON_CLK_S4
> > + tristate "S4 SoC Peripherals clock controllers support"
> > + depends on ARM64
> > + default y
> > + select COMMON_CLK_MESON_REGMAP
> > + select COMMON_CLK_MESON_DUALDIV
> > + select COMMON_CLK_MESON_VID_PLL_DIV
> > + help
> > + Support for the Peripherals clock controller on Amlogic S805X2 and S905Y4
> > + devices, aka s4. Amlogic S805X2 and S905Y4 devices include AQ222 and AQ229.
> > + Say Y if you want peripherals to work.
> > endmenu
[...]
> > +static struct clk_regmap s4_rtc_32k_by_oscin = {
> > + .data = &(struct clk_regmap_gate_data){
> > + .offset = CLKCTRL_RTC_BY_OSCIN_CTRL0,
> > + .bit_idx = 30,
> > + },
> > + .hw.init = &(struct clk_init_data) {
> > + .name = "rtc_32k_by_oscin",
> > + .ops = &clk_regmap_gate_ops,
> > + .parent_hws = (const struct clk_hw *[]) {
> > + &s4_rtc_32k_by_oscin_sel.hw
> > + },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + },
> > +};
> > +
> > +/*
> > + * This RTC clock can be supplied by an external 32KHz crystal oscillator.
> > + * If it is used, it should be documented in using fw_name and documented in the
> > + * Bindings. Not currently in use on this board.
> > + */
>
> This is confusing and not really helpful
> What you describe here is simply the purpose of fw_name ... so it does
> not warrant a specific comment
>
> > +static const struct clk_parent_data rtc_clk_sel_parent_data[] = {
> > + { .hw = &s4_rtc_32k_by_oscin.hw },
> > + { .hw = &s4_rtc_32k_by_oscin_div.hw },
> > + { .fw_name = "ext_32k", }
> > +};
> > +
> > +/*
> > + * All clocks that can be inherited from a more accurate RTC clock are marked
> > + * with the CLK_SET_RATE_NO_REPARENT flag. This is because in certain
> > + * situations, we may need to freeze their parent. The parent setup of these
> > + * clocks should be located on the device tree side.
> > + */
>
> It looks like the consensus is that CLK_SET_RATE_NO_REPARENT is not
> required. Please have at look at the discussion between Dmitry and
> Martin for the a1 controller
>
I hope below links will be helpful for you:
CLK_SET_RATE_NO_REPARENT IRC discussion:
https://libera.irclog.whitequark.org/linux-amlogic/2023-05-18
Clock driver LKML discussion about CLK_SET_RATE_NO_REPARENT:
https://lore.kernel.org/all/20230530120640.irugyrio3qa7czjy@CAB-WSD-L081021/
https://lore.kernel.org/all/20230524092750.ldm362chnpkwkcj4@CAB-WSD-L081021/
PWM discussion about special RTC case:
https://lore.kernel.org/all/20230522133739.7tc35zr2npsysopd@CAB-WSD-L081021/
And I apologize for any confusion I may have caused in our previous
discussion. I want to clarify that I have updated the implementation
of CLK_SET_RATE_NO_REPARENT after discussing it with Martin...
[...]
--
Thank you,
Dmitry
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH V9 3/4] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver
2023-06-06 14:34 ` Jerome Brunet
@ 2023-06-08 2:29 ` Yu Tu
0 siblings, 0 replies; 15+ messages in thread
From: Yu Tu @ 2023-06-08 2:29 UTC (permalink / raw)
To: Jerome Brunet, linux-clk, linux-arm-kernel, linux-amlogic,
linux-kernel, devicetree, Rob Herring, Neil Armstrong,
Kevin Hilman, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Conor Dooley, Martin Blumenstingl
Cc: kelvin.zhang, qi.duan
On 2023/6/6 22:34, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On Wed 17 May 2023 at 15:02, Yu Tu <yu.tu@amlogic.com> wrote:
>
>> Add the S4 PLL clock controller driver in the s4 SoC family.
>>
>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>> ---
>> drivers/clk/meson/Kconfig | 13 +
>> drivers/clk/meson/Makefile | 1 +
>> drivers/clk/meson/s4-pll.c | 907 +++++++++++++++++++++++++++++++++++++
>> drivers/clk/meson/s4-pll.h | 87 ++++
>> 4 files changed, 1008 insertions(+)
>> create mode 100644 drivers/clk/meson/s4-pll.c
>> create mode 100644 drivers/clk/meson/s4-pll.h
>>
>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>> index fc002c155bc3..a663c90a3f3b 100644
>> --- a/drivers/clk/meson/Kconfig
>> +++ b/drivers/clk/meson/Kconfig
>> @@ -115,4 +115,17 @@ config COMMON_CLK_G12A
>> help
>> Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
>> devices, aka g12a. Say Y if you want peripherals to work.
>> +
>> +config COMMON_CLK_S4_PLL
>> + tristate "S4 SoC PLL clock controllers support"
>> + depends on ARM64
>> + default y
>> + select COMMON_CLK_MESON_MPLL
>> + select COMMON_CLK_MESON_PLL
>> + select COMMON_CLK_MESON_REGMAP
>> + help
>> + Support for the pll clock controller on Amlogic S805X2 and S905Y4 devices,
>> + aka s4. Amlogic S805X2 and S905Y4 devices include AQ222 and AQ229.
>
> I'm confused, what are the AQ222 and AQ229 ? are those SoC or boards
> like your reference designs ?
>
> If those are boards, it should not be mentionned here
Okay. I will reomove those boards name in next version.
>
> Also, what about the S905X4 ? is it another SoC family ?
Yes. You're right.
>
>> + Say Y if you want the board to work, because plls are the parent of most
>> + peripherals.
>> endmenu
>> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
>> index 6eca2a406ee3..376f49cc13f1 100644
>> --- a/drivers/clk/meson/Makefile
>> +++ b/drivers/clk/meson/Makefile
>> @@ -19,3 +19,4 @@ obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
>> obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
>> obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
>> obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
>> +obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o
>> diff --git a/drivers/clk/meson/s4-pll.c b/drivers/clk/meson/s4-pll.c
>> new file mode 100644
>> index 000000000000..c70a33586bcd
>> --- /dev/null
>> +++ b/drivers/clk/meson/s4-pll.c
>> @@ -0,0 +1,907 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Amlogic Meson-S4 PLL Clock Controller Driver
>> + *
>> + * Copyright (c) 2021 Amlogic, inc.
>> + * Author: Yu Tu <yu.tu@amlogic.com>
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/of_device.h>
>> +#include <linux/platform_device.h>
>> +
>> +#include "clk-mpll.h"
>> +#include "clk-pll.h"
>> +#include "clk-regmap.h"
>> +#include "s4-pll.h"
>> +
>> +static DEFINE_SPINLOCK(meson_clk_lock);
>> +
>> +static struct clk_regmap s4_fixed_pll_dco = {
>> + .data = &(struct meson_clk_pll_data){
>> + .en = {
>> + .reg_off = ANACTRL_FIXPLL_CTRL0,
>> + .shift = 28,
>> + .width = 1,
>> + },
>> + .m = {
>> + .reg_off = ANACTRL_FIXPLL_CTRL0,
>> + .shift = 0,
>> + .width = 8,
>> + },
>> + .n = {
>> + .reg_off = ANACTRL_FIXPLL_CTRL0,
>> + .shift = 10,
>> + .width = 5,
>> + },
>> + .frac = {
>> + .reg_off = ANACTRL_FIXPLL_CTRL1,
>> + .shift = 0,
>> + .width = 17,
>> + },
>> + .l = {
>> + .reg_off = ANACTRL_FIXPLL_CTRL0,
>> + .shift = 31,
>> + .width = 1,
>> + },
>> + .rst = {
>> + .reg_off = ANACTRL_FIXPLL_CTRL0,
>> + .shift = 29,
>> + .width = 1,
>> + },
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fixed_pll_dco",
>> + /*
>> + * This clock is a fixed value (4GHz) that is initialized by ROMcode.
>> + * This clock won't ever change at runtime.
>> + * The chip design determines that this clock cannot be changed after
>> + * initialization. To prevent system crash caused by changing
>> + * fixed related register in kernel phase. This register is not
>> + * writable in the kernel phase.
>> + * So we use ro_ops.
>> + */
>> + .ops = &meson_clk_pll_ro_ops,
>> + .parent_data = (const struct clk_parent_data []) {
>> + { .fw_name = "xtal", }
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_fixed_pll = {
>> + .data = &(struct clk_regmap_div_data){
>> + .offset = ANACTRL_FIXPLL_CTRL0,
>> + .shift = 16,
>> + .width = 2,
>> + .flags = CLK_DIVIDER_POWER_OF_TWO,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fixed_pll",
>> + /*
>> + * This clock is a fixed value (2GHz) that is initialized by ROMcode.
>> + * For more information, please refer to s4_fixed_pll_dco.
>> + */
>> + .ops = &clk_regmap_divider_ro_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fixed_pll_dco.hw
>> + },
>> + .num_parents = 1,
>> + /*
>> + * This clock won't ever change at runtime so
>> + * CLK_SET_RATE_PARENT is not required
>> + */
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor s4_fclk_div2_div = {
>> + .mult = 1,
>> + .div = 2,
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div2_div",
>> + .ops = &clk_fixed_factor_ops,
>> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_fclk_div2 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_FIXPLL_CTRL1,
>> + .bit_idx = 24,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div2",
>> + /*
>> + * This clock is a fixed value (1GHz) that is initialized by ROMcode.
>> + * For more information, please refer to s4_fixed_pll_dco.
>> + */
>> + .ops = &clk_regmap_gate_ro_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fclk_div2_div.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor s4_fclk_div3_div = {
>> + .mult = 1,
>> + .div = 3,
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div3_div",
>> + .ops = &clk_fixed_factor_ops,
>> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_fclk_div3 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_FIXPLL_CTRL1,
>> + .bit_idx = 20,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div3",
>> + /*
>> + * For more information, please refer to s4_fixed_pll_dco.
>> + */
>> + .ops = &clk_regmap_gate_ro_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fclk_div3_div.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor s4_fclk_div4_div = {
>> + .mult = 1,
>> + .div = 4,
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div4_div",
>> + .ops = &clk_fixed_factor_ops,
>> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_fclk_div4 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_FIXPLL_CTRL1,
>> + .bit_idx = 21,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div4",
>> + /*
>> + * For more information, please refer to s4_fixed_pll_dco.
>> + */
>> + .ops = &clk_regmap_gate_ro_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fclk_div4_div.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor s4_fclk_div5_div = {
>> + .mult = 1,
>> + .div = 5,
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div5_div",
>> + .ops = &clk_fixed_factor_ops,
>> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_fclk_div5 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_FIXPLL_CTRL1,
>> + .bit_idx = 22,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div5",
>> + /*
>> + * For more information, please refer to s4_fixed_pll_dco.
>> + */
>> + .ops = &clk_regmap_gate_ro_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fclk_div5_div.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor s4_fclk_div7_div = {
>> + .mult = 1,
>> + .div = 7,
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div7_div",
>> + .ops = &clk_fixed_factor_ops,
>> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_fclk_div7 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_FIXPLL_CTRL1,
>> + .bit_idx = 23,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div7",
>> + /*
>> + * For more information, please refer to s4_fixed_pll_dco.
>> + */
>> + .ops = &clk_regmap_gate_ro_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fclk_div7_div.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor s4_fclk_div2p5_div = {
>> + .mult = 2,
>> + .div = 5,
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div2p5_div",
>> + .ops = &clk_fixed_factor_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fixed_pll.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_fclk_div2p5 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_FIXPLL_CTRL1,
>> + .bit_idx = 25,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div2p5",
>> + /*
>> + * For more information, please refer to s4_fixed_pll_dco.
>> + */
>> + .ops = &clk_regmap_gate_ro_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fclk_div2p5_div.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static const struct pll_mult_range s4_gp0_pll_mult_range = {
>> + .min = 125,
>> + .max = 250,
>> +};
>> +
>> +/*
>> + * Internal gp0 pll emulation configuration parameters
>> + */
>> +static const struct reg_sequence s4_gp0_init_regs[] = {
>> + { .reg = ANACTRL_GP0PLL_CTRL1, .def = 0x00000000 },
>> + { .reg = ANACTRL_GP0PLL_CTRL2, .def = 0x00000000 },
>> + { .reg = ANACTRL_GP0PLL_CTRL3, .def = 0x48681c00 },
>> + { .reg = ANACTRL_GP0PLL_CTRL4, .def = 0x88770290 },
>> + { .reg = ANACTRL_GP0PLL_CTRL5, .def = 0x39272000 },
>> + { .reg = ANACTRL_GP0PLL_CTRL6, .def = 0x56540000 }
>> +};
>> +
>> +static struct clk_regmap s4_gp0_pll_dco = {
>> + .data = &(struct meson_clk_pll_data){
>> + .en = {
>> + .reg_off = ANACTRL_GP0PLL_CTRL0,
>> + .shift = 28,
>> + .width = 1,
>> + },
>> + .m = {
>> + .reg_off = ANACTRL_GP0PLL_CTRL0,
>> + .shift = 0,
>> + .width = 8,
>> + },
>> + .n = {
>> + .reg_off = ANACTRL_GP0PLL_CTRL0,
>> + .shift = 10,
>> + .width = 5,
>> + },
>> + .frac = {
>> + .reg_off = ANACTRL_GP0PLL_CTRL1,
>> + .shift = 0,
>> + .width = 17,
>> + },
>> + .l = {
>> + .reg_off = ANACTRL_GP0PLL_CTRL0,
>> + .shift = 31,
>> + .width = 1,
>> + },
>> + .rst = {
>> + .reg_off = ANACTRL_GP0PLL_CTRL0,
>> + .shift = 29,
>> + .width = 1,
>> + },
>> + .range = &s4_gp0_pll_mult_range,
>> + .init_regs = s4_gp0_init_regs,
>> + .init_count = ARRAY_SIZE(s4_gp0_init_regs),
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gp0_pll_dco",
>> + .ops = &meson_clk_pll_ops,
>> + .parent_data = (const struct clk_parent_data []) {
>> + { .fw_name = "xtal", }
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_gp0_pll = {
>> + .data = &(struct clk_regmap_div_data){
>> + .offset = ANACTRL_GP0PLL_CTRL0,
>> + .shift = 16,
>> + .width = 3,
>> + .flags = (CLK_DIVIDER_POWER_OF_TWO |
>> + CLK_DIVIDER_ROUND_CLOSEST),
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gp0_pll",
>> + .ops = &clk_regmap_divider_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_gp0_pll_dco.hw
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +/*
>> + * Internal hifi pll emulation configuration parameters
>> + */
>> +static const struct reg_sequence s4_hifi_init_regs[] = {
>> + { .reg = ANACTRL_HIFIPLL_CTRL1, .def = 0x00010e56 },
>> + { .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00000000 },
>> + { .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x6a285c00 },
>> + { .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x65771290 },
>> + { .reg = ANACTRL_HIFIPLL_CTRL5, .def = 0x39272000 },
>> + { .reg = ANACTRL_HIFIPLL_CTRL6, .def = 0x56540000 }
>> +};
>> +
>> +static struct clk_regmap s4_hifi_pll_dco = {
>> + .data = &(struct meson_clk_pll_data){
>> + .en = {
>> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
>> + .shift = 28,
>> + .width = 1,
>> + },
>> + .m = {
>> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
>> + .shift = 0,
>> + .width = 8,
>> + },
>> + .n = {
>> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
>> + .shift = 10,
>> + .width = 5,
>> + },
>> + .frac = {
>> + .reg_off = ANACTRL_HIFIPLL_CTRL1,
>> + .shift = 0,
>> + .width = 17,
>> + },
>> + .l = {
>> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
>> + .shift = 31,
>> + .width = 1,
>> + },
>> + .rst = {
>> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
>> + .shift = 29,
>> + .width = 1,
>> + },
>> + .range = &s4_gp0_pll_mult_range,
>> + .init_regs = s4_hifi_init_regs,
>> + .init_count = ARRAY_SIZE(s4_hifi_init_regs),
>> + .flags = CLK_MESON_PLL_ROUND_CLOSEST,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "hifi_pll_dco",
>> + .ops = &meson_clk_pll_ops,
>> + .parent_data = (const struct clk_parent_data []) {
>> + { .fw_name = "xtal", }
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_hifi_pll = {
>> + .data = &(struct clk_regmap_div_data){
>> + .offset = ANACTRL_HIFIPLL_CTRL0,
>> + .shift = 16,
>> + .width = 2,
>> + .flags = (CLK_DIVIDER_POWER_OF_TWO |
>> + CLK_DIVIDER_ROUND_CLOSEST),
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "hifi_pll",
>> + .ops = &clk_regmap_divider_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_hifi_pll_dco.hw
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_hdmi_pll_dco = {
>> + .data = &(struct meson_clk_pll_data){
>> + .en = {
>> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
>> + .shift = 28,
>> + .width = 1,
>> + },
>> + .m = {
>> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
>> + .shift = 0,
>> + .width = 8,
>> + },
>> + .n = {
>> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
>> + .shift = 10,
>> + .width = 5,
>> + },
>> + .frac = {
>> + .reg_off = ANACTRL_HDMIPLL_CTRL1,
>> + .shift = 0,
>> + .width = 17,
>> + },
>> + .l = {
>> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
>> + .shift = 31,
>> + .width = 1,
>> + },
>> + .rst = {
>> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
>> + .shift = 29,
>> + .width = 1,
>> + },
>> + .range = &s4_gp0_pll_mult_range,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "hdmi_pll_dco",
>> + .ops = &meson_clk_pll_ops,
>> + .parent_data = (const struct clk_parent_data []) {
>> + { .fw_name = "xtal", }
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_hdmi_pll_od = {
>> + .data = &(struct clk_regmap_div_data){
>> + .offset = ANACTRL_HDMIPLL_CTRL0,
>> + .shift = 16,
>> + .width = 4,
>> + .flags = CLK_DIVIDER_POWER_OF_TWO,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "hdmi_pll_od",
>> + .ops = &clk_regmap_divider_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_hdmi_pll_dco.hw
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_hdmi_pll = {
>> + .data = &(struct clk_regmap_div_data){
>> + .offset = ANACTRL_HDMIPLL_CTRL0,
>> + .shift = 20,
>> + .width = 2,
>> + .flags = CLK_DIVIDER_POWER_OF_TWO,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "hdmi_pll",
>> + .ops = &clk_regmap_divider_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_hdmi_pll_od.hw
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor s4_mpll_50m_div = {
>> + .mult = 1,
>> + .div = 80,
>> + .hw.init = &(struct clk_init_data){
>> + .name = "mpll_50m_div",
>> + .ops = &clk_fixed_factor_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fixed_pll_dco.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_mpll_50m = {
>> + .data = &(struct clk_regmap_mux_data){
>> + .offset = ANACTRL_FIXPLL_CTRL3,
>> + .mask = 0x1,
>> + .shift = 5,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "mpll_50m",
>> + .ops = &clk_regmap_mux_ro_ops,
>> + .parent_data = (const struct clk_parent_data []) {
>> + { .fw_name = "xtal", },
>> + { .hw = &s4_mpll_50m_div.hw },
>> + },
>> + .num_parents = 2,
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor s4_mpll_prediv = {
>> + .mult = 1,
>> + .div = 2,
>> + .hw.init = &(struct clk_init_data){
>> + .name = "mpll_prediv",
>> + .ops = &clk_fixed_factor_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fixed_pll_dco.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static const struct reg_sequence s4_mpll0_init_regs[] = {
>> + { .reg = ANACTRL_MPLL_CTRL2, .def = 0x40000033 }
>> +};
>> +
>> +static struct clk_regmap s4_mpll0_div = {
>> + .data = &(struct meson_clk_mpll_data){
>> + .sdm = {
>> + .reg_off = ANACTRL_MPLL_CTRL1,
>> + .shift = 0,
>> + .width = 14,
>> + },
>> + .sdm_en = {
>> + .reg_off = ANACTRL_MPLL_CTRL1,
>> + .shift = 30,
>> + .width = 1,
>> + },
>> + .n2 = {
>> + .reg_off = ANACTRL_MPLL_CTRL1,
>> + .shift = 20,
>> + .width = 9,
>> + },
>> + .ssen = {
>> + .reg_off = ANACTRL_MPLL_CTRL1,
>> + .shift = 29,
>> + .width = 1,
>> + },
>> + .lock = &meson_clk_lock,
>> + .init_regs = s4_mpll0_init_regs,
>> + .init_count = ARRAY_SIZE(s4_mpll0_init_regs),
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "mpll0_div",
>> + .ops = &meson_clk_mpll_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_mpll_prediv.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_mpll0 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_MPLL_CTRL1,
>> + .bit_idx = 31,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "mpll0",
>> + .ops = &clk_regmap_gate_ops,
>> + .parent_hws = (const struct clk_hw *[]) { &s4_mpll0_div.hw },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static const struct reg_sequence s4_mpll1_init_regs[] = {
>> + { .reg = ANACTRL_MPLL_CTRL4, .def = 0x40000033 }
>> +};
>> +
>> +static struct clk_regmap s4_mpll1_div = {
>> + .data = &(struct meson_clk_mpll_data){
>> + .sdm = {
>> + .reg_off = ANACTRL_MPLL_CTRL3,
>> + .shift = 0,
>> + .width = 14,
>> + },
>> + .sdm_en = {
>> + .reg_off = ANACTRL_MPLL_CTRL3,
>> + .shift = 30,
>> + .width = 1,
>> + },
>> + .n2 = {
>> + .reg_off = ANACTRL_MPLL_CTRL3,
>> + .shift = 20,
>> + .width = 9,
>> + },
>> + .ssen = {
>> + .reg_off = ANACTRL_MPLL_CTRL3,
>> + .shift = 29,
>> + .width = 1,
>> + },
>> + .lock = &meson_clk_lock,
>> + .init_regs = s4_mpll1_init_regs,
>> + .init_count = ARRAY_SIZE(s4_mpll1_init_regs),
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "mpll1_div",
>> + .ops = &meson_clk_mpll_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_mpll_prediv.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_mpll1 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_MPLL_CTRL3,
>> + .bit_idx = 31,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "mpll1",
>> + .ops = &clk_regmap_gate_ops,
>> + .parent_hws = (const struct clk_hw *[]) { &s4_mpll1_div.hw },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static const struct reg_sequence s4_mpll2_init_regs[] = {
>> + { .reg = ANACTRL_MPLL_CTRL6, .def = 0x40000033 }
>> +};
>> +
>> +static struct clk_regmap s4_mpll2_div = {
>> + .data = &(struct meson_clk_mpll_data){
>> + .sdm = {
>> + .reg_off = ANACTRL_MPLL_CTRL5,
>> + .shift = 0,
>> + .width = 14,
>> + },
>> + .sdm_en = {
>> + .reg_off = ANACTRL_MPLL_CTRL5,
>> + .shift = 30,
>> + .width = 1,
>> + },
>> + .n2 = {
>> + .reg_off = ANACTRL_MPLL_CTRL5,
>> + .shift = 20,
>> + .width = 9,
>> + },
>> + .ssen = {
>> + .reg_off = ANACTRL_MPLL_CTRL5,
>> + .shift = 29,
>> + .width = 1,
>> + },
>> + .lock = &meson_clk_lock,
>> + .init_regs = s4_mpll2_init_regs,
>> + .init_count = ARRAY_SIZE(s4_mpll2_init_regs),
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "mpll2_div",
>> + .ops = &meson_clk_mpll_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_mpll_prediv.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_mpll2 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_MPLL_CTRL5,
>> + .bit_idx = 31,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "mpll2",
>> + .ops = &clk_regmap_gate_ops,
>> + .parent_hws = (const struct clk_hw *[]) { &s4_mpll2_div.hw },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static const struct reg_sequence s4_mpll3_init_regs[] = {
>> + { .reg = ANACTRL_MPLL_CTRL8, .def = 0x40000033 }
>> +};
>> +
>> +static struct clk_regmap s4_mpll3_div = {
>> + .data = &(struct meson_clk_mpll_data){
>> + .sdm = {
>> + .reg_off = ANACTRL_MPLL_CTRL7,
>> + .shift = 0,
>> + .width = 14,
>> + },
>> + .sdm_en = {
>> + .reg_off = ANACTRL_MPLL_CTRL7,
>> + .shift = 30,
>> + .width = 1,
>> + },
>> + .n2 = {
>> + .reg_off = ANACTRL_MPLL_CTRL7,
>> + .shift = 20,
>> + .width = 9,
>> + },
>> + .ssen = {
>> + .reg_off = ANACTRL_MPLL_CTRL7,
>> + .shift = 29,
>> + .width = 1,
>> + },
>> + .lock = &meson_clk_lock,
>> + .init_regs = s4_mpll3_init_regs,
>> + .init_count = ARRAY_SIZE(s4_mpll3_init_regs),
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "mpll3_div",
>> + .ops = &meson_clk_mpll_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_mpll_prediv.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_mpll3 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_MPLL_CTRL7,
>> + .bit_idx = 31,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "mpll3",
>> + .ops = &clk_regmap_gate_ops,
>> + .parent_hws = (const struct clk_hw *[]) { &s4_mpll3_div.hw },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +/* Array of all clocks provided by this provider */
>> +static struct clk_hw_onecell_data s4_pll_hw_onecell_data = {
>> + .hws = {
>> + [CLKID_FIXED_PLL_DCO] = &s4_fixed_pll_dco.hw,
>> + [CLKID_FIXED_PLL] = &s4_fixed_pll.hw,
>> + [CLKID_FCLK_DIV2_DIV] = &s4_fclk_div2_div.hw,
>> + [CLKID_FCLK_DIV2] = &s4_fclk_div2.hw,
>> + [CLKID_FCLK_DIV3_DIV] = &s4_fclk_div3_div.hw,
>> + [CLKID_FCLK_DIV3] = &s4_fclk_div3.hw,
>> + [CLKID_FCLK_DIV4_DIV] = &s4_fclk_div4_div.hw,
>> + [CLKID_FCLK_DIV4] = &s4_fclk_div4.hw,
>> + [CLKID_FCLK_DIV5_DIV] = &s4_fclk_div5_div.hw,
>> + [CLKID_FCLK_DIV5] = &s4_fclk_div5.hw,
>> + [CLKID_FCLK_DIV7_DIV] = &s4_fclk_div7_div.hw,
>> + [CLKID_FCLK_DIV7] = &s4_fclk_div7.hw,
>> + [CLKID_FCLK_DIV2P5_DIV] = &s4_fclk_div2p5_div.hw,
>> + [CLKID_FCLK_DIV2P5] = &s4_fclk_div2p5.hw,
>> + [CLKID_GP0_PLL_DCO] = &s4_gp0_pll_dco.hw,
>> + [CLKID_GP0_PLL] = &s4_gp0_pll.hw,
>> + [CLKID_HIFI_PLL_DCO] = &s4_hifi_pll_dco.hw,
>> + [CLKID_HIFI_PLL] = &s4_hifi_pll.hw,
>> + [CLKID_HDMI_PLL_DCO] = &s4_hdmi_pll_dco.hw,
>> + [CLKID_HDMI_PLL_OD] = &s4_hdmi_pll_od.hw,
>> + [CLKID_HDMI_PLL] = &s4_hdmi_pll.hw,
>> + [CLKID_MPLL_50M_DIV] = &s4_mpll_50m_div.hw,
>> + [CLKID_MPLL_50M] = &s4_mpll_50m.hw,
>> + [CLKID_MPLL_PREDIV] = &s4_mpll_prediv.hw,
>> + [CLKID_MPLL0_DIV] = &s4_mpll0_div.hw,
>> + [CLKID_MPLL0] = &s4_mpll0.hw,
>> + [CLKID_MPLL1_DIV] = &s4_mpll1_div.hw,
>> + [CLKID_MPLL1] = &s4_mpll1.hw,
>> + [CLKID_MPLL2_DIV] = &s4_mpll2_div.hw,
>> + [CLKID_MPLL2] = &s4_mpll2.hw,
>> + [CLKID_MPLL3_DIV] = &s4_mpll3_div.hw,
>> + [CLKID_MPLL3] = &s4_mpll3.hw,
>> + [NR_PLL_CLKS] = NULL
>> + },
>> + .num = NR_PLL_CLKS,
>> +};
>> +
>> +static struct clk_regmap *const s4_pll_clk_regmaps[] = {
>> + &s4_fixed_pll_dco,
>> + &s4_fixed_pll,
>> + &s4_fclk_div2,
>> + &s4_fclk_div3,
>> + &s4_fclk_div4,
>> + &s4_fclk_div5,
>> + &s4_fclk_div7,
>> + &s4_fclk_div2p5,
>> + &s4_gp0_pll_dco,
>> + &s4_gp0_pll,
>> + &s4_hifi_pll_dco,
>> + &s4_hifi_pll,
>> + &s4_hdmi_pll_dco,
>> + &s4_hdmi_pll_od,
>> + &s4_hdmi_pll,
>> + &s4_mpll_50m,
>> + &s4_mpll0_div,
>> + &s4_mpll0,
>> + &s4_mpll1_div,
>> + &s4_mpll1,
>> + &s4_mpll2_div,
>> + &s4_mpll2,
>> + &s4_mpll3_div,
>> + &s4_mpll3,
>> +};
>> +
>> +static const struct reg_sequence s4_init_regs[] = {
>> + { .reg = ANACTRL_MPLL_CTRL0, .def = 0x00000543 },
>> +};
>> +
>> +static struct regmap_config clkc_regmap_config = {
>> + .reg_bits = 32,
>> + .val_bits = 32,
>> + .reg_stride = 4,
>> +};
>> +
>> +static int meson_s4_pll_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct regmap *regmap;
>> + void __iomem *base;
>> + int ret, i;
>> +
>> + base = devm_platform_ioremap_resource(pdev, 0);
>> + if (IS_ERR(base))
>> + return PTR_ERR(base);
>> +
>> + regmap = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
>> + if (IS_ERR(regmap))
>> + return PTR_ERR(regmap);
>> +
>> + ret = regmap_multi_reg_write(regmap, s4_init_regs, ARRAY_SIZE(s4_init_regs));
>> + if (ret) {
>> + dev_err(dev, "Failed to init registers\n");
>> + return ret;
>> + }
>> +
>> + /* Populate regmap for the regmap backed clocks */
>> + for (i = 0; i < ARRAY_SIZE(s4_pll_clk_regmaps); i++)
>> + s4_pll_clk_regmaps[i]->map = regmap;
>> +
>> + for (i = 0; i < s4_pll_hw_onecell_data.num; i++) {
>> + /* array might be sparse */
>> + if (!s4_pll_hw_onecell_data.hws[i])
>> + continue;
>> +
>> + ret = devm_clk_hw_register(dev, s4_pll_hw_onecell_data.hws[i]);
>> + if (ret) {
>> + dev_err(dev, "Clock registration failed\n");
>> + return ret;
>> + }
>> + }
>> +
>> + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
>> + &s4_pll_hw_onecell_data);
>> +}
>> +
>> +static const struct of_device_id clkc_match_table[] = {
>> + {
>> + .compatible = "amlogic,s4-pll-clkc",
>> + },
>> + {}
>> +};
>> +
>> +static struct platform_driver s4_driver = {
>> + .probe = meson_s4_pll_probe,
>> + .driver = {
>> + .name = "s4-pll-clkc",
>> + .of_match_table = clkc_match_table,
>> + },
>> +};
>> +
>> +module_platform_driver(s4_driver);
>> +MODULE_LICENSE("GPL");
>> diff --git a/drivers/clk/meson/s4-pll.h b/drivers/clk/meson/s4-pll.h
>> new file mode 100644
>> index 000000000000..021d9f8b2b30
>> --- /dev/null
>> +++ b/drivers/clk/meson/s4-pll.h
>> @@ -0,0 +1,87 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>> +/*
>> + * Copyright (c) 2021 Amlogic, inc.
>> + * Author: Yu Tu <yu.tu@amlogic.com>
>> + */
>> +
>> +#ifndef __MESON_S4_PLL_H__
>> +#define __MESON_S4_PLL_H__
>> +
>> +/* ANA_CTRL - Registers */
>> +
>> +#define ANACTRL_FIXPLL_CTRL0 0x040
>> +#define ANACTRL_FIXPLL_CTRL1 0x044
>> +#define ANACTRL_FIXPLL_CTRL2 0x048
>> +#define ANACTRL_FIXPLL_CTRL3 0x04c
>> +#define ANACTRL_FIXPLL_CTRL4 0x050
>> +#define ANACTRL_FIXPLL_CTRL5 0x054
>> +#define ANACTRL_FIXPLL_CTRL6 0x058
>> +#define ANACTRL_FIXPLL_STS 0x05c
>> +#define ANACTRL_GP0PLL_CTRL0 0x080
>> +#define ANACTRL_GP0PLL_CTRL1 0x084
>> +#define ANACTRL_GP0PLL_CTRL2 0x088
>> +#define ANACTRL_GP0PLL_CTRL3 0x08c
>> +#define ANACTRL_GP0PLL_CTRL4 0x090
>> +#define ANACTRL_GP0PLL_CTRL5 0x094
>> +#define ANACTRL_GP0PLL_CTRL6 0x098
>> +#define ANACTRL_GP0PLL_STS 0x09c
>> +#define ANACTRL_HIFIPLL_CTRL0 0x100
>> +#define ANACTRL_HIFIPLL_CTRL1 0x104
>> +#define ANACTRL_HIFIPLL_CTRL2 0x108
>> +#define ANACTRL_HIFIPLL_CTRL3 0x10c
>> +#define ANACTRL_HIFIPLL_CTRL4 0x110
>> +#define ANACTRL_HIFIPLL_CTRL5 0x114
>> +#define ANACTRL_HIFIPLL_CTRL6 0x118
>> +#define ANACTRL_HIFIPLL_STS 0x11c
>> +#define ANACTRL_MPLL_CTRL0 0x180
>> +#define ANACTRL_MPLL_CTRL1 0x184
>> +#define ANACTRL_MPLL_CTRL2 0x188
>> +#define ANACTRL_MPLL_CTRL3 0x18c
>> +#define ANACTRL_MPLL_CTRL4 0x190
>> +#define ANACTRL_MPLL_CTRL5 0x194
>> +#define ANACTRL_MPLL_CTRL6 0x198
>> +#define ANACTRL_MPLL_CTRL7 0x19c
>> +#define ANACTRL_MPLL_CTRL8 0x1a0
>> +#define ANACTRL_MPLL_STS 0x1a4
>> +#define ANACTRL_HDMIPLL_CTRL0 0x1c0
>> +#define ANACTRL_HDMIPLL_CTRL1 0x1c4
>> +#define ANACTRL_HDMIPLL_CTRL2 0x1c8
>> +#define ANACTRL_HDMIPLL_CTRL3 0x1cc
>> +#define ANACTRL_HDMIPLL_CTRL4 0x1d0
>> +#define ANACTRL_HDMIPLL_CTRL5 0x1d4
>> +#define ANACTRL_HDMIPLL_CTRL6 0x1d8
>> +#define ANACTRL_HDMIPLL_STS 0x1dc
>> +#define ANACTRL_HDMIPLL_VLOCK 0x1e4
>> +
>> +/*
>> + * CLKID index values
>> + *
>> + * These indices are entirely contrived and do not map onto the hardware.
>> + * It has now been decided to expose everything by default in the DT header:
>> + * include/dt-bindings/clock/amlogic,s4-pll-clkc.h. Only the clocks ids we don't
>> + * want to expose, such as the internal muxes and dividers of composite clocks,
>> + * will remain defined here.
>> + */
>> +#define CLKID_FIXED_PLL_DCO 0
>> +#define CLKID_FCLK_DIV2_DIV 2
>> +#define CLKID_FCLK_DIV3_DIV 4
>> +#define CLKID_FCLK_DIV4_DIV 6
>> +#define CLKID_FCLK_DIV5_DIV 8
>> +#define CLKID_FCLK_DIV7_DIV 10
>> +#define CLKID_FCLK_DIV2P5_DIV 12
>> +#define CLKID_GP0_PLL_DCO 14
>> +#define CLKID_HIFI_PLL_DCO 16
>> +#define CLKID_HDMI_PLL_DCO 18
>> +#define CLKID_HDMI_PLL_OD 19
>> +#define CLKID_MPLL_50M_DIV 21
>> +#define CLKID_MPLL_PREDIV 23
>> +#define CLKID_MPLL0_DIV 24
>> +#define CLKID_MPLL1_DIV 26
>> +#define CLKID_MPLL2_DIV 28
>> +#define CLKID_MPLL3_DIV 30
>> +
>> +#define NR_PLL_CLKS 32
>> +/* include the CLKIDs that have been made part of the DT binding */
>> +#include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
>> +
>> +#endif /* __MESON_S4_PLL_H__ */
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH V9 3/4] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver
2023-06-06 14:02 ` Jerome Brunet
@ 2023-06-08 2:54 ` Yu Tu
2023-06-08 8:53 ` Jerome Brunet
0 siblings, 1 reply; 15+ messages in thread
From: Yu Tu @ 2023-06-08 2:54 UTC (permalink / raw)
To: Jerome Brunet, linux-clk, linux-arm-kernel, linux-amlogic,
linux-kernel, devicetree, Rob Herring, Neil Armstrong,
Kevin Hilman, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Conor Dooley, Martin Blumenstingl
Cc: kelvin.zhang, qi.duan
On 2023/6/6 22:02, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On Wed 17 May 2023 at 15:02, Yu Tu <yu.tu@amlogic.com> wrote:
>
>> Add the S4 PLL clock controller driver in the s4 SoC family.
>>
>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>> ---
>> drivers/clk/meson/Kconfig | 13 +
>> drivers/clk/meson/Makefile | 1 +
>> drivers/clk/meson/s4-pll.c | 907 +++++++++++++++++++++++++++++++++++++
>> drivers/clk/meson/s4-pll.h | 87 ++++
>> 4 files changed, 1008 insertions(+)
>> create mode 100644 drivers/clk/meson/s4-pll.c
>> create mode 100644 drivers/clk/meson/s4-pll.h
>>
>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>> index fc002c155bc3..a663c90a3f3b 100644
>> --- a/drivers/clk/meson/Kconfig
>> +++ b/drivers/clk/meson/Kconfig
>> @@ -115,4 +115,17 @@ config COMMON_CLK_G12A
>> help
>> Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
>> devices, aka g12a. Say Y if you want peripherals to work.
>> +
>> +config COMMON_CLK_S4_PLL
>> + tristate "S4 SoC PLL clock controllers support"
>> + depends on ARM64
>> + default y
>> + select COMMON_CLK_MESON_MPLL
>> + select COMMON_CLK_MESON_PLL
>> + select COMMON_CLK_MESON_REGMAP
>> + help
>> + Support for the pll clock controller on Amlogic S805X2 and S905Y4 devices,
>> + aka s4. Amlogic S805X2 and S905Y4 devices include AQ222 and AQ229.
>> + Say Y if you want the board to work, because plls are the parent of most
>> + peripherals.
>> endmenu
>> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
>> index 6eca2a406ee3..376f49cc13f1 100644
>> --- a/drivers/clk/meson/Makefile
>> +++ b/drivers/clk/meson/Makefile
>> @@ -19,3 +19,4 @@ obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
>> obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
>> obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
>> obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
>> +obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o
>> diff --git a/drivers/clk/meson/s4-pll.c b/drivers/clk/meson/s4-pll.c
>> new file mode 100644
>> index 000000000000..c70a33586bcd
>> --- /dev/null
>> +++ b/drivers/clk/meson/s4-pll.c
>> @@ -0,0 +1,907 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Amlogic Meson-S4 PLL Clock Controller Driver
>> + *
>> + * Copyright (c) 2021 Amlogic, inc.
>> + * Author: Yu Tu <yu.tu@amlogic.com>
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/of_device.h>
>> +#include <linux/platform_device.h>
>> +
>> +#include "clk-mpll.h"
>> +#include "clk-pll.h"
>> +#include "clk-regmap.h"
>> +#include "s4-pll.h"
>> +
>> +static DEFINE_SPINLOCK(meson_clk_lock);
>> +
>> +static struct clk_regmap s4_fixed_pll_dco = {
>> + .data = &(struct meson_clk_pll_data){
>> + .en = {
>> + .reg_off = ANACTRL_FIXPLL_CTRL0,
>> + .shift = 28,
>> + .width = 1,
>> + },
>> + .m = {
>> + .reg_off = ANACTRL_FIXPLL_CTRL0,
>> + .shift = 0,
>> + .width = 8,
>> + },
>> + .n = {
>> + .reg_off = ANACTRL_FIXPLL_CTRL0,
>> + .shift = 10,
>> + .width = 5,
>> + },
>> + .frac = {
>> + .reg_off = ANACTRL_FIXPLL_CTRL1,
>> + .shift = 0,
>> + .width = 17,
>> + },
>> + .l = {
>> + .reg_off = ANACTRL_FIXPLL_CTRL0,
>> + .shift = 31,
>> + .width = 1,
>> + },
>> + .rst = {
>> + .reg_off = ANACTRL_FIXPLL_CTRL0,
>> + .shift = 29,
>> + .width = 1,
>> + },
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fixed_pll_dco",
>> + /*
>> + * This clock is a fixed value (4GHz) that is initialized by ROMcode.
>
> Really, isn't it the bl2 doing that ?
Yes. The first step is ROMcode initialization. bl2 can also be
initialized if any parameters need to be adjusted.
>
>> + * This clock won't ever change at runtime.
>> + * The chip design determines that this clock cannot be changed after
>> + * initialization. To prevent system crash caused by changing
>> + * fixed related register in kernel phase. This register is not
>> + * writable in the kernel phase.
>> + * So we use ro_ops.
>> + */
>
> This explanation is good but we don't need mutliple copy/paste or
> "please refer" for the same thing. That is very verbose (I think I
> already commented on this previously)
>
> Just make one comment block, that clearly explain your intent and that
> it applies to the fixed_pll group
Okay.
>
>> + .ops = &meson_clk_pll_ro_ops,
>> + .parent_data = (const struct clk_parent_data []) {
>> + { .fw_name = "xtal", }
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_fixed_pll = {
>> + .data = &(struct clk_regmap_div_data){
>> + .offset = ANACTRL_FIXPLL_CTRL0,
>> + .shift = 16,
>> + .width = 2,
>> + .flags = CLK_DIVIDER_POWER_OF_TWO,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fixed_pll",
>> + /*
>> + * This clock is a fixed value (2GHz) that is initialized by ROMcode.
>> + * For more information, please refer to s4_fixed_pll_dco.
>> + */
>> + .ops = &clk_regmap_divider_ro_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fixed_pll_dco.hw
>> + },
>> + .num_parents = 1,
>> + /*
>> + * This clock won't ever change at runtime so
>> + * CLK_SET_RATE_PARENT is not required
>> + */
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor s4_fclk_div2_div = {
>> + .mult = 1,
>> + .div = 2,
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div2_div",
>> + .ops = &clk_fixed_factor_ops,
>> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_fclk_div2 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_FIXPLL_CTRL1,
>> + .bit_idx = 24,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div2",
>> + /*
>> + * This clock is a fixed value (1GHz) that is initialized by ROMcode.
>> + * For more information, please refer to s4_fixed_pll_dco.
>> + */
>> + .ops = &clk_regmap_gate_ro_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fclk_div2_div.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor s4_fclk_div3_div = {
>> + .mult = 1,
>> + .div = 3,
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div3_div",
>> + .ops = &clk_fixed_factor_ops,
>> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_fclk_div3 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_FIXPLL_CTRL1,
>> + .bit_idx = 20,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div3",
>> + /*
>> + * For more information, please refer to s4_fixed_pll_dco.
>> + */
>> + .ops = &clk_regmap_gate_ro_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fclk_div3_div.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor s4_fclk_div4_div = {
>> + .mult = 1,
>> + .div = 4,
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div4_div",
>> + .ops = &clk_fixed_factor_ops,
>> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_fclk_div4 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_FIXPLL_CTRL1,
>> + .bit_idx = 21,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div4",
>> + /*
>> + * For more information, please refer to s4_fixed_pll_dco.
>> + */
>
> While div2 and div3 got an explanation from previous SoCs, they others -
> like div4/div7/etc ... - have been able to cope with rw ops so far.
>
> Why is the S4 different for all these clocks ?
The chip was changed fixed pll for security reasons.
Fixed PLL registers are not writable in the kernel phase. Write of fixed
PLL-related register will cause the system to crash.
>
> Requiring RO ops (or fishy clock flags) is usually a sign that a clock
> is used without an appropriate driver.
>
>> + .ops = &clk_regmap_gate_ro_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fclk_div4_div.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor s4_fclk_div5_div = {
>> + .mult = 1,
>> + .div = 5,
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div5_div",
>> + .ops = &clk_fixed_factor_ops,
>> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_fclk_div5 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_FIXPLL_CTRL1,
>> + .bit_idx = 22,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div5",
>> + /*
>> + * For more information, please refer to s4_fixed_pll_dco.
>> + */
>> + .ops = &clk_regmap_gate_ro_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fclk_div5_div.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor s4_fclk_div7_div = {
>> + .mult = 1,
>> + .div = 7,
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div7_div",
>> + .ops = &clk_fixed_factor_ops,
>> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_fclk_div7 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_FIXPLL_CTRL1,
>> + .bit_idx = 23,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div7",
>> + /*
>> + * For more information, please refer to s4_fixed_pll_dco.
>> + */
>> + .ops = &clk_regmap_gate_ro_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fclk_div7_div.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor s4_fclk_div2p5_div = {
>> + .mult = 2,
>> + .div = 5,
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div2p5_div",
>> + .ops = &clk_fixed_factor_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fixed_pll.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_fclk_div2p5 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_FIXPLL_CTRL1,
>> + .bit_idx = 25,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div2p5",
>> + /*
>> + * For more information, please refer to s4_fixed_pll_dco.
>> + */
>> + .ops = &clk_regmap_gate_ro_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fclk_div2p5_div.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static const struct pll_mult_range s4_gp0_pll_mult_range = {
>> + .min = 125,
>> + .max = 250,
>> +};
>> +
>> +/*
>> + * Internal gp0 pll emulation configuration parameters
>> + */
>> +static const struct reg_sequence s4_gp0_init_regs[] = {
>> + { .reg = ANACTRL_GP0PLL_CTRL1, .def = 0x00000000 },
>> + { .reg = ANACTRL_GP0PLL_CTRL2, .def = 0x00000000 },
>> + { .reg = ANACTRL_GP0PLL_CTRL3, .def = 0x48681c00 },
>> + { .reg = ANACTRL_GP0PLL_CTRL4, .def = 0x88770290 },
>> + { .reg = ANACTRL_GP0PLL_CTRL5, .def = 0x39272000 },
>> + { .reg = ANACTRL_GP0PLL_CTRL6, .def = 0x56540000 }
>> +};
>> +
>> +static struct clk_regmap s4_gp0_pll_dco = {
>> + .data = &(struct meson_clk_pll_data){
>> + .en = {
>> + .reg_off = ANACTRL_GP0PLL_CTRL0,
>> + .shift = 28,
>> + .width = 1,
>> + },
>> + .m = {
>> + .reg_off = ANACTRL_GP0PLL_CTRL0,
>> + .shift = 0,
>> + .width = 8,
>> + },
>> + .n = {
>> + .reg_off = ANACTRL_GP0PLL_CTRL0,
>> + .shift = 10,
>> + .width = 5,
>> + },
>> + .frac = {
>> + .reg_off = ANACTRL_GP0PLL_CTRL1,
>> + .shift = 0,
>> + .width = 17,
>> + },
>> + .l = {
>> + .reg_off = ANACTRL_GP0PLL_CTRL0,
>> + .shift = 31,
>> + .width = 1,
>> + },
>> + .rst = {
>> + .reg_off = ANACTRL_GP0PLL_CTRL0,
>> + .shift = 29,
>> + .width = 1,
>> + },
>> + .range = &s4_gp0_pll_mult_range,
>> + .init_regs = s4_gp0_init_regs,
>> + .init_count = ARRAY_SIZE(s4_gp0_init_regs),
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gp0_pll_dco",
>> + .ops = &meson_clk_pll_ops,
>> + .parent_data = (const struct clk_parent_data []) {
>> + { .fw_name = "xtal", }
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_gp0_pll = {
>> + .data = &(struct clk_regmap_div_data){
>> + .offset = ANACTRL_GP0PLL_CTRL0,
>> + .shift = 16,
>> + .width = 3,
>> + .flags = (CLK_DIVIDER_POWER_OF_TWO |
>> + CLK_DIVIDER_ROUND_CLOSEST),
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "gp0_pll",
>> + .ops = &clk_regmap_divider_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_gp0_pll_dco.hw
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +/*
>> + * Internal hifi pll emulation configuration parameters
>> + */
>> +static const struct reg_sequence s4_hifi_init_regs[] = {
>> + { .reg = ANACTRL_HIFIPLL_CTRL1, .def = 0x00010e56 },
>> + { .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00000000 },
>> + { .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x6a285c00 },
>> + { .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x65771290 },
>> + { .reg = ANACTRL_HIFIPLL_CTRL5, .def = 0x39272000 },
>> + { .reg = ANACTRL_HIFIPLL_CTRL6, .def = 0x56540000 }
>> +};
>> +
>> +static struct clk_regmap s4_hifi_pll_dco = {
>> + .data = &(struct meson_clk_pll_data){
>> + .en = {
>> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
>> + .shift = 28,
>> + .width = 1,
>> + },
>> + .m = {
>> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
>> + .shift = 0,
>> + .width = 8,
>> + },
>> + .n = {
>> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
>> + .shift = 10,
>> + .width = 5,
>> + },
>> + .frac = {
>> + .reg_off = ANACTRL_HIFIPLL_CTRL1,
>> + .shift = 0,
>> + .width = 17,
>> + },
>> + .l = {
>> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
>> + .shift = 31,
>> + .width = 1,
>> + },
>> + .rst = {
>> + .reg_off = ANACTRL_HIFIPLL_CTRL0,
>> + .shift = 29,
>> + .width = 1,
>> + },
>> + .range = &s4_gp0_pll_mult_range,
>> + .init_regs = s4_hifi_init_regs,
>> + .init_count = ARRAY_SIZE(s4_hifi_init_regs),
>> + .flags = CLK_MESON_PLL_ROUND_CLOSEST,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "hifi_pll_dco",
>> + .ops = &meson_clk_pll_ops,
>> + .parent_data = (const struct clk_parent_data []) {
>> + { .fw_name = "xtal", }
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_hifi_pll = {
>> + .data = &(struct clk_regmap_div_data){
>> + .offset = ANACTRL_HIFIPLL_CTRL0,
>> + .shift = 16,
>> + .width = 2,
>> + .flags = (CLK_DIVIDER_POWER_OF_TWO |
>> + CLK_DIVIDER_ROUND_CLOSEST),
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "hifi_pll",
>> + .ops = &clk_regmap_divider_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_hifi_pll_dco.hw
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_hdmi_pll_dco = {
>> + .data = &(struct meson_clk_pll_data){
>> + .en = {
>> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
>> + .shift = 28,
>> + .width = 1,
>> + },
>> + .m = {
>> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
>> + .shift = 0,
>> + .width = 8,
>> + },
>> + .n = {
>> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
>> + .shift = 10,
>> + .width = 5,
>> + },
>> + .frac = {
>> + .reg_off = ANACTRL_HDMIPLL_CTRL1,
>> + .shift = 0,
>> + .width = 17,
>> + },
>> + .l = {
>> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
>> + .shift = 31,
>> + .width = 1,
>> + },
>> + .rst = {
>> + .reg_off = ANACTRL_HDMIPLL_CTRL0,
>> + .shift = 29,
>> + .width = 1,
>> + },
>> + .range = &s4_gp0_pll_mult_range,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "hdmi_pll_dco",
>> + .ops = &meson_clk_pll_ops,
>> + .parent_data = (const struct clk_parent_data []) {
>> + { .fw_name = "xtal", }
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_hdmi_pll_od = {
>> + .data = &(struct clk_regmap_div_data){
>> + .offset = ANACTRL_HDMIPLL_CTRL0,
>> + .shift = 16,
>> + .width = 4,
>> + .flags = CLK_DIVIDER_POWER_OF_TWO,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "hdmi_pll_od",
>> + .ops = &clk_regmap_divider_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_hdmi_pll_dco.hw
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_hdmi_pll = {
>> + .data = &(struct clk_regmap_div_data){
>> + .offset = ANACTRL_HDMIPLL_CTRL0,
>> + .shift = 20,
>> + .width = 2,
>> + .flags = CLK_DIVIDER_POWER_OF_TWO,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "hdmi_pll",
>> + .ops = &clk_regmap_divider_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_hdmi_pll_od.hw
>> + },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor s4_mpll_50m_div = {
>> + .mult = 1,
>> + .div = 80,
>> + .hw.init = &(struct clk_init_data){
>> + .name = "mpll_50m_div",
>> + .ops = &clk_fixed_factor_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fixed_pll_dco.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_mpll_50m = {
>> + .data = &(struct clk_regmap_mux_data){
>> + .offset = ANACTRL_FIXPLL_CTRL3,
>> + .mask = 0x1,
>> + .shift = 5,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "mpll_50m",
>> + .ops = &clk_regmap_mux_ro_ops,
>> + .parent_data = (const struct clk_parent_data []) {
>> + { .fw_name = "xtal", },
>> + { .hw = &s4_mpll_50m_div.hw },
>> + },
>> + .num_parents = 2,
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor s4_mpll_prediv = {
>> + .mult = 1,
>> + .div = 2,
>> + .hw.init = &(struct clk_init_data){
>> + .name = "mpll_prediv",
>> + .ops = &clk_fixed_factor_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fixed_pll_dco.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static const struct reg_sequence s4_mpll0_init_regs[] = {
>> + { .reg = ANACTRL_MPLL_CTRL2, .def = 0x40000033 }
>> +};
>> +
>> +static struct clk_regmap s4_mpll0_div = {
>> + .data = &(struct meson_clk_mpll_data){
>> + .sdm = {
>> + .reg_off = ANACTRL_MPLL_CTRL1,
>> + .shift = 0,
>> + .width = 14,
>> + },
>> + .sdm_en = {
>> + .reg_off = ANACTRL_MPLL_CTRL1,
>> + .shift = 30,
>> + .width = 1,
>> + },
>> + .n2 = {
>> + .reg_off = ANACTRL_MPLL_CTRL1,
>> + .shift = 20,
>> + .width = 9,
>> + },
>> + .ssen = {
>> + .reg_off = ANACTRL_MPLL_CTRL1,
>> + .shift = 29,
>> + .width = 1,
>> + },
>> + .lock = &meson_clk_lock,
>> + .init_regs = s4_mpll0_init_regs,
>> + .init_count = ARRAY_SIZE(s4_mpll0_init_regs),
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "mpll0_div",
>> + .ops = &meson_clk_mpll_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_mpll_prediv.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_mpll0 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_MPLL_CTRL1,
>> + .bit_idx = 31,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "mpll0",
>> + .ops = &clk_regmap_gate_ops,
>> + .parent_hws = (const struct clk_hw *[]) { &s4_mpll0_div.hw },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static const struct reg_sequence s4_mpll1_init_regs[] = {
>> + { .reg = ANACTRL_MPLL_CTRL4, .def = 0x40000033 }
>> +};
>> +
>> +static struct clk_regmap s4_mpll1_div = {
>> + .data = &(struct meson_clk_mpll_data){
>> + .sdm = {
>> + .reg_off = ANACTRL_MPLL_CTRL3,
>> + .shift = 0,
>> + .width = 14,
>> + },
>> + .sdm_en = {
>> + .reg_off = ANACTRL_MPLL_CTRL3,
>> + .shift = 30,
>> + .width = 1,
>> + },
>> + .n2 = {
>> + .reg_off = ANACTRL_MPLL_CTRL3,
>> + .shift = 20,
>> + .width = 9,
>> + },
>> + .ssen = {
>> + .reg_off = ANACTRL_MPLL_CTRL3,
>> + .shift = 29,
>> + .width = 1,
>> + },
>> + .lock = &meson_clk_lock,
>> + .init_regs = s4_mpll1_init_regs,
>> + .init_count = ARRAY_SIZE(s4_mpll1_init_regs),
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "mpll1_div",
>> + .ops = &meson_clk_mpll_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_mpll_prediv.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_mpll1 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_MPLL_CTRL3,
>> + .bit_idx = 31,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "mpll1",
>> + .ops = &clk_regmap_gate_ops,
>> + .parent_hws = (const struct clk_hw *[]) { &s4_mpll1_div.hw },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static const struct reg_sequence s4_mpll2_init_regs[] = {
>> + { .reg = ANACTRL_MPLL_CTRL6, .def = 0x40000033 }
>> +};
>> +
>> +static struct clk_regmap s4_mpll2_div = {
>> + .data = &(struct meson_clk_mpll_data){
>> + .sdm = {
>> + .reg_off = ANACTRL_MPLL_CTRL5,
>> + .shift = 0,
>> + .width = 14,
>> + },
>> + .sdm_en = {
>> + .reg_off = ANACTRL_MPLL_CTRL5,
>> + .shift = 30,
>> + .width = 1,
>> + },
>> + .n2 = {
>> + .reg_off = ANACTRL_MPLL_CTRL5,
>> + .shift = 20,
>> + .width = 9,
>> + },
>> + .ssen = {
>> + .reg_off = ANACTRL_MPLL_CTRL5,
>> + .shift = 29,
>> + .width = 1,
>> + },
>> + .lock = &meson_clk_lock,
>> + .init_regs = s4_mpll2_init_regs,
>> + .init_count = ARRAY_SIZE(s4_mpll2_init_regs),
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "mpll2_div",
>> + .ops = &meson_clk_mpll_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_mpll_prediv.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_mpll2 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_MPLL_CTRL5,
>> + .bit_idx = 31,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "mpll2",
>> + .ops = &clk_regmap_gate_ops,
>> + .parent_hws = (const struct clk_hw *[]) { &s4_mpll2_div.hw },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +static const struct reg_sequence s4_mpll3_init_regs[] = {
>> + { .reg = ANACTRL_MPLL_CTRL8, .def = 0x40000033 }
>> +};
>> +
>> +static struct clk_regmap s4_mpll3_div = {
>> + .data = &(struct meson_clk_mpll_data){
>> + .sdm = {
>> + .reg_off = ANACTRL_MPLL_CTRL7,
>> + .shift = 0,
>> + .width = 14,
>> + },
>> + .sdm_en = {
>> + .reg_off = ANACTRL_MPLL_CTRL7,
>> + .shift = 30,
>> + .width = 1,
>> + },
>> + .n2 = {
>> + .reg_off = ANACTRL_MPLL_CTRL7,
>> + .shift = 20,
>> + .width = 9,
>> + },
>> + .ssen = {
>> + .reg_off = ANACTRL_MPLL_CTRL7,
>> + .shift = 29,
>> + .width = 1,
>> + },
>> + .lock = &meson_clk_lock,
>> + .init_regs = s4_mpll3_init_regs,
>> + .init_count = ARRAY_SIZE(s4_mpll3_init_regs),
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "mpll3_div",
>> + .ops = &meson_clk_mpll_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_mpll_prediv.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_mpll3 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_MPLL_CTRL7,
>> + .bit_idx = 31,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "mpll3",
>> + .ops = &clk_regmap_gate_ops,
>> + .parent_hws = (const struct clk_hw *[]) { &s4_mpll3_div.hw },
>> + .num_parents = 1,
>> + .flags = CLK_SET_RATE_PARENT,
>> + },
>> +};
>> +
>> +/* Array of all clocks provided by this provider */
>> +static struct clk_hw_onecell_data s4_pll_hw_onecell_data = {
>> + .hws = {
>> + [CLKID_FIXED_PLL_DCO] = &s4_fixed_pll_dco.hw,
>> + [CLKID_FIXED_PLL] = &s4_fixed_pll.hw,
>> + [CLKID_FCLK_DIV2_DIV] = &s4_fclk_div2_div.hw,
>> + [CLKID_FCLK_DIV2] = &s4_fclk_div2.hw,
>> + [CLKID_FCLK_DIV3_DIV] = &s4_fclk_div3_div.hw,
>> + [CLKID_FCLK_DIV3] = &s4_fclk_div3.hw,
>> + [CLKID_FCLK_DIV4_DIV] = &s4_fclk_div4_div.hw,
>> + [CLKID_FCLK_DIV4] = &s4_fclk_div4.hw,
>> + [CLKID_FCLK_DIV5_DIV] = &s4_fclk_div5_div.hw,
>> + [CLKID_FCLK_DIV5] = &s4_fclk_div5.hw,
>> + [CLKID_FCLK_DIV7_DIV] = &s4_fclk_div7_div.hw,
>> + [CLKID_FCLK_DIV7] = &s4_fclk_div7.hw,
>> + [CLKID_FCLK_DIV2P5_DIV] = &s4_fclk_div2p5_div.hw,
>> + [CLKID_FCLK_DIV2P5] = &s4_fclk_div2p5.hw,
>> + [CLKID_GP0_PLL_DCO] = &s4_gp0_pll_dco.hw,
>> + [CLKID_GP0_PLL] = &s4_gp0_pll.hw,
>> + [CLKID_HIFI_PLL_DCO] = &s4_hifi_pll_dco.hw,
>> + [CLKID_HIFI_PLL] = &s4_hifi_pll.hw,
>> + [CLKID_HDMI_PLL_DCO] = &s4_hdmi_pll_dco.hw,
>> + [CLKID_HDMI_PLL_OD] = &s4_hdmi_pll_od.hw,
>> + [CLKID_HDMI_PLL] = &s4_hdmi_pll.hw,
>> + [CLKID_MPLL_50M_DIV] = &s4_mpll_50m_div.hw,
>> + [CLKID_MPLL_50M] = &s4_mpll_50m.hw,
>> + [CLKID_MPLL_PREDIV] = &s4_mpll_prediv.hw,
>> + [CLKID_MPLL0_DIV] = &s4_mpll0_div.hw,
>> + [CLKID_MPLL0] = &s4_mpll0.hw,
>> + [CLKID_MPLL1_DIV] = &s4_mpll1_div.hw,
>> + [CLKID_MPLL1] = &s4_mpll1.hw,
>> + [CLKID_MPLL2_DIV] = &s4_mpll2_div.hw,
>> + [CLKID_MPLL2] = &s4_mpll2.hw,
>> + [CLKID_MPLL3_DIV] = &s4_mpll3_div.hw,
>> + [CLKID_MPLL3] = &s4_mpll3.hw,
>> + [NR_PLL_CLKS] = NULL
>> + },
>> + .num = NR_PLL_CLKS,
>> +};
>> +
>> +static struct clk_regmap *const s4_pll_clk_regmaps[] = {
>> + &s4_fixed_pll_dco,
>> + &s4_fixed_pll,
>> + &s4_fclk_div2,
>> + &s4_fclk_div3,
>> + &s4_fclk_div4,
>> + &s4_fclk_div5,
>> + &s4_fclk_div7,
>> + &s4_fclk_div2p5,
>> + &s4_gp0_pll_dco,
>> + &s4_gp0_pll,
>> + &s4_hifi_pll_dco,
>> + &s4_hifi_pll,
>> + &s4_hdmi_pll_dco,
>> + &s4_hdmi_pll_od,
>> + &s4_hdmi_pll,
>> + &s4_mpll_50m,
>> + &s4_mpll0_div,
>> + &s4_mpll0,
>> + &s4_mpll1_div,
>> + &s4_mpll1,
>> + &s4_mpll2_div,
>> + &s4_mpll2,
>> + &s4_mpll3_div,
>> + &s4_mpll3,
>> +};
>> +
>> +static const struct reg_sequence s4_init_regs[] = {
>> + { .reg = ANACTRL_MPLL_CTRL0, .def = 0x00000543 },
>> +};
>> +
>> +static struct regmap_config clkc_regmap_config = {
>> + .reg_bits = 32,
>> + .val_bits = 32,
>> + .reg_stride = 4,
>> +};
>> +
>> +static int meson_s4_pll_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct regmap *regmap;
>> + void __iomem *base;
>> + int ret, i;
>> +
>> + base = devm_platform_ioremap_resource(pdev, 0);
>> + if (IS_ERR(base))
>> + return PTR_ERR(base);
>> +
>> + regmap = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
>> + if (IS_ERR(regmap))
>> + return PTR_ERR(regmap);
>> +
>> + ret = regmap_multi_reg_write(regmap, s4_init_regs, ARRAY_SIZE(s4_init_regs));
>> + if (ret) {
>> + dev_err(dev, "Failed to init registers\n");
>> + return ret;
>> + }
>> +
>> + /* Populate regmap for the regmap backed clocks */
>> + for (i = 0; i < ARRAY_SIZE(s4_pll_clk_regmaps); i++)
>> + s4_pll_clk_regmaps[i]->map = regmap;
>> +
>> + for (i = 0; i < s4_pll_hw_onecell_data.num; i++) {
>> + /* array might be sparse */
>> + if (!s4_pll_hw_onecell_data.hws[i])
>> + continue;
>> +
>> + ret = devm_clk_hw_register(dev, s4_pll_hw_onecell_data.hws[i]);
>> + if (ret) {
>> + dev_err(dev, "Clock registration failed\n");
>> + return ret;
>> + }
>> + }
>> +
>> + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
>> + &s4_pll_hw_onecell_data);
>> +}
>> +
>> +static const struct of_device_id clkc_match_table[] = {
>> + {
>> + .compatible = "amlogic,s4-pll-clkc",
>> + },
>> + {}
>> +};
>> +
>> +static struct platform_driver s4_driver = {
>> + .probe = meson_s4_pll_probe,
>> + .driver = {
>> + .name = "s4-pll-clkc",
>> + .of_match_table = clkc_match_table,
>> + },
>> +};
>> +
>> +module_platform_driver(s4_driver);
>> +MODULE_LICENSE("GPL");
>> diff --git a/drivers/clk/meson/s4-pll.h b/drivers/clk/meson/s4-pll.h
>> new file mode 100644
>> index 000000000000..021d9f8b2b30
>> --- /dev/null
>> +++ b/drivers/clk/meson/s4-pll.h
>> @@ -0,0 +1,87 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>> +/*
>> + * Copyright (c) 2021 Amlogic, inc.
>> + * Author: Yu Tu <yu.tu@amlogic.com>
>> + */
>> +
>> +#ifndef __MESON_S4_PLL_H__
>> +#define __MESON_S4_PLL_H__
>> +
>> +/* ANA_CTRL - Registers */
>> +
>> +#define ANACTRL_FIXPLL_CTRL0 0x040
>> +#define ANACTRL_FIXPLL_CTRL1 0x044
>> +#define ANACTRL_FIXPLL_CTRL2 0x048
>> +#define ANACTRL_FIXPLL_CTRL3 0x04c
>> +#define ANACTRL_FIXPLL_CTRL4 0x050
>> +#define ANACTRL_FIXPLL_CTRL5 0x054
>> +#define ANACTRL_FIXPLL_CTRL6 0x058
>> +#define ANACTRL_FIXPLL_STS 0x05c
>> +#define ANACTRL_GP0PLL_CTRL0 0x080
>> +#define ANACTRL_GP0PLL_CTRL1 0x084
>> +#define ANACTRL_GP0PLL_CTRL2 0x088
>> +#define ANACTRL_GP0PLL_CTRL3 0x08c
>> +#define ANACTRL_GP0PLL_CTRL4 0x090
>> +#define ANACTRL_GP0PLL_CTRL5 0x094
>> +#define ANACTRL_GP0PLL_CTRL6 0x098
>> +#define ANACTRL_GP0PLL_STS 0x09c
>> +#define ANACTRL_HIFIPLL_CTRL0 0x100
>> +#define ANACTRL_HIFIPLL_CTRL1 0x104
>> +#define ANACTRL_HIFIPLL_CTRL2 0x108
>> +#define ANACTRL_HIFIPLL_CTRL3 0x10c
>> +#define ANACTRL_HIFIPLL_CTRL4 0x110
>> +#define ANACTRL_HIFIPLL_CTRL5 0x114
>> +#define ANACTRL_HIFIPLL_CTRL6 0x118
>> +#define ANACTRL_HIFIPLL_STS 0x11c
>> +#define ANACTRL_MPLL_CTRL0 0x180
>> +#define ANACTRL_MPLL_CTRL1 0x184
>> +#define ANACTRL_MPLL_CTRL2 0x188
>> +#define ANACTRL_MPLL_CTRL3 0x18c
>> +#define ANACTRL_MPLL_CTRL4 0x190
>> +#define ANACTRL_MPLL_CTRL5 0x194
>> +#define ANACTRL_MPLL_CTRL6 0x198
>> +#define ANACTRL_MPLL_CTRL7 0x19c
>> +#define ANACTRL_MPLL_CTRL8 0x1a0
>> +#define ANACTRL_MPLL_STS 0x1a4
>> +#define ANACTRL_HDMIPLL_CTRL0 0x1c0
>> +#define ANACTRL_HDMIPLL_CTRL1 0x1c4
>> +#define ANACTRL_HDMIPLL_CTRL2 0x1c8
>> +#define ANACTRL_HDMIPLL_CTRL3 0x1cc
>> +#define ANACTRL_HDMIPLL_CTRL4 0x1d0
>> +#define ANACTRL_HDMIPLL_CTRL5 0x1d4
>> +#define ANACTRL_HDMIPLL_CTRL6 0x1d8
>> +#define ANACTRL_HDMIPLL_STS 0x1dc
>> +#define ANACTRL_HDMIPLL_VLOCK 0x1e4
>> +
>> +/*
>> + * CLKID index values
>> + *
>> + * These indices are entirely contrived and do not map onto the hardware.
>> + * It has now been decided to expose everything by default in the DT header:
>> + * include/dt-bindings/clock/amlogic,s4-pll-clkc.h. Only the clocks ids we don't
>> + * want to expose, such as the internal muxes and dividers of composite clocks,
>> + * will remain defined here.
>> + */
>> +#define CLKID_FIXED_PLL_DCO 0
>> +#define CLKID_FCLK_DIV2_DIV 2
>> +#define CLKID_FCLK_DIV3_DIV 4
>> +#define CLKID_FCLK_DIV4_DIV 6
>> +#define CLKID_FCLK_DIV5_DIV 8
>> +#define CLKID_FCLK_DIV7_DIV 10
>> +#define CLKID_FCLK_DIV2P5_DIV 12
>> +#define CLKID_GP0_PLL_DCO 14
>> +#define CLKID_HIFI_PLL_DCO 16
>> +#define CLKID_HDMI_PLL_DCO 18
>> +#define CLKID_HDMI_PLL_OD 19
>> +#define CLKID_MPLL_50M_DIV 21
>> +#define CLKID_MPLL_PREDIV 23
>> +#define CLKID_MPLL0_DIV 24
>> +#define CLKID_MPLL1_DIV 26
>> +#define CLKID_MPLL2_DIV 28
>> +#define CLKID_MPLL3_DIV 30
>> +
>> +#define NR_PLL_CLKS 32
>> +/* include the CLKIDs that have been made part of the DT binding */
>> +#include <dt-bindings/clock/amlogic,s4-pll-clkc.h>
>> +
>> +#endif /* __MESON_S4_PLL_H__ */
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH V9 4/4] clk: meson: s4: add support for Amlogic S4 SoC peripheral clock controller
2023-06-06 15:38 ` [PATCH V9 4/4] clk: meson: s4: add support for Amlogic S4 SoC peripheral clock controller Dmitry Rokosov
@ 2023-06-08 3:26 ` Yu Tu
0 siblings, 0 replies; 15+ messages in thread
From: Yu Tu @ 2023-06-08 3:26 UTC (permalink / raw)
To: Dmitry Rokosov
Cc: Jerome Brunet, linux-clk, linux-arm-kernel, linux-amlogic,
linux-kernel, devicetree, Rob Herring, Neil Armstrong,
Kevin Hilman, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Conor Dooley, Martin Blumenstingl,
kelvin.zhang, qi.duan
Hi Dmitry,
On 2023/6/6 23:38, Dmitry Rokosov wrote:
> [ EXTERNAL EMAIL ]
>
> Hello Yu,
>
> On Tue, Jun 06, 2023 at 04:38:15PM +0200, Jerome Brunet wrote:
>>
>> On Wed 17 May 2023 at 15:02, Yu Tu <yu.tu@amlogic.com> wrote:
>>
>>> Add the peripherals clock controller driver in the s4 SoC family.
>>>
>>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>>> ---
>>> drivers/clk/meson/Kconfig | 12 +
>>> drivers/clk/meson/Makefile | 1 +
>>> drivers/clk/meson/s4-peripherals.c | 3830 ++++++++++++++++++++++++++++
>>> drivers/clk/meson/s4-peripherals.h | 217 ++
>>> 4 files changed, 4060 insertions(+)
>>> create mode 100644 drivers/clk/meson/s4-peripherals.c
>>> create mode 100644 drivers/clk/meson/s4-peripherals.h
>>>
>>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>>> index a663c90a3f3b..a6eb9fa15c74 100644
>>> --- a/drivers/clk/meson/Kconfig
>>> +++ b/drivers/clk/meson/Kconfig
>>> @@ -128,4 +128,16 @@ config COMMON_CLK_S4_PLL
>>> aka s4. Amlogic S805X2 and S905Y4 devices include AQ222 and AQ229.
>>> Say Y if you want the board to work, because plls are the parent of most
>>> peripherals.
>>> +
>>> +config COMMON_CLK_S4
>>> + tristate "S4 SoC Peripherals clock controllers support"
>>> + depends on ARM64
>>> + default y
>>> + select COMMON_CLK_MESON_REGMAP
>>> + select COMMON_CLK_MESON_DUALDIV
>>> + select COMMON_CLK_MESON_VID_PLL_DIV
>>> + help
>>> + Support for the Peripherals clock controller on Amlogic S805X2 and S905Y4
>>> + devices, aka s4. Amlogic S805X2 and S905Y4 devices include AQ222 and AQ229.
>>> + Say Y if you want peripherals to work.
>>> endmenu
>
> [...]
>
>>> +static struct clk_regmap s4_rtc_32k_by_oscin = {
>>> + .data = &(struct clk_regmap_gate_data){
>>> + .offset = CLKCTRL_RTC_BY_OSCIN_CTRL0,
>>> + .bit_idx = 30,
>>> + },
>>> + .hw.init = &(struct clk_init_data) {
>>> + .name = "rtc_32k_by_oscin",
>>> + .ops = &clk_regmap_gate_ops,
>>> + .parent_hws = (const struct clk_hw *[]) {
>>> + &s4_rtc_32k_by_oscin_sel.hw
>>> + },
>>> + .num_parents = 1,
>>> + .flags = CLK_SET_RATE_PARENT,
>>> + },
>>> +};
>>> +
>>> +/*
>>> + * This RTC clock can be supplied by an external 32KHz crystal oscillator.
>>> + * If it is used, it should be documented in using fw_name and documented in the
>>> + * Bindings. Not currently in use on this board.
>>> + */
>>
>> This is confusing and not really helpful
>> What you describe here is simply the purpose of fw_name ... so it does
>> not warrant a specific comment
>>
>>> +static const struct clk_parent_data rtc_clk_sel_parent_data[] = {
>>> + { .hw = &s4_rtc_32k_by_oscin.hw },
>>> + { .hw = &s4_rtc_32k_by_oscin_div.hw },
>>> + { .fw_name = "ext_32k", }
>>> +};
>>> +
>>> +/*
>>> + * All clocks that can be inherited from a more accurate RTC clock are marked
>>> + * with the CLK_SET_RATE_NO_REPARENT flag. This is because in certain
>>> + * situations, we may need to freeze their parent. The parent setup of these
>>> + * clocks should be located on the device tree side.
>>> + */
>>
>> It looks like the consensus is that CLK_SET_RATE_NO_REPARENT is not
>> required. Please have at look at the discussion between Dmitry and
>> Martin for the a1 controller
>>
>
> I hope below links will be helpful for you:
>
> CLK_SET_RATE_NO_REPARENT IRC discussion:
> https://libera.irclog.whitequark.org/linux-amlogic/2023-05-18
>
> Clock driver LKML discussion about CLK_SET_RATE_NO_REPARENT:
> https://lore.kernel.org/all/20230530120640.irugyrio3qa7czjy@CAB-WSD-L081021/
> https://lore.kernel.org/all/20230524092750.ldm362chnpkwkcj4@CAB-WSD-L081021/
>
> PWM discussion about special RTC case:
> https://lore.kernel.org/all/20230522133739.7tc35zr2npsysopd@CAB-WSD-L081021/
>
> And I apologize for any confusion I may have caused in our previous
> discussion. I want to clarify that I have updated the implementation
> of CLK_SET_RATE_NO_REPARENT after discussing it with Martin...
>
> [...]
Thank you so much for your comments.
>
> --
> Thank you,
> Dmitry
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH V9 3/4] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver
2023-06-08 2:54 ` Yu Tu
@ 2023-06-08 8:53 ` Jerome Brunet
2023-06-08 9:30 ` Yu Tu
2023-06-08 11:32 ` Dmitry Rokosov
0 siblings, 2 replies; 15+ messages in thread
From: Jerome Brunet @ 2023-06-08 8:53 UTC (permalink / raw)
To: Yu Tu, linux-clk, linux-arm-kernel, linux-amlogic, linux-kernel,
devicetree, Rob Herring, Neil Armstrong, Kevin Hilman,
Michael Turquette, Stephen Boyd, Krzysztof Kozlowski,
Conor Dooley, Martin Blumenstingl
Cc: kelvin.zhang, qi.duan
>>> +
>>> +static struct clk_regmap s4_fclk_div4 = {
>>> + .data = &(struct clk_regmap_gate_data){
>>> + .offset = ANACTRL_FIXPLL_CTRL1,
>>> + .bit_idx = 21,
>>> + },
>>> + .hw.init = &(struct clk_init_data){
>>> + .name = "fclk_div4",
>>> + /*
>>> + * For more information, please refer to s4_fixed_pll_dco.
>>> + */
>> While div2 and div3 got an explanation from previous SoCs, they others -
>> like div4/div7/etc ... - have been able to cope with rw ops so far.
>> Why is the S4 different for all these clocks ?
>
> The chip was changed fixed pll for security reasons.
>
> Fixed PLL registers are not writable in the kernel phase. Write of fixed
> PLL-related register will cause the system to crash.
>
That is definitely worth mentionning
>> Requiring RO ops (or fishy clock flags) is usually a sign that a clock
>> is used without an appropriate driver.
>>
Neil is currently dealing with the dt-bindings, please
* Adjust your patchset accordingly
* Wait for his v2 to land, you'll need it.
>>> + .ops = &clk_regmap_gate_ro_ops,
>>> + .parent_hws = (const struct clk_hw *[]) {
>>> + &s4_fclk_div4_div.hw
>>> + },
>>> + .num_parents = 1,
>>> + },
>>> +};
>>> +
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH V9 3/4] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver
2023-06-08 8:53 ` Jerome Brunet
@ 2023-06-08 9:30 ` Yu Tu
2023-06-08 11:32 ` Dmitry Rokosov
1 sibling, 0 replies; 15+ messages in thread
From: Yu Tu @ 2023-06-08 9:30 UTC (permalink / raw)
To: Jerome Brunet, linux-clk, linux-arm-kernel, linux-amlogic,
linux-kernel, devicetree, Rob Herring, Neil Armstrong,
Kevin Hilman, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Conor Dooley, Martin Blumenstingl
Cc: kelvin.zhang, qi.duan
On 2023/6/8 16:53, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
>>>> +
>>>> +static struct clk_regmap s4_fclk_div4 = {
>>>> + .data = &(struct clk_regmap_gate_data){
>>>> + .offset = ANACTRL_FIXPLL_CTRL1,
>>>> + .bit_idx = 21,
>>>> + },
>>>> + .hw.init = &(struct clk_init_data){
>>>> + .name = "fclk_div4",
>>>> + /*
>>>> + * For more information, please refer to s4_fixed_pll_dco.
>>>> + */
>>> While div2 and div3 got an explanation from previous SoCs, they others -
>>> like div4/div7/etc ... - have been able to cope with rw ops so far.
>>> Why is the S4 different for all these clocks ?
>>
>> The chip was changed fixed pll for security reasons.
>>
>> Fixed PLL registers are not writable in the kernel phase. Write of fixed
>> PLL-related register will cause the system to crash.
>>
>
> That is definitely worth mentionning
Can I understand that you agree with the use of "ro_ops" for FIXed PLL
related clocks later?
>
>>> Requiring RO ops (or fishy clock flags) is usually a sign that a clock
>>> is used without an appropriate driver.
>>>
>
> Neil is currently dealing with the dt-bindings, please
> * Adjust your patchset accordingly
> * Wait for his v2 to land, you'll need it.
OKay.
>
>>>> + .ops = &clk_regmap_gate_ro_ops,
>>>> + .parent_hws = (const struct clk_hw *[]) {
>>>> + &s4_fclk_div4_div.hw
>>>> + },
>>>> + .num_parents = 1,
>>>> + },
>>>> +};
>>>> +
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH V9 3/4] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver
2023-06-08 8:53 ` Jerome Brunet
2023-06-08 9:30 ` Yu Tu
@ 2023-06-08 11:32 ` Dmitry Rokosov
2023-06-08 12:46 ` Jerome Brunet
1 sibling, 1 reply; 15+ messages in thread
From: Dmitry Rokosov @ 2023-06-08 11:32 UTC (permalink / raw)
To: Jerome Brunet
Cc: Yu Tu, linux-clk, linux-arm-kernel, linux-amlogic, linux-kernel,
devicetree, Rob Herring, Neil Armstrong, Kevin Hilman,
Michael Turquette, Stephen Boyd, Krzysztof Kozlowski,
Conor Dooley, Martin Blumenstingl, kelvin.zhang, qi.duan
Hello Jerome,
On Thu, Jun 08, 2023 at 10:53:31AM +0200, Jerome Brunet wrote:
>
> >>> +
> >>> +static struct clk_regmap s4_fclk_div4 = {
> >>> + .data = &(struct clk_regmap_gate_data){
> >>> + .offset = ANACTRL_FIXPLL_CTRL1,
> >>> + .bit_idx = 21,
> >>> + },
> >>> + .hw.init = &(struct clk_init_data){
> >>> + .name = "fclk_div4",
> >>> + /*
> >>> + * For more information, please refer to s4_fixed_pll_dco.
> >>> + */
> >> While div2 and div3 got an explanation from previous SoCs, they others -
> >> like div4/div7/etc ... - have been able to cope with rw ops so far.
> >> Why is the S4 different for all these clocks ?
> >
> > The chip was changed fixed pll for security reasons.
> >
> > Fixed PLL registers are not writable in the kernel phase. Write of fixed
> > PLL-related register will cause the system to crash.
> >
>
> That is definitely worth mentionning
>
> >> Requiring RO ops (or fishy clock flags) is usually a sign that a clock
> >> is used without an appropriate driver.
> >>
>
> Neil is currently dealing with the dt-bindings, please
> * Adjust your patchset accordingly
> * Wait for his v2 to land, you'll need it.
>
I saw Neil patch series with merging 'private' and 'public' clock
bindings parts. Should I send the same patchset for a1 clocks after v6.5
landed?
> >>> + .ops = &clk_regmap_gate_ro_ops,
> >>> + .parent_hws = (const struct clk_hw *[]) {
> >>> + &s4_fclk_div4_div.hw
> >>> + },
> >>> + .num_parents = 1,
> >>> + },
> >>> +};
> >>> +
>
> _______________________________________________
> linux-amlogic mailing list
> linux-amlogic@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic
--
Thank you,
Dmitry
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH V9 3/4] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver
2023-06-08 11:32 ` Dmitry Rokosov
@ 2023-06-08 12:46 ` Jerome Brunet
2023-06-08 21:02 ` Dmitry Rokosov
0 siblings, 1 reply; 15+ messages in thread
From: Jerome Brunet @ 2023-06-08 12:46 UTC (permalink / raw)
To: Dmitry Rokosov
Cc: Yu Tu, linux-clk, linux-arm-kernel, linux-amlogic, linux-kernel,
devicetree, Rob Herring, Neil Armstrong, Kevin Hilman,
Michael Turquette, Stephen Boyd, Krzysztof Kozlowski,
Conor Dooley, Martin Blumenstingl, kelvin.zhang, qi.duan
On Thu 08 Jun 2023 at 14:32, Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
>>
>> Neil is currently dealing with the dt-bindings, please
>> * Adjust your patchset accordingly
>> * Wait for his v2 to land, you'll need it.
>>
>
> I saw Neil patch series with merging 'private' and 'public' clock
> bindings parts. Should I send the same patchset for a1 clocks after v6.5
> landed?
>
I think Neil's patchset is already dealing with the a1.
We'll see if it can be part of this cycle PR. I don't want to rush
anything and rc6 is coming this monday. It may have to wait for the next cycle.
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH V9 3/4] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver
2023-06-08 12:46 ` Jerome Brunet
@ 2023-06-08 21:02 ` Dmitry Rokosov
0 siblings, 0 replies; 15+ messages in thread
From: Dmitry Rokosov @ 2023-06-08 21:02 UTC (permalink / raw)
To: Jerome Brunet
Cc: Yu Tu, linux-clk, linux-arm-kernel, linux-amlogic, linux-kernel,
devicetree, Rob Herring, Neil Armstrong, Kevin Hilman,
Michael Turquette, Stephen Boyd, Krzysztof Kozlowski,
Conor Dooley, Martin Blumenstingl, kelvin.zhang, qi.duan
On Thu, Jun 08, 2023 at 02:46:54PM +0200, Jerome Brunet wrote:
>
> On Thu 08 Jun 2023 at 14:32, Dmitry Rokosov <ddrokosov@sberdevices.ru> wrote:
> >>
> >> Neil is currently dealing with the dt-bindings, please
> >> * Adjust your patchset accordingly
> >> * Wait for his v2 to land, you'll need it.
> >>
> >
> > I saw Neil patch series with merging 'private' and 'public' clock
> > bindings parts. Should I send the same patchset for a1 clocks after v6.5
> > landed?
> >
>
> I think Neil's patchset is already dealing with the a1.
>
> We'll see if it can be part of this cycle PR. I don't want to rush
> anything and rc6 is coming this monday. It may have to wait for the next cycle.
Alright, I understand. Please let me know if and when you need
assistance, as I am ready to help.
--
Thank you,
Dmitry
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2023-06-08 21:02 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-05-17 7:02 [PATCH V9 0/4] Add S4 SoC PLL and Peripheral clock Yu Tu
2023-05-17 7:02 ` [PATCH V9 1/4] dt-bindings: clock: document Amlogic S4 SoC PLL clock controller Yu Tu
2023-05-17 7:02 ` [PATCH V9 2/4] dt-bindings: clock: document Amlogic S4 SoC peripherals " Yu Tu
2023-05-17 7:02 ` [PATCH V9 3/4] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver Yu Tu
2023-06-06 14:02 ` Jerome Brunet
2023-06-08 2:54 ` Yu Tu
2023-06-08 8:53 ` Jerome Brunet
2023-06-08 9:30 ` Yu Tu
2023-06-08 11:32 ` Dmitry Rokosov
2023-06-08 12:46 ` Jerome Brunet
2023-06-08 21:02 ` Dmitry Rokosov
2023-06-06 14:34 ` Jerome Brunet
2023-06-08 2:29 ` Yu Tu
[not found] ` <20230517070215.28463-5-yu.tu@amlogic.com>
[not found] ` <1jwn0g39t2.fsf@starbuckisacylon.baylibre.com>
2023-06-06 15:38 ` [PATCH V9 4/4] clk: meson: s4: add support for Amlogic S4 SoC peripheral clock controller Dmitry Rokosov
2023-06-08 3:26 ` Yu Tu
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