* [PATCH] clk: qcom: Add Global Clock controller (GCC) driver for SDM660
[not found] <20180407135934.26122-1-ctatlor97@gmail.com>
@ 2018-08-10 20:21 ` Craig Tatlor
2018-08-11 21:30 ` kbuild test robot
` (4 more replies)
0 siblings, 5 replies; 18+ messages in thread
From: Craig Tatlor @ 2018-08-10 20:21 UTC (permalink / raw)
Cc: ctatlor97, linux-arm-msm, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Andy Gross, David Brown, linux-clk,
devicetree, linux-kernel, linux-soc
Add support for the global clock controller found on SDM660
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Based on CAF implementation.
Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
---
.../devicetree/bindings/clock/qcom,gcc.txt | 1 +
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-sdm660.c | 2479 +++++++++++++++++
include/dt-bindings/clock/qcom,gcc-sdm660.h | 159 ++
5 files changed, 2649 insertions(+)
create mode 100644 drivers/clk/qcom/gcc-sdm660.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-sdm660.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 664ea1fd6c76..e498ad2e8db8 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -19,6 +19,7 @@ Required properties :
"qcom,gcc-msm8996"
"qcom,gcc-msm8998"
"qcom,gcc-mdm9615"
+ "qcom,gcc-sdm660"
"qcom,gcc-sdm845"
- reg : shall contain base register location and length
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 9c3480dcc38a..c4bda6d24c1f 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -226,6 +226,15 @@ config MSM_GCC_8998
Say Y if you want to use peripheral devices such as UART, SPI,
i2c, USB, UFS, SD/eMMC, PCIe, etc.
+config SDM_GCC_660
+ tristate "SDM660 Global Clock Controller"
+ select QCOM_GDSC
+ depends on COMMON_CLK_QCOM
+ help
+ Support for the global clock controller on SDM660 devices.
+ Say Y if you want to use peripheral devices such as UART, SPI,
+ i2C, USB, UFS, SDDC, PCIe, etc.
+
config SDM_GCC_845
tristate "SDM845 Global Clock Controller"
select QCOM_GDSC
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 762c01137c2f..6e37d30d7c02 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o
obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o
obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
+obj-$(CONFIG_SDM_GCC_660) += gcc-sdm660.o
obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
new file mode 100644
index 000000000000..bdb445aa4baa
--- /dev/null
+++ b/drivers/clk/qcom/gcc-sdm660.c
@@ -0,0 +1,2479 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018, Craig Tatlor.
+ */
+
+#include <linux/kernel.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/clock/qcom,gcc-sdm660.h>
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-alpha-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "reset.h"
+#include "gdsc.h"
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+enum {
+ P_XO,
+ P_SLEEP_CLK,
+ P_GPLL0,
+ P_GPLL1,
+ P_GPLL4,
+ P_GPLL0_EARLY_DIV,
+ P_GPLL1_EARLY_DIV,
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_EARLY_DIV, 6 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div[] = {
+ "xo",
+ "gpll0",
+ "gpll0_early_div",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0[] = {
+ "xo",
+ "gpll0",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_SLEEP_CLK, 5 },
+ { P_GPLL0_EARLY_DIV, 6 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div[] = {
+ "xo",
+ "gpll0",
+ "sleep_clk",
+ "gpll0_early_div",
+};
+
+static const struct parent_map gcc_parent_map_xo_sleep_clk[] = {
+ { P_XO, 0 },
+ { P_SLEEP_CLK, 5 },
+};
+
+static const char * const gcc_parent_names_xo_sleep_clk[] = {
+ "xo",
+ "sleep_clk",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll4[] = {
+ { P_XO, 0 },
+ { P_GPLL4, 5 },
+};
+
+static const char * const gcc_parent_names_xo_gpll4[] = {
+ "xo",
+ "gpll4",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_EARLY_DIV, 3 },
+ { P_GPLL1, 4 },
+ { P_GPLL4, 5 },
+ { P_GPLL1_EARLY_DIV, 6 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
+ "xo",
+ "gpll0",
+ "gpll0_early_div",
+ "gpll1",
+ "gpll4",
+ "gpll1_early_div",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL4, 5 },
+ { P_GPLL0_EARLY_DIV, 6 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div[] = {
+ "xo",
+ "gpll0",
+ "gpll4",
+ "gpll0_early_div",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_EARLY_DIV, 2 },
+ { P_GPLL4, 5 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4[] = {
+ "xo",
+ "gpll0",
+ "gpll0_early_div",
+ "gpll4",
+};
+
+static struct clk_fixed_factor xo = {
+ .mult = 1,
+ .div = 1,
+ .hw.init = &(struct clk_init_data){
+ .name = "xo",
+ .parent_names = (const char *[]){ "xo_board" },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll0_early = {
+ .offset = 0x0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_early",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor gpll0_early_div = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_early_div",
+ .parent_names = (const char *[]){ "gpll0_early" },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll0 = {
+ .offset = 0x00000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll0",
+ .parent_names = (const char *[]){ "gpll0_early" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll1_early = {
+ .offset = 0x1000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll1_early",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor gpll1_early_div = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll1_early_div",
+ .parent_names = (const char *[]){ "gpll1_early" },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll1 = {
+ .offset = 0x1000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll1",
+ .parent_names = (const char *[]){ "gpll1_early" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll4_early = {
+ .offset = 0x77000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll4_early",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll4 = {
+ .offset = 0x77000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "gpll4",
+ .parent_names = (const char *[]) { "gpll4_early" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(50000000, P_GPLL0, 12, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x19020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup1_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(50000000, P_GPLL0, 12, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
+ .cmd_rcgr = 0x1900c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup1_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x1b020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup2_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
+ .cmd_rcgr = 0x1b00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup2_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x1d020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup3_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
+ .cmd_rcgr = 0x1d00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup3_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x1f020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup4_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
+ .cmd_rcgr = 0x1f00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup4_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
+ F(3686400, P_GPLL0, 1, 96, 15625),
+ F(7372800, P_GPLL0, 1, 192, 15625),
+ F(14745600, P_GPLL0, 1, 384, 15625),
+ F(16000000, P_GPLL0, 5, 2, 15),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 5, 1, 5),
+ F(32000000, P_GPLL0, 1, 4, 75),
+ F(40000000, P_GPLL0, 15, 0, 0),
+ F(46400000, P_GPLL0, 1, 29, 375),
+ F(48000000, P_GPLL0, 12.5, 0, 0),
+ F(51200000, P_GPLL0, 1, 32, 375),
+ F(56000000, P_GPLL0, 1, 7, 75),
+ F(58982400, P_GPLL0, 1, 1536, 15625),
+ F(60000000, P_GPLL0, 10, 0, 0),
+ F(63157895, P_GPLL0, 9.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
+ .cmd_rcgr = 0x1a00c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart1_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
+ .cmd_rcgr = 0x1c00c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart2_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x26020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup1_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
+ .cmd_rcgr = 0x2600c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup1_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x28020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup2_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
+ .cmd_rcgr = 0x2800c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup2_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x2a020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup3_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
+ .cmd_rcgr = 0x2a00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup3_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x2c020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup4_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
+ .cmd_rcgr = 0x2c00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup4_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
+ .cmd_rcgr = 0x2700c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_uart1_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
+ .cmd_rcgr = 0x2900c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_uart2_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gp1_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gp1_clk_src = {
+ .cmd_rcgr = 0x64004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
+ .freq_tbl = ftbl_gp1_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp1_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gp2_clk_src = {
+ .cmd_rcgr = 0x65004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
+ .freq_tbl = ftbl_gp1_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp2_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gp3_clk_src = {
+ .cmd_rcgr = 0x66004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
+ .freq_tbl = ftbl_gp1_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp3_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] = {
+ F(300000000, P_GPLL0, 2, 0, 0),
+ F(600000000, P_GPLL0, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 hmss_gpll0_clk_src = {
+ .cmd_rcgr = 0x4805c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_hmss_gpll0_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "hmss_gpll0_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_hmss_gpll4_clk_src[] = {
+ F(384000000, P_GPLL4, 4, 0, 0),
+ F(768000000, P_GPLL4, 2, 0, 0),
+ F(1536000000, P_GPLL4, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 hmss_gpll4_clk_src = {
+ .cmd_rcgr = 0x48074,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll4,
+ .freq_tbl = ftbl_hmss_gpll4_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "hmss_gpll4_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll4,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 hmss_rbcpr_clk_src = {
+ .cmd_rcgr = 0x48044,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_hmss_rbcpr_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "hmss_rbcpr_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_pdm2_clk_src[] = {
+ F(60000000, P_GPLL0, 10, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 pdm2_clk_src = {
+ .cmd_rcgr = 0x33010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_pdm2_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pdm2_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(80200000, P_GPLL1_EARLY_DIV, 5, 0, 0),
+ F(160400000, P_GPLL1, 5, 0, 0),
+ F(267333333, P_GPLL1, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 qspi_ser_clk_src = {
+ .cmd_rcgr = 0x4d00c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
+ .freq_tbl = ftbl_qspi_ser_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "qspi_ser_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
+ .num_parents = 6,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
+ F(144000, P_XO, 16, 3, 25),
+ F(400000, P_XO, 12, 1, 4),
+ F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
+ F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
+ F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(192000000, P_GPLL4, 8, 0, 0),
+ F(384000000, P_GPLL4, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 sdcc1_apps_clk_src = {
+ .cmd_rcgr = 0x1602c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div,
+ .freq_tbl = ftbl_sdcc1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc1_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
+ F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ F(300000000, P_GPLL0, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 sdcc1_ice_core_clk_src = {
+ .cmd_rcgr = 0x16010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc1_ice_core_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
+ F(144000, P_XO, 16, 3, 25),
+ F(400000, P_XO, 12, 1, 4),
+ F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
+ F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
+ F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(192000000, P_GPLL4, 8, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 sdcc2_apps_clk_src = {
+ .cmd_rcgr = 0x14010,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4,
+ .freq_tbl = ftbl_sdcc2_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc2_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
+ F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ F(240000000, P_GPLL0, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ufs_axi_clk_src = {
+ .cmd_rcgr = 0x75018,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_ufs_axi_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ufs_axi_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
+ F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ F(300000000, P_GPLL0, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ufs_ice_core_clk_src = {
+ .cmd_rcgr = 0x76010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_ufs_ice_core_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ufs_ice_core_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 ufs_phy_aux_clk_src = {
+ .cmd_rcgr = 0x76044,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_sleep_clk,
+ .freq_tbl = ftbl_hmss_rbcpr_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ufs_phy_aux_clk_src",
+ .parent_names = gcc_parent_names_xo_sleep_clk,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = {
+ F(37500000, P_GPLL0_EARLY_DIV, 8, 0, 0),
+ F(75000000, P_GPLL0, 8, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ufs_unipro_core_clk_src = {
+ .cmd_rcgr = 0x76028,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_ufs_unipro_core_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ufs_unipro_core_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(60000000, P_GPLL0, 10, 0, 0),
+ F(120000000, P_GPLL0, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb20_master_clk_src = {
+ .cmd_rcgr = 0x2f010,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_usb20_master_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb20_master_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb20_mock_utmi_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(60000000, P_GPLL0, 10, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb20_mock_utmi_clk_src = {
+ .cmd_rcgr = 0x2f024,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_usb20_mock_utmi_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb20_mock_utmi_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(66666667, P_GPLL0_EARLY_DIV, 4.5, 0, 0),
+ F(120000000, P_GPLL0, 5, 0, 0),
+ F(133333333, P_GPLL0, 4.5, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ F(240000000, P_GPLL0, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb30_master_clk_src = {
+ .cmd_rcgr = 0xf014,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_usb30_master_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb30_master_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(40000000, P_GPLL0_EARLY_DIV, 7.5, 0, 0),
+ F(60000000, P_GPLL0, 10, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb30_mock_utmi_clk_src = {
+ .cmd_rcgr = 0xf028,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb30_mock_utmi_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
+ F(1200000, P_XO, 16, 0, 0),
+ F(19200000, P_XO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb3_phy_aux_clk_src = {
+ .cmd_rcgr = 0x5000c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_sleep_clk,
+ .freq_tbl = ftbl_usb3_phy_aux_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb3_phy_aux_clk_src",
+ .parent_names = gcc_parent_names_xo_sleep_clk,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_branch gcc_aggre2_ufs_axi_clk = {
+ .halt_reg = 0x75034,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x75034,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_aggre2_ufs_axi_clk",
+ .parent_names = (const char *[]){
+ "ufs_axi_clk_src",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_aggre2_usb3_axi_clk = {
+ .halt_reg = 0xf03c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf03c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_aggre2_usb3_axi_clk",
+ .parent_names = (const char *[]){
+ "usb30_master_clk_src",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_bimc_gfx_clk = {
+ .halt_reg = 0x7106c,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x7106c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_bimc_gfx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_bimc_hmss_axi_clk = {
+ .halt_reg = 0x48004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(22),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_bimc_hmss_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
+ .halt_reg = 0x4401c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4401c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_bimc_mss_q6_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_ahb_clk = {
+ .halt_reg = 0x17004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(17),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
+ .halt_reg = 0x19008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x19008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup1_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup1_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
+ .halt_reg = 0x19004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x19004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup1_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup1_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
+ .halt_reg = 0x1b008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1b008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup2_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup2_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
+ .halt_reg = 0x1b004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1b004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup2_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup2_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
+ .halt_reg = 0x1d008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1d008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup3_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup3_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
+ .halt_reg = 0x1d004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1d004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup3_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup3_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
+ .halt_reg = 0x1f008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1f008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup4_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup4_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
+ .halt_reg = 0x1f004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1f004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup4_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup4_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart1_apps_clk = {
+ .halt_reg = 0x1a004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart1_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_uart1_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart2_apps_clk = {
+ .halt_reg = 0x1c004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1c004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart2_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_uart2_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_ahb_clk = {
+ .halt_reg = 0x25004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(15),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
+ .halt_reg = 0x26008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x26008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup1_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup1_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
+ .halt_reg = 0x26004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x26004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup1_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup1_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
+ .halt_reg = 0x28008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup2_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup2_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
+ .halt_reg = 0x28004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup2_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup2_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
+ .halt_reg = 0x2a008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2a008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup3_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup3_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
+ .halt_reg = 0x2a004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup3_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup3_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
+ .halt_reg = 0x2c008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2c008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup4_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup4_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
+ .halt_reg = 0x2c004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2c004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup4_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup4_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_uart1_apps_clk = {
+ .halt_reg = 0x27004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x27004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_uart1_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_uart1_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_uart2_apps_clk = {
+ .halt_reg = 0x29004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x29004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_uart2_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_uart2_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_boot_rom_ahb_clk = {
+ .halt_reg = 0x38004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(10),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_boot_rom_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cfg_noc_usb2_axi_clk = {
+ .halt_reg = 0x5058,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5058,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_cfg_noc_usb2_axi_clk",
+ .parent_names = (const char *[]){
+ "usb20_master_clk_src",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
+ .halt_reg = 0x5018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_cfg_noc_usb3_axi_clk",
+ .parent_names = (const char *[]){
+ "usb30_master_clk_src",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_dcc_ahb_clk = {
+ .halt_reg = 0x84004,
+ .clkr = {
+ .enable_reg = 0x84004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_dcc_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp1_clk = {
+ .halt_reg = 0x64000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x64000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp1_clk",
+ .parent_names = (const char *[]){
+ "gp1_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp2_clk = {
+ .halt_reg = 0x65000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x65000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp2_clk",
+ .parent_names = (const char *[]){
+ "gp2_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp3_clk = {
+ .halt_reg = 0x66000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x66000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp3_clk",
+ .parent_names = (const char *[]){
+ "gp3_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_bimc_gfx_clk = {
+ .halt_reg = 0x71010,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x71010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_bimc_gfx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_cfg_ahb_clk = {
+ .halt_reg = 0x71004,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x71004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_gpll0_clk = {
+ .halt_reg = 0x5200c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_gpll0_clk",
+ .parent_names = (const char *[]){
+ "gpll0",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_gpll0_div_clk = {
+ .halt_reg = 0x5200c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(3),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_gpll0_div_clk",
+ .parent_names = (const char *[]){
+ "gpll0_early_div",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_hmss_dvm_bus_clk = {
+ .halt_reg = 0x4808c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4808c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_hmss_dvm_bus_clk",
+ .ops = &clk_branch2_ops,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ },
+};
+
+static struct clk_branch gcc_hmss_rbcpr_clk = {
+ .halt_reg = 0x48008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x48008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_hmss_rbcpr_clk",
+ .parent_names = (const char *[]){
+ "hmss_rbcpr_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mmss_gpll0_clk = {
+ .halt_reg = 0x5200c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mmss_gpll0_clk",
+ .parent_names = (const char *[]){
+ "gpll0",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mmss_gpll0_div_clk = {
+ .halt_reg = 0x5200c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mmss_gpll0_div_clk",
+ .parent_names = (const char *[]){
+ "gpll0_early_div",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
+ .halt_reg = 0x9004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mmss_noc_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
+ .halt_reg = 0x9000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mmss_sys_noc_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mss_cfg_ahb_clk = {
+ .halt_reg = 0x8a000,
+ .clkr = {
+ .enable_reg = 0x8a000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mss_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
+ .halt_reg = 0x8a004,
+ .clkr = {
+ .enable_reg = 0x8a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mss_mnoc_bimc_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
+ .halt_reg = 0x8a040,
+ .clkr = {
+ .enable_reg = 0x8a040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mss_q6_bimc_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mss_snoc_axi_clk = {
+ .halt_reg = 0x8a03c,
+ .clkr = {
+ .enable_reg = 0x8a03c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mss_snoc_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pdm2_clk = {
+ .halt_reg = 0x3300c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3300c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pdm2_clk",
+ .parent_names = (const char *[]){
+ "pdm2_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pdm_ahb_clk = {
+ .halt_reg = 0x33004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x33004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pdm_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_prng_ahb_clk = {
+ .halt_reg = 0x34004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(13),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_prng_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qspi_ahb_clk = {
+ .halt_reg = 0x4d004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4d004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qspi_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qspi_ser_clk = {
+ .halt_reg = 0x4d008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4d008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qspi_ser_clk",
+ .parent_names = (const char *[]){
+ "qspi_ser_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_rx0_usb2_clkref_clk = {
+ .halt_reg = 0x88018,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x88018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_rx0_usb2_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_rx1_usb2_clkref_clk = {
+ .halt_reg = 0x88014,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x88014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_rx1_usb2_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_ahb_clk = {
+ .halt_reg = 0x16008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x16008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_apps_clk = {
+ .halt_reg = 0x16004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x16004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_apps_clk",
+ .parent_names = (const char *[]){
+ "sdcc1_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_ice_core_clk = {
+ .halt_reg = 0x1600c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1600c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_ice_core_clk",
+ .parent_names = (const char *[]){
+ "sdcc1_ice_core_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc2_ahb_clk = {
+ .halt_reg = 0x14008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x14008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc2_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc2_apps_clk = {
+ .halt_reg = 0x14004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x14004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc2_apps_clk",
+ .parent_names = (const char *[]){
+ "sdcc2_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_ahb_clk = {
+ .halt_reg = 0x7500c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x7500c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_axi_clk = {
+ .halt_reg = 0x75008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x75008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_axi_clk",
+ .parent_names = (const char *[]){
+ "ufs_axi_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_clkref_clk = {
+ .halt_reg = 0x88008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x88008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_ice_core_clk = {
+ .halt_reg = 0x7600c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x7600c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_ice_core_clk",
+ .parent_names = (const char *[]){
+ "ufs_ice_core_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_phy_aux_clk = {
+ .halt_reg = 0x76040,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x76040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_phy_aux_clk",
+ .parent_names = (const char *[]){
+ "ufs_phy_aux_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
+ .halt_reg = 0x75014,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x75014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_rx_symbol_0_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
+ .halt_reg = 0x7605c,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x7605c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_rx_symbol_1_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
+ .halt_reg = 0x75010,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x75010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_tx_symbol_0_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_unipro_core_clk = {
+ .halt_reg = 0x76008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x76008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_unipro_core_clk",
+ .parent_names = (const char *[]){
+ "ufs_unipro_core_clk_src",
+ },
+ .flags = CLK_SET_RATE_PARENT,
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb20_master_clk = {
+ .halt_reg = 0x2f004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2f004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb20_master_clk",
+ .parent_names = (const char *[]){
+ "usb20_master_clk_src"
+ },
+ .flags = CLK_SET_RATE_PARENT,
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb20_mock_utmi_clk = {
+ .halt_reg = 0x2f00c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2f00c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb20_mock_utmi_clk",
+ .parent_names = (const char *[]){
+ "usb20_mock_utmi_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb20_sleep_clk = {
+ .halt_reg = 0x2f008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2f008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb20_sleep_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_master_clk = {
+ .halt_reg = 0xf008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb30_master_clk",
+ .parent_names = (const char *[]){
+ "usb30_master_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_mock_utmi_clk = {
+ .halt_reg = 0xf010,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb30_mock_utmi_clk",
+ .parent_names = (const char *[]){
+ "usb30_mock_utmi_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_sleep_clk = {
+ .halt_reg = 0xf00c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf00c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb30_sleep_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_clkref_clk = {
+ .halt_reg = 0x8800c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x8800c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb3_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_phy_aux_clk = {
+ .halt_reg = 0x50000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x50000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb3_phy_aux_clk",
+ .parent_names = (const char *[]){
+ "usb3_phy_aux_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_phy_pipe_clk = {
+ .halt_reg = 0x50004,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x50004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb3_phy_pipe_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
+ .halt_reg = 0x6a004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb_phy_cfg_ahb2phy_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct gdsc ufs_gdsc = {
+ .gdscr = 0x75004,
+ .gds_hw_ctrl = 0x0,
+ .pd = {
+ .name = "ufs_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc usb_30_gdsc = {
+ .gdscr = 0xf004,
+ .gds_hw_ctrl = 0x0,
+ .pd = {
+ .name = "usb_30_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc pcie_0_gdsc = {
+ .gdscr = 0x6b004,
+ .gds_hw_ctrl = 0x0,
+ .pd = {
+ .name = "pcie_0_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+struct clk_hw *gcc_sdm660_hws[] = {
+ [GCC_XO] = &xo.hw,
+ [GCC_GPLL0_EARLY_DIV] = &gpll0_early_div.hw,
+ [GCC_GPLL1_EARLY_DIV] = &gpll1_early_div.hw,
+};
+
+static struct clk_regmap *gcc_660_clocks[] = {
+ [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
+ [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
+ [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
+ [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
+ [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
+ [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
+ [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
+ [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
+ [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
+ [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
+ [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
+ [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
+ [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
+ [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
+ [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
+ [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,
+ [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,
+ [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
+ [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
+ [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
+ [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
+ [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
+ [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
+ [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
+ [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
+ [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
+ [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
+ [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
+ [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
+ [GCC_CFG_NOC_USB2_AXI_CLK] = &gcc_cfg_noc_usb2_axi_clk.clkr,
+ [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,
+ [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
+ [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
+ [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
+ [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
+ [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
+ [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
+ [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,
+ [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,
+ [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr,
+ [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
+ [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,
+ [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
+ [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
+ [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,
+ [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
+ [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
+ [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
+ [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
+ [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
+ [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
+ [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
+ [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
+ [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
+ [GCC_RX0_USB2_CLKREF_CLK] = &gcc_rx0_usb2_clkref_clk.clkr,
+ [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
+ [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
+ [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
+ [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
+ [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
+ [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
+ [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
+ [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
+ [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
+ [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
+ [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,
+ [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
+ [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
+ [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
+ [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
+ [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
+ [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
+ [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
+ [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
+ [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
+ [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
+ [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
+ [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
+ [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
+ [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
+ [GP1_CLK_SRC] = &gp1_clk_src.clkr,
+ [GP2_CLK_SRC] = &gp2_clk_src.clkr,
+ [GP3_CLK_SRC] = &gp3_clk_src.clkr,
+ [GPLL0] = &gpll0.clkr,
+ [GPLL0_EARLY] = &gpll0_early.clkr,
+ [GPLL1] = &gpll1.clkr,
+ [GPLL1_EARLY] = &gpll1_early.clkr,
+ [GPLL1] = &gpll1.clkr,
+ [GPLL4_EARLY] = &gpll4_early.clkr,
+ [GPLL4] = &gpll4.clkr,
+ [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
+ [HMSS_GPLL4_CLK_SRC] = &hmss_gpll4_clk_src.clkr,
+ [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
+ [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
+ [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
+ [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
+ [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
+ [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
+ [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
+ [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
+ [UFS_PHY_AUX_CLK_SRC] = &ufs_phy_aux_clk_src.clkr,
+ [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr,
+ [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
+ [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
+ [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
+ [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
+ [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
+};
+
+static struct gdsc *gcc_660_gdscs[] = {
+ [UFS_GDSC] = &ufs_gdsc,
+ [USB_30_GDSC] = &usb_30_gdsc,
+ [PCIE_0_GDSC] = &pcie_0_gdsc,
+};
+
+static const struct qcom_reset_map gcc_660_resets[] = {
+ [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
+ [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
+ [GCC_UFS_BCR] = { 0x75000 },
+ [GCC_USB3_DP_PHY_BCR] = { 0x50028 },
+ [GCC_USB3_PHY_BCR] = { 0x50020 },
+ [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
+ [GCC_USB_20_BCR] = { 0x2f000 },
+ [GCC_USB_30_BCR] = { 0xf000 },
+ [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
+};
+
+static const struct regmap_config gcc_660_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x94000,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc gcc_660_desc = {
+ .config = &gcc_660_regmap_config,
+ .clks = gcc_660_clocks,
+ .num_clks = ARRAY_SIZE(gcc_660_clocks),
+ .resets = gcc_660_resets,
+ .num_resets = ARRAY_SIZE(gcc_660_resets),
+ .gdscs = gcc_660_gdscs,
+ .num_gdscs = ARRAY_SIZE(gcc_660_gdscs),
+};
+
+static const struct of_device_id gcc_660_match_table[] = {
+ { .compatible = "qcom,gcc-sdm660" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, gcc_660_match_table);
+
+static int gcc_660_probe(struct platform_device *pdev)
+{
+ int i, ret = 0;
+ struct regmap *regmap;
+
+ regmap = qcom_cc_map(pdev, &gcc_660_desc);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ /*
+ * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
+ * turned off by hardware during certain apps low power modes.
+ */
+ ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
+ if (ret)
+ return ret;
+
+ /* Register the hws */
+ for (i = 0; i < ARRAY_SIZE(gcc_sdm660_hws); i++) {
+ ret = devm_clk_hw_register(&pdev->dev, gcc_sdm660_hws[i]);
+ if (ret)
+ return ret;
+ }
+
+ return qcom_cc_really_probe(pdev, &gcc_660_desc, regmap);
+}
+
+static struct platform_driver gcc_660_driver = {
+ .probe = gcc_660_probe,
+ .driver = {
+ .name = "gcc-sdm660",
+ .of_match_table = gcc_660_match_table,
+ },
+};
+
+static int __init gcc_660_init(void)
+{
+ return platform_driver_register(&gcc_660_driver);
+}
+core_initcall_sync(gcc_660_init);
+
+static void __exit gcc_660_exit(void)
+{
+ platform_driver_unregister(&gcc_660_driver);
+}
+module_exit(gcc_660_exit);
+
+MODULE_DESCRIPTION("QCOM GCC sdm660 Driver");
diff --git a/include/dt-bindings/clock/qcom,gcc-sdm660.h b/include/dt-bindings/clock/qcom,gcc-sdm660.h
new file mode 100644
index 000000000000..76aabcc5e7e3
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sdm660.h
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018, Craig Tatlor.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H
+#define _DT_BINDINGS_CLK_MSM_GCC_660_H
+
+#define GCC_XO 0
+#define GCC_GPLL0_EARLY_DIV 1
+#define GCC_GPLL1_EARLY_DIV 2
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 3
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 4
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 5
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 6
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 7
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 8
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC 9
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC 10
+#define BLSP1_UART1_APPS_CLK_SRC 11
+#define BLSP1_UART2_APPS_CLK_SRC 12
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC 13
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC 14
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC 15
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC 16
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC 17
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC 18
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC 19
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC 20
+#define BLSP2_UART1_APPS_CLK_SRC 21
+#define BLSP2_UART2_APPS_CLK_SRC 22
+#define GCC_AGGRE2_UFS_AXI_CLK 23
+#define GCC_AGGRE2_USB3_AXI_CLK 24
+#define GCC_BIMC_GFX_CLK 25
+#define GCC_BIMC_HMSS_AXI_CLK 26
+#define GCC_BIMC_MSS_Q6_AXI_CLK 27
+#define GCC_BLSP1_AHB_CLK 28
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 29
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 30
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 31
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 32
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 33
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 34
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 35
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 36
+#define GCC_BLSP1_UART1_APPS_CLK 37
+#define GCC_BLSP1_UART2_APPS_CLK 38
+#define GCC_BLSP2_AHB_CLK 39
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK 40
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK 41
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK 42
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK 43
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK 44
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK 46
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK 45
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK 46
+#define GCC_BLSP2_UART1_APPS_CLK 47
+#define GCC_BLSP2_UART2_APPS_CLK 48
+#define GCC_BOOT_ROM_AHB_CLK 49
+#define GCC_CFG_NOC_USB2_AXI_CLK 50
+#define GCC_CFG_NOC_USB3_AXI_CLK 51
+#define GCC_DCC_AHB_CLK 52
+#define GCC_GP1_CLK 53
+#define GCC_GP2_CLK 54
+#define GCC_GP3_CLK 55
+#define GCC_GPU_BIMC_GFX_CLK 56
+#define GCC_GPU_CFG_AHB_CLK 57
+#define GCC_GPU_GPLL0_CLK 58
+#define GCC_GPU_GPLL0_DIV_CLK 59
+#define GCC_HMSS_DVM_BUS_CLK 60
+#define GCC_HMSS_RBCPR_CLK 61
+#define GCC_MMSS_GPLL0_CLK 62
+#define GCC_MMSS_GPLL0_DIV_CLK 63
+#define GCC_MMSS_NOC_CFG_AHB_CLK 64
+#define GCC_MMSS_SYS_NOC_AXI_CLK 65
+#define GCC_MSS_CFG_AHB_CLK 66
+#define GCC_MSS_GPLL0_DIV_CLK 67
+#define GCC_MSS_MNOC_BIMC_AXI_CLK 68
+#define GCC_MSS_Q6_BIMC_AXI_CLK 69
+#define GCC_MSS_SNOC_AXI_CLK 70
+#define GCC_PDM2_CLK 71
+#define GCC_PDM_AHB_CLK 72
+#define GCC_PRNG_AHB_CLK 73
+#define GCC_QSPI_AHB_CLK 74
+#define GCC_QSPI_SER_CLK 75
+#define GCC_SDCC1_AHB_CLK 76
+#define GCC_SDCC1_APPS_CLK 77
+#define GCC_SDCC1_ICE_CORE_CLK 78
+#define GCC_SDCC2_AHB_CLK 79
+#define GCC_SDCC2_APPS_CLK 80
+#define GCC_UFS_AHB_CLK 81
+#define GCC_UFS_AXI_CLK 82
+#define GCC_UFS_CLKREF_CLK 83
+#define GCC_UFS_ICE_CORE_CLK 84
+#define GCC_UFS_PHY_AUX_CLK 85
+#define GCC_UFS_RX_SYMBOL_0_CLK 86
+#define GCC_UFS_RX_SYMBOL_1_CLK 87
+#define GCC_UFS_TX_SYMBOL_0_CLK 88
+#define GCC_UFS_UNIPRO_CORE_CLK 89
+#define GCC_USB20_MASTER_CLK 90
+#define GCC_USB20_MOCK_UTMI_CLK 91
+#define GCC_USB20_SLEEP_CLK 92
+#define GCC_USB30_MASTER_CLK 93
+#define GCC_USB30_MOCK_UTMI_CLK 94
+#define GCC_USB30_SLEEP_CLK 95
+#define GCC_USB3_CLKREF_CLK 96
+#define GCC_USB3_PHY_AUX_CLK 97
+#define GCC_USB3_PHY_PIPE_CLK 98
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK 99
+#define GP1_CLK_SRC 100
+#define GP2_CLK_SRC 101
+#define GP3_CLK_SRC 102
+#define GPLL0 103
+#define GPLL0_EARLY 104
+#define GPLL1 105
+#define GPLL1_EARLY 106
+#define GPLL4 107
+#define GPLL4_EARLY 108
+#define HMSS_GPLL0_CLK_SRC 109
+#define HMSS_GPLL4_CLK_SRC 110
+#define HMSS_RBCPR_CLK_SRC 111
+#define PDM2_CLK_SRC 112
+#define QSPI_SER_CLK_SRC 113
+#define SDCC1_APPS_CLK_SRC 114
+#define SDCC1_ICE_CORE_CLK_SRC 115
+#define SDCC2_APPS_CLK_SRC 116
+#define UFS_AXI_CLK_SRC 117
+#define UFS_ICE_CORE_CLK_SRC 118
+#define UFS_PHY_AUX_CLK_SRC 119
+#define UFS_UNIPRO_CORE_CLK_SRC 120
+#define USB20_MASTER_CLK_SRC 121
+#define USB20_MOCK_UTMI_CLK_SRC 122
+#define USB30_MASTER_CLK_SRC 123
+#define USB30_MOCK_UTMI_CLK_SRC 124
+#define USB3_PHY_AUX_CLK_SRC 125
+#define GPLL0_OUT_MSSCC 126
+#define GCC_UFS_AXI_HW_CTL_CLK 127
+#define GCC_UFS_ICE_CORE_HW_CTL_CLK 128
+#define GCC_UFS_PHY_AUX_HW_CTL_CLK 129
+#define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 130
+#define GCC_RX0_USB2_CLKREF_CLK 131
+#define GCC_RX1_USB2_CLKREF_CLK 132
+
+#define PCIE_0_GDSC 0
+#define UFS_GDSC 1
+#define USB_30_GDSC 2
+
+#define GCC_QUSB2PHY_PRIM_BCR 0
+#define GCC_QUSB2PHY_SEC_BCR 1
+#define GCC_UFS_BCR 2
+#define GCC_USB3_DP_PHY_BCR 3
+#define GCC_USB3_PHY_BCR 4
+#define GCC_USB3PHY_PHY_BCR 5
+#define GCC_USB_20_BCR 6
+#define GCC_USB_30_BCR 7
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR 8
+
+#endif
--
2.18.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH] clk: qcom: Add Global Clock controller (GCC) driver for SDM660
2018-08-10 20:21 ` [PATCH] clk: qcom: Add Global Clock controller (GCC) driver for SDM660 Craig Tatlor
@ 2018-08-11 21:30 ` kbuild test robot
2018-08-11 21:30 ` [RFC PATCH] clk: qcom: gcc_sdm660_hws[] can be static kbuild test robot
` (3 subsequent siblings)
4 siblings, 0 replies; 18+ messages in thread
From: kbuild test robot @ 2018-08-11 21:30 UTC (permalink / raw)
To: Craig Tatlor
Cc: kbuild-all, ctatlor97, linux-arm-msm, Michael Turquette,
Stephen Boyd, Rob Herring, Mark Rutland, Andy Gross, David Brown,
linux-clk, devicetree, linux-kernel, linux-soc
Hi Craig,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on agross/for-next]
[also build test WARNING on v4.18-rc8]
[cannot apply to next-20180810]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Craig-Tatlor/clk-qcom-Add-Global-Clock-controller-GCC-driver-for-SDM660/20180811-150111
base: https://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git for-next
reproduce:
# apt-get install sparse
make ARCH=x86_64 allmodconfig
make C=1 CF=-D__CHECK_ENDIAN__
sparse warnings: (new ones prefixed by >>)
>> drivers/clk/qcom/gcc-sdm660.c:2255:15: sparse: symbol 'gcc_sdm660_hws' was not declared. Should it be static?
drivers/clk/qcom/gcc-sdm660.c:2304:10: sparse: Initializer entry defined twice
drivers/clk/qcom/gcc-sdm660.c:2306:10: also defined here
Please review and possibly fold the followup patch.
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
^ permalink raw reply [flat|nested] 18+ messages in thread
* [RFC PATCH] clk: qcom: gcc_sdm660_hws[] can be static
2018-08-10 20:21 ` [PATCH] clk: qcom: Add Global Clock controller (GCC) driver for SDM660 Craig Tatlor
2018-08-11 21:30 ` kbuild test robot
@ 2018-08-11 21:30 ` kbuild test robot
2018-08-13 6:55 ` [PATCH] clk: qcom: Add Global Clock controller (GCC) driver for SDM660 Taniya Das
` (2 subsequent siblings)
4 siblings, 0 replies; 18+ messages in thread
From: kbuild test robot @ 2018-08-11 21:30 UTC (permalink / raw)
To: Craig Tatlor
Cc: kbuild-all, ctatlor97, linux-arm-msm, Michael Turquette,
Stephen Boyd, Rob Herring, Mark Rutland, Andy Gross, David Brown,
linux-clk, devicetree, linux-kernel, linux-soc
Fixes: 851e534f5d75 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM660")
Signed-off-by: kbuild test robot <fengguang.wu@intel.com>
---
gcc-sdm660.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
index bdb445a..cec8b41 100644
--- a/drivers/clk/qcom/gcc-sdm660.c
+++ b/drivers/clk/qcom/gcc-sdm660.c
@@ -2252,7 +2252,7 @@ static struct gdsc pcie_0_gdsc = {
.flags = VOTABLE,
};
-struct clk_hw *gcc_sdm660_hws[] = {
+static struct clk_hw *gcc_sdm660_hws[] = {
[GCC_XO] = &xo.hw,
[GCC_GPLL0_EARLY_DIV] = &gpll0_early_div.hw,
[GCC_GPLL1_EARLY_DIV] = &gpll1_early_div.hw,
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH] clk: qcom: Add Global Clock controller (GCC) driver for SDM660
2018-08-10 20:21 ` [PATCH] clk: qcom: Add Global Clock controller (GCC) driver for SDM660 Craig Tatlor
2018-08-11 21:30 ` kbuild test robot
2018-08-11 21:30 ` [RFC PATCH] clk: qcom: gcc_sdm660_hws[] can be static kbuild test robot
@ 2018-08-13 6:55 ` Taniya Das
2018-08-13 7:45 ` Craig Tatlor
2018-08-13 9:44 ` Craig Tatlor
2018-09-25 16:35 ` [PATCH v2] " Craig Tatlor
2018-09-25 17:35 ` [PATCH v3] " Craig Tatlor
4 siblings, 2 replies; 18+ messages in thread
From: Taniya Das @ 2018-08-13 6:55 UTC (permalink / raw)
To: Craig Tatlor
Cc: linux-arm-msm, Michael Turquette, Stephen Boyd, Rob Herring,
Mark Rutland, Andy Gross, David Brown, linux-clk, devicetree,
linux-kernel, linux-soc
Hello Craig,
Could you please correct the authorship and also provide the reference
to code where this is picked from?
On 8/11/2018 1:51 AM, Craig Tatlor wrote:
> Add support for the global clock controller found on SDM660
> based devices. This should allow most non-multimedia device
> drivers to probe and control their clocks.
> Based on CAF implementation.
>
> Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
> ---
> .../devicetree/bindings/clock/qcom,gcc.txt | 1 +
> drivers/clk/qcom/Kconfig | 9 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/gcc-sdm660.c | 2479 +++++++++++++++++
> include/dt-bindings/clock/qcom,gcc-sdm660.h | 159 ++
> 5 files changed, 2649 insertions(+)
> create mode 100644 drivers/clk/qcom/gcc-sdm660.c
> create mode 100644 include/dt-bindings/clock/qcom,gcc-sdm660.h
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
> index 664ea1fd6c76..e498ad2e8db8 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
> @@ -19,6 +19,7 @@ Required properties :
> "qcom,gcc-msm8996"
> "qcom,gcc-msm8998"
> "qcom,gcc-mdm9615"
> + "qcom,gcc-sdm660"
> "qcom,gcc-sdm845"
>
> - reg : shall contain base register location and length
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 9c3480dcc38a..c4bda6d24c1f 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -226,6 +226,15 @@ config MSM_GCC_8998
> Say Y if you want to use peripheral devices such as UART, SPI,
> i2c, USB, UFS, SD/eMMC, PCIe, etc.
>
> +config SDM_GCC_660
> + tristate "SDM660 Global Clock Controller"
> + select QCOM_GDSC
> + depends on COMMON_CLK_QCOM
> + help
> + Support for the global clock controller on SDM660 devices.
> + Say Y if you want to use peripheral devices such as UART, SPI,
> + i2C, USB, UFS, SDDC, PCIe, etc.
> +
> config SDM_GCC_845
> tristate "SDM845 Global Clock Controller"
> select QCOM_GDSC
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 762c01137c2f..6e37d30d7c02 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -38,6 +38,7 @@ obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o
> obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o
> obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
> obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
> +obj-$(CONFIG_SDM_GCC_660) += gcc-sdm660.o
> obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
> obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
> obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
> diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
> new file mode 100644
> index 000000000000..bdb445aa4baa
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-sdm660.c
> @@ -0,0 +1,2479 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2018, Craig Tatlor.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/bitops.h>
> +#include <linux/err.h>
> +#include <linux/platform_device.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/clk-provider.h>
> +#include <linux/regmap.h>
> +#include <linux/reset-controller.h>
> +
> +#include <dt-bindings/clock/qcom,gcc-sdm660.h>
> +
> +#include "common.h"
> +#include "clk-regmap.h"
> +#include "clk-alpha-pll.h"
> +#include "clk-rcg.h"
> +#include "clk-branch.h"
> +#include "reset.h"
> +#include "gdsc.h"
> +
> +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
> +
> +enum {
> + P_XO,
> + P_SLEEP_CLK,
> + P_GPLL0,
> + P_GPLL1,
> + P_GPLL4,
> + P_GPLL0_EARLY_DIV,
> + P_GPLL1_EARLY_DIV,
> +};
> +
> +static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div[] = {
> + { P_XO, 0 },
> + { P_GPLL0, 1 },
> + { P_GPLL0_EARLY_DIV, 6 },
> +};
> +
> +static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div[] = {
> + "xo",
> + "gpll0",
> + "gpll0_early_div",
> +};
> +
> +static const struct parent_map gcc_parent_map_xo_gpll0[] = {
> + { P_XO, 0 },
> + { P_GPLL0, 1 },
> +};
> +
> +static const char * const gcc_parent_names_xo_gpll0[] = {
> + "xo",
> + "gpll0",
> +};
> +
> +static const struct parent_map gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] = {
> + { P_XO, 0 },
> + { P_GPLL0, 1 },
> + { P_SLEEP_CLK, 5 },
> + { P_GPLL0_EARLY_DIV, 6 },
> +};
> +
> +static const char * const gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div[] = {
> + "xo",
> + "gpll0",
> + "sleep_clk",
> + "gpll0_early_div",
> +};
> +
> +static const struct parent_map gcc_parent_map_xo_sleep_clk[] = {
> + { P_XO, 0 },
> + { P_SLEEP_CLK, 5 },
> +};
> +
> +static const char * const gcc_parent_names_xo_sleep_clk[] = {
> + "xo",
> + "sleep_clk",
> +};
> +
> +static const struct parent_map gcc_parent_map_xo_gpll4[] = {
> + { P_XO, 0 },
> + { P_GPLL4, 5 },
> +};
> +
> +static const char * const gcc_parent_names_xo_gpll4[] = {
> + "xo",
> + "gpll4",
> +};
> +
> +static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
> + { P_XO, 0 },
> + { P_GPLL0, 1 },
> + { P_GPLL0_EARLY_DIV, 3 },
> + { P_GPLL1, 4 },
> + { P_GPLL4, 5 },
> + { P_GPLL1_EARLY_DIV, 6 },
> +};
> +
> +static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
> + "xo",
> + "gpll0",
> + "gpll0_early_div",
> + "gpll1",
> + "gpll4",
> + "gpll1_early_div",
> +};
> +
> +static const struct parent_map gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] = {
> + { P_XO, 0 },
> + { P_GPLL0, 1 },
> + { P_GPLL4, 5 },
> + { P_GPLL0_EARLY_DIV, 6 },
> +};
> +
> +static const char * const gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div[] = {
> + "xo",
> + "gpll0",
> + "gpll4",
> + "gpll0_early_div",
> +};
> +
> +static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] = {
> + { P_XO, 0 },
> + { P_GPLL0, 1 },
> + { P_GPLL0_EARLY_DIV, 2 },
> + { P_GPLL4, 5 },
> +};
> +
> +static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4[] = {
> + "xo",
> + "gpll0",
> + "gpll0_early_div",
> + "gpll4",
> +};
> +
> +static struct clk_fixed_factor xo = {
> + .mult = 1,
> + .div = 1,
> + .hw.init = &(struct clk_init_data){
> + .name = "xo",
> + .parent_names = (const char *[]){ "xo_board" },
> + .num_parents = 1,
> + .ops = &clk_fixed_factor_ops,
> + },
> +};
> +
> +static struct clk_alpha_pll gpll0_early = {
> + .offset = 0x0,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .clkr = {
> + .enable_reg = 0x52000,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpll0_early",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_ops,
> + },
> + },
> +};
> +
> +static struct clk_fixed_factor gpll0_early_div = {
> + .mult = 1,
> + .div = 2,
> + .hw.init = &(struct clk_init_data){
> + .name = "gpll0_early_div",
> + .parent_names = (const char *[]){ "gpll0_early" },
> + .num_parents = 1,
> + .ops = &clk_fixed_factor_ops,
> + },
> +};
> +
> +static struct clk_alpha_pll_postdiv gpll0 = {
> + .offset = 0x00000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gpll0",
> + .parent_names = (const char *[]){ "gpll0_early" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_postdiv_ops,
> + },
> +};
> +
> +static struct clk_alpha_pll gpll1_early = {
> + .offset = 0x1000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .clkr = {
> + .enable_reg = 0x52000,
> + .enable_mask = BIT(1),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpll1_early",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_ops,
> + },
> + },
> +};
> +
> +static struct clk_fixed_factor gpll1_early_div = {
> + .mult = 1,
> + .div = 2,
> + .hw.init = &(struct clk_init_data){
> + .name = "gpll1_early_div",
> + .parent_names = (const char *[]){ "gpll1_early" },
> + .num_parents = 1,
> + .ops = &clk_fixed_factor_ops,
> + },
> +};
> +
> +static struct clk_alpha_pll_postdiv gpll1 = {
> + .offset = 0x1000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gpll1",
> + .parent_names = (const char *[]){ "gpll1_early" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_postdiv_ops,
> + },
> +};
> +
> +static struct clk_alpha_pll gpll4_early = {
> + .offset = 0x77000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .clkr = {
> + .enable_reg = 0x52000,
> + .enable_mask = BIT(4),
> + .hw.init = &(struct clk_init_data){
> + .name = "gpll4_early",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_ops,
> + },
> + },
> +};
> +
> +static struct clk_alpha_pll_postdiv gpll4 = {
> + .offset = 0x77000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> + .clkr.hw.init = &(struct clk_init_data)
> + {
> + .name = "gpll4",
> + .parent_names = (const char *[]) { "gpll4_early" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_postdiv_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + F(50000000, P_GPLL0, 12, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x19020,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp1_qup1_i2c_apps_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
> + F(960000, P_XO, 10, 1, 2),
> + F(4800000, P_XO, 4, 0, 0),
> + F(9600000, P_XO, 2, 0, 0),
> + F(15000000, P_GPLL0, 10, 1, 4),
> + F(19200000, P_XO, 1, 0, 0),
> + F(25000000, P_GPLL0, 12, 1, 2),
> + F(50000000, P_GPLL0, 12, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
> + .cmd_rcgr = 0x1900c,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp1_qup1_spi_apps_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x1b020,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp1_qup2_i2c_apps_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
> + .cmd_rcgr = 0x1b00c,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp1_qup2_spi_apps_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x1d020,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp1_qup3_i2c_apps_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
> + .cmd_rcgr = 0x1d00c,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp1_qup3_spi_apps_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x1f020,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp1_qup4_i2c_apps_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
> + .cmd_rcgr = 0x1f00c,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp1_qup4_spi_apps_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
> + F(3686400, P_GPLL0, 1, 96, 15625),
> + F(7372800, P_GPLL0, 1, 192, 15625),
> + F(14745600, P_GPLL0, 1, 384, 15625),
> + F(16000000, P_GPLL0, 5, 2, 15),
> + F(19200000, P_XO, 1, 0, 0),
> + F(24000000, P_GPLL0, 5, 1, 5),
> + F(32000000, P_GPLL0, 1, 4, 75),
> + F(40000000, P_GPLL0, 15, 0, 0),
> + F(46400000, P_GPLL0, 1, 29, 375),
> + F(48000000, P_GPLL0, 12.5, 0, 0),
> + F(51200000, P_GPLL0, 1, 32, 375),
> + F(56000000, P_GPLL0, 1, 7, 75),
> + F(58982400, P_GPLL0, 1, 1536, 15625),
> + F(60000000, P_GPLL0, 10, 0, 0),
> + F(63157895, P_GPLL0, 9.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
> + .cmd_rcgr = 0x1a00c,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp1_uart1_apps_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
> + .cmd_rcgr = 0x1c00c,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp1_uart2_apps_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x26020,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp2_qup1_i2c_apps_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
> + .cmd_rcgr = 0x2600c,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp2_qup1_spi_apps_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x28020,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp2_qup2_i2c_apps_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
> + .cmd_rcgr = 0x2800c,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp2_qup2_spi_apps_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x2a020,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp2_qup3_i2c_apps_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
> + .cmd_rcgr = 0x2a00c,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp2_qup3_spi_apps_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
> + .cmd_rcgr = 0x2c020,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp2_qup4_i2c_apps_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
> + .cmd_rcgr = 0x2c00c,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp2_qup4_spi_apps_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
> + .cmd_rcgr = 0x2700c,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp2_uart1_apps_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
> + .cmd_rcgr = 0x2900c,
> + .mnd_width = 16,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "blsp2_uart2_apps_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gp1_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + F(100000000, P_GPLL0, 6, 0, 0),
> + F(200000000, P_GPLL0, 3, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 gp1_clk_src = {
> + .cmd_rcgr = 0x64004,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
> + .freq_tbl = ftbl_gp1_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gp1_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
> + .num_parents = 4,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gp2_clk_src = {
> + .cmd_rcgr = 0x65004,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
> + .freq_tbl = ftbl_gp1_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gp2_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
> + .num_parents = 4,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 gp3_clk_src = {
> + .cmd_rcgr = 0x66004,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
> + .freq_tbl = ftbl_gp1_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gp3_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
> + .num_parents = 4,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] = {
> + F(300000000, P_GPLL0, 2, 0, 0),
> + F(600000000, P_GPLL0, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 hmss_gpll0_clk_src = {
> + .cmd_rcgr = 0x4805c,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_hmss_gpll0_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "hmss_gpll0_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_hmss_gpll4_clk_src[] = {
> + F(384000000, P_GPLL4, 4, 0, 0),
> + F(768000000, P_GPLL4, 2, 0, 0),
> + F(1536000000, P_GPLL4, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 hmss_gpll4_clk_src = {
> + .cmd_rcgr = 0x48074,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll4,
> + .freq_tbl = ftbl_hmss_gpll4_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "hmss_gpll4_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll4,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 hmss_rbcpr_clk_src = {
> + .cmd_rcgr = 0x48044,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_hmss_rbcpr_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "hmss_rbcpr_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_pdm2_clk_src[] = {
> + F(60000000, P_GPLL0, 10, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 pdm2_clk_src = {
> + .cmd_rcgr = 0x33010,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_pdm2_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "pdm2_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + F(80200000, P_GPLL1_EARLY_DIV, 5, 0, 0),
> + F(160400000, P_GPLL1, 5, 0, 0),
> + F(267333333, P_GPLL1, 3, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 qspi_ser_clk_src = {
> + .cmd_rcgr = 0x4d00c,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
> + .freq_tbl = ftbl_qspi_ser_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "qspi_ser_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
> + .num_parents = 6,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
> + F(144000, P_XO, 16, 3, 25),
> + F(400000, P_XO, 12, 1, 4),
> + F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
> + F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
> + F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
> + F(100000000, P_GPLL0, 6, 0, 0),
> + F(192000000, P_GPLL4, 8, 0, 0),
> + F(384000000, P_GPLL4, 4, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 sdcc1_apps_clk_src = {
> + .cmd_rcgr = 0x1602c,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div,
> + .freq_tbl = ftbl_sdcc1_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "sdcc1_apps_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div,
> + .num_parents = 4,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
> + F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
> + F(150000000, P_GPLL0, 4, 0, 0),
> + F(200000000, P_GPLL0, 3, 0, 0),
> + F(300000000, P_GPLL0, 2, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 sdcc1_ice_core_clk_src = {
> + .cmd_rcgr = 0x16010,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "sdcc1_ice_core_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
> + F(144000, P_XO, 16, 3, 25),
> + F(400000, P_XO, 12, 1, 4),
> + F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
> + F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
> + F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
> + F(100000000, P_GPLL0, 6, 0, 0),
> + F(192000000, P_GPLL4, 8, 0, 0),
> + F(200000000, P_GPLL0, 3, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 sdcc2_apps_clk_src = {
> + .cmd_rcgr = 0x14010,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4,
> + .freq_tbl = ftbl_sdcc2_apps_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "sdcc2_apps_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4,
> + .num_parents = 4,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
> + F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
> + F(100000000, P_GPLL0, 6, 0, 0),
> + F(150000000, P_GPLL0, 4, 0, 0),
> + F(200000000, P_GPLL0, 3, 0, 0),
> + F(240000000, P_GPLL0, 2.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 ufs_axi_clk_src = {
> + .cmd_rcgr = 0x75018,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_ufs_axi_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "ufs_axi_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
> + F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
> + F(150000000, P_GPLL0, 4, 0, 0),
> + F(300000000, P_GPLL0, 2, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 ufs_ice_core_clk_src = {
> + .cmd_rcgr = 0x76010,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_ufs_ice_core_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "ufs_ice_core_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_rcg2 ufs_phy_aux_clk_src = {
> + .cmd_rcgr = 0x76044,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_sleep_clk,
> + .freq_tbl = ftbl_hmss_rbcpr_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "ufs_phy_aux_clk_src",
> + .parent_names = gcc_parent_names_xo_sleep_clk,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = {
> + F(37500000, P_GPLL0_EARLY_DIV, 8, 0, 0),
> + F(75000000, P_GPLL0, 8, 0, 0),
> + F(150000000, P_GPLL0, 4, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 ufs_unipro_core_clk_src = {
> + .cmd_rcgr = 0x76028,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_ufs_unipro_core_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "ufs_unipro_core_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + F(60000000, P_GPLL0, 10, 0, 0),
> + F(120000000, P_GPLL0, 5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 usb20_master_clk_src = {
> + .cmd_rcgr = 0x2f010,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_usb20_master_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "usb20_master_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_usb20_mock_utmi_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + F(60000000, P_GPLL0, 10, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 usb20_mock_utmi_clk_src = {
> + .cmd_rcgr = 0x2f024,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_usb20_mock_utmi_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "usb20_mock_utmi_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + F(66666667, P_GPLL0_EARLY_DIV, 4.5, 0, 0),
> + F(120000000, P_GPLL0, 5, 0, 0),
> + F(133333333, P_GPLL0, 4.5, 0, 0),
> + F(150000000, P_GPLL0, 4, 0, 0),
> + F(200000000, P_GPLL0, 3, 0, 0),
> + F(240000000, P_GPLL0, 2.5, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 usb30_master_clk_src = {
> + .cmd_rcgr = 0xf014,
> + .mnd_width = 8,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_usb30_master_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "usb30_master_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
> + F(19200000, P_XO, 1, 0, 0),
> + F(40000000, P_GPLL0_EARLY_DIV, 7.5, 0, 0),
> + F(60000000, P_GPLL0, 10, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 usb30_mock_utmi_clk_src = {
> + .cmd_rcgr = 0xf028,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
> + .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "usb30_mock_utmi_clk_src",
> + .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
> + .num_parents = 3,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
> + F(1200000, P_XO, 16, 0, 0),
> + F(19200000, P_XO, 1, 0, 0),
> + { }
> +};
> +
> +static struct clk_rcg2 usb3_phy_aux_clk_src = {
> + .cmd_rcgr = 0x5000c,
> + .mnd_width = 0,
> + .hid_width = 5,
> + .parent_map = gcc_parent_map_xo_sleep_clk,
> + .freq_tbl = ftbl_usb3_phy_aux_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "usb3_phy_aux_clk_src",
> + .parent_names = gcc_parent_names_xo_sleep_clk,
> + .num_parents = 2,
> + .ops = &clk_rcg2_ops,
> + },
> +};
> +
> +static struct clk_branch gcc_aggre2_ufs_axi_clk = {
> + .halt_reg = 0x75034,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x75034,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_aggre2_ufs_axi_clk",
> + .parent_names = (const char *[]){
> + "ufs_axi_clk_src",
> + },
> + .num_parents = 1,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_aggre2_usb3_axi_clk = {
> + .halt_reg = 0xf03c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0xf03c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_aggre2_usb3_axi_clk",
> + .parent_names = (const char *[]){
> + "usb30_master_clk_src",
> + },
> + .num_parents = 1,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_bimc_gfx_clk = {
> + .halt_reg = 0x7106c,
> + .halt_check = BRANCH_VOTED,
> + .clkr = {
> + .enable_reg = 0x7106c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_bimc_gfx_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_bimc_hmss_axi_clk = {
> + .halt_reg = 0x48004,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x52004,
> + .enable_mask = BIT(22),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_bimc_hmss_axi_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
> + .halt_reg = 0x4401c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x4401c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_bimc_mss_q6_axi_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_ahb_clk = {
> + .halt_reg = 0x17004,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x52004,
> + .enable_mask = BIT(17),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_blsp1_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
> + .halt_reg = 0x19008,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x19008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_blsp1_qup1_i2c_apps_clk",
> + .parent_names = (const char *[]){
> + "blsp1_qup1_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
> + .halt_reg = 0x19004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x19004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_blsp1_qup1_spi_apps_clk",
> + .parent_names = (const char *[]){
> + "blsp1_qup1_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
> + .halt_reg = 0x1b008,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x1b008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_blsp1_qup2_i2c_apps_clk",
> + .parent_names = (const char *[]){
> + "blsp1_qup2_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
> + .halt_reg = 0x1b004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x1b004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_blsp1_qup2_spi_apps_clk",
> + .parent_names = (const char *[]){
> + "blsp1_qup2_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
> + .halt_reg = 0x1d008,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x1d008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_blsp1_qup3_i2c_apps_clk",
> + .parent_names = (const char *[]){
> + "blsp1_qup3_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
> + .halt_reg = 0x1d004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x1d004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_blsp1_qup3_spi_apps_clk",
> + .parent_names = (const char *[]){
> + "blsp1_qup3_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
> + .halt_reg = 0x1f008,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x1f008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_blsp1_qup4_i2c_apps_clk",
> + .parent_names = (const char *[]){
> + "blsp1_qup4_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
> + .halt_reg = 0x1f004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x1f004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_blsp1_qup4_spi_apps_clk",
> + .parent_names = (const char *[]){
> + "blsp1_qup4_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_uart1_apps_clk = {
> + .halt_reg = 0x1a004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x1a004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_blsp1_uart1_apps_clk",
> + .parent_names = (const char *[]){
> + "blsp1_uart1_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp1_uart2_apps_clk = {
> + .halt_reg = 0x1c004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x1c004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_blsp1_uart2_apps_clk",
> + .parent_names = (const char *[]){
> + "blsp1_uart2_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_ahb_clk = {
> + .halt_reg = 0x25004,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x52004,
> + .enable_mask = BIT(15),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_blsp2_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
> + .halt_reg = 0x26008,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x26008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_blsp2_qup1_i2c_apps_clk",
> + .parent_names = (const char *[]){
> + "blsp2_qup1_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
> + .halt_reg = 0x26004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x26004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_blsp2_qup1_spi_apps_clk",
> + .parent_names = (const char *[]){
> + "blsp2_qup1_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
> + .halt_reg = 0x28008,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x28008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_blsp2_qup2_i2c_apps_clk",
> + .parent_names = (const char *[]){
> + "blsp2_qup2_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
> + .halt_reg = 0x28004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x28004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_blsp2_qup2_spi_apps_clk",
> + .parent_names = (const char *[]){
> + "blsp2_qup2_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
> + .halt_reg = 0x2a008,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2a008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_blsp2_qup3_i2c_apps_clk",
> + .parent_names = (const char *[]){
> + "blsp2_qup3_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
> + .halt_reg = 0x2a004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2a004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_blsp2_qup3_spi_apps_clk",
> + .parent_names = (const char *[]){
> + "blsp2_qup3_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
> + .halt_reg = 0x2c008,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2c008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_blsp2_qup4_i2c_apps_clk",
> + .parent_names = (const char *[]){
> + "blsp2_qup4_i2c_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
> + .halt_reg = 0x2c004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2c004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_blsp2_qup4_spi_apps_clk",
> + .parent_names = (const char *[]){
> + "blsp2_qup4_spi_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_uart1_apps_clk = {
> + .halt_reg = 0x27004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x27004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_blsp2_uart1_apps_clk",
> + .parent_names = (const char *[]){
> + "blsp2_uart1_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_blsp2_uart2_apps_clk = {
> + .halt_reg = 0x29004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x29004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_blsp2_uart2_apps_clk",
> + .parent_names = (const char *[]){
> + "blsp2_uart2_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_boot_rom_ahb_clk = {
> + .halt_reg = 0x38004,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x52004,
> + .enable_mask = BIT(10),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_boot_rom_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_cfg_noc_usb2_axi_clk = {
> + .halt_reg = 0x5058,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x5058,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_cfg_noc_usb2_axi_clk",
> + .parent_names = (const char *[]){
> + "usb20_master_clk_src",
> + },
> + .num_parents = 1,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
> + .halt_reg = 0x5018,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x5018,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_cfg_noc_usb3_axi_clk",
> + .parent_names = (const char *[]){
> + "usb30_master_clk_src",
> + },
> + .num_parents = 1,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_dcc_ahb_clk = {
> + .halt_reg = 0x84004,
> + .clkr = {
> + .enable_reg = 0x84004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_dcc_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gp1_clk = {
> + .halt_reg = 0x64000,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x64000,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_gp1_clk",
> + .parent_names = (const char *[]){
> + "gp1_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gp2_clk = {
> + .halt_reg = 0x65000,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x65000,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_gp2_clk",
> + .parent_names = (const char *[]){
> + "gp2_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gp3_clk = {
> + .halt_reg = 0x66000,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x66000,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_gp3_clk",
> + .parent_names = (const char *[]){
> + "gp3_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gpu_bimc_gfx_clk = {
> + .halt_reg = 0x71010,
> + .halt_check = BRANCH_VOTED,
> + .clkr = {
> + .enable_reg = 0x71010,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_gpu_bimc_gfx_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gpu_cfg_ahb_clk = {
> + .halt_reg = 0x71004,
> + .halt_check = BRANCH_VOTED,
> + .clkr = {
> + .enable_reg = 0x71004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_gpu_cfg_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gpu_gpll0_clk = {
> + .halt_reg = 0x5200c,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x5200c,
> + .enable_mask = BIT(4),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_gpu_gpll0_clk",
> + .parent_names = (const char *[]){
> + "gpll0",
> + },
> + .num_parents = 1,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_gpu_gpll0_div_clk = {
> + .halt_reg = 0x5200c,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x5200c,
> + .enable_mask = BIT(3),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_gpu_gpll0_div_clk",
> + .parent_names = (const char *[]){
> + "gpll0_early_div",
> + },
> + .num_parents = 1,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_hmss_dvm_bus_clk = {
> + .halt_reg = 0x4808c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x4808c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_hmss_dvm_bus_clk",
> + .ops = &clk_branch2_ops,
> + .flags = CLK_IGNORE_UNUSED,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_hmss_rbcpr_clk = {
> + .halt_reg = 0x48008,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x48008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_hmss_rbcpr_clk",
> + .parent_names = (const char *[]){
> + "hmss_rbcpr_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_mmss_gpll0_clk = {
> + .halt_reg = 0x5200c,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x5200c,
> + .enable_mask = BIT(1),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_mmss_gpll0_clk",
> + .parent_names = (const char *[]){
> + "gpll0",
> + },
> + .num_parents = 1,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_mmss_gpll0_div_clk = {
> + .halt_reg = 0x5200c,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x5200c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_mmss_gpll0_div_clk",
> + .parent_names = (const char *[]){
> + "gpll0_early_div",
> + },
> + .num_parents = 1,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
> + .halt_reg = 0x9004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x9004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_mmss_noc_cfg_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
> + .halt_reg = 0x9000,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x9000,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_mmss_sys_noc_axi_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_mss_cfg_ahb_clk = {
> + .halt_reg = 0x8a000,
> + .clkr = {
> + .enable_reg = 0x8a000,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_mss_cfg_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
> + .halt_reg = 0x8a004,
> + .clkr = {
> + .enable_reg = 0x8a004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_mss_mnoc_bimc_axi_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
> + .halt_reg = 0x8a040,
> + .clkr = {
> + .enable_reg = 0x8a040,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_mss_q6_bimc_axi_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_mss_snoc_axi_clk = {
> + .halt_reg = 0x8a03c,
> + .clkr = {
> + .enable_reg = 0x8a03c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_mss_snoc_axi_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pdm2_clk = {
> + .halt_reg = 0x3300c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x3300c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pdm2_clk",
> + .parent_names = (const char *[]){
> + "pdm2_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_pdm_ahb_clk = {
> + .halt_reg = 0x33004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x33004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_pdm_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_prng_ahb_clk = {
> + .halt_reg = 0x34004,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x52004,
> + .enable_mask = BIT(13),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_prng_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qspi_ahb_clk = {
> + .halt_reg = 0x4d004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x4d004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qspi_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_qspi_ser_clk = {
> + .halt_reg = 0x4d008,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x4d008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_qspi_ser_clk",
> + .parent_names = (const char *[]){
> + "qspi_ser_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_rx0_usb2_clkref_clk = {
> + .halt_reg = 0x88018,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x88018,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_rx0_usb2_clkref_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_rx1_usb2_clkref_clk = {
> + .halt_reg = 0x88014,
> + .halt_check = BRANCH_HALT_VOTED,
> + .clkr = {
> + .enable_reg = 0x88014,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_rx1_usb2_clkref_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sdcc1_ahb_clk = {
> + .halt_reg = 0x16008,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x16008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_sdcc1_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sdcc1_apps_clk = {
> + .halt_reg = 0x16004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x16004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_sdcc1_apps_clk",
> + .parent_names = (const char *[]){
> + "sdcc1_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sdcc1_ice_core_clk = {
> + .halt_reg = 0x1600c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x1600c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_sdcc1_ice_core_clk",
> + .parent_names = (const char *[]){
> + "sdcc1_ice_core_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sdcc2_ahb_clk = {
> + .halt_reg = 0x14008,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x14008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_sdcc2_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_sdcc2_apps_clk = {
> + .halt_reg = 0x14004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x14004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_sdcc2_apps_clk",
> + .parent_names = (const char *[]){
> + "sdcc2_apps_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_ahb_clk = {
> + .halt_reg = 0x7500c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x7500c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_ahb_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_axi_clk = {
> + .halt_reg = 0x75008,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x75008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_axi_clk",
> + .parent_names = (const char *[]){
> + "ufs_axi_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_clkref_clk = {
> + .halt_reg = 0x88008,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x88008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_clkref_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_ice_core_clk = {
> + .halt_reg = 0x7600c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x7600c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_ice_core_clk",
> + .parent_names = (const char *[]){
> + "ufs_ice_core_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_phy_aux_clk = {
> + .halt_reg = 0x76040,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x76040,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_phy_aux_clk",
> + .parent_names = (const char *[]){
> + "ufs_phy_aux_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
> + .halt_reg = 0x75014,
> + .halt_check = BRANCH_HALT_SKIP,
> + .clkr = {
> + .enable_reg = 0x75014,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_rx_symbol_0_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
> + .halt_reg = 0x7605c,
> + .halt_check = BRANCH_HALT_SKIP,
> + .clkr = {
> + .enable_reg = 0x7605c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_rx_symbol_1_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
> + .halt_reg = 0x75010,
> + .halt_check = BRANCH_HALT_SKIP,
> + .clkr = {
> + .enable_reg = 0x75010,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_tx_symbol_0_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_ufs_unipro_core_clk = {
> + .halt_reg = 0x76008,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x76008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_unipro_core_clk",
> + .parent_names = (const char *[]){
> + "ufs_unipro_core_clk_src",
> + },
> + .flags = CLK_SET_RATE_PARENT,
> + .num_parents = 1,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb20_master_clk = {
> + .halt_reg = 0x2f004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2f004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_usb20_master_clk",
> + .parent_names = (const char *[]){
> + "usb20_master_clk_src"
> + },
> + .flags = CLK_SET_RATE_PARENT,
> + .num_parents = 1,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb20_mock_utmi_clk = {
> + .halt_reg = 0x2f00c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2f00c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_usb20_mock_utmi_clk",
> + .parent_names = (const char *[]){
> + "usb20_mock_utmi_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb20_sleep_clk = {
> + .halt_reg = 0x2f008,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x2f008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_usb20_sleep_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb30_master_clk = {
> + .halt_reg = 0xf008,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0xf008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_usb30_master_clk",
> + .parent_names = (const char *[]){
> + "usb30_master_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb30_mock_utmi_clk = {
> + .halt_reg = 0xf010,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0xf010,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_usb30_mock_utmi_clk",
> + .parent_names = (const char *[]){
> + "usb30_mock_utmi_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb30_sleep_clk = {
> + .halt_reg = 0xf00c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0xf00c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_usb30_sleep_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb3_clkref_clk = {
> + .halt_reg = 0x8800c,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x8800c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_usb3_clkref_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb3_phy_aux_clk = {
> + .halt_reg = 0x50000,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x50000,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_usb3_phy_aux_clk",
> + .parent_names = (const char *[]){
> + "usb3_phy_aux_clk_src",
> + },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb3_phy_pipe_clk = {
> + .halt_reg = 0x50004,
> + .halt_check = BRANCH_HALT_DELAY,
> + .clkr = {
> + .enable_reg = 0x50004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_usb3_phy_pipe_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
> + .halt_reg = 0x6a004,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x6a004,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_usb_phy_cfg_ahb2phy_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct gdsc ufs_gdsc = {
> + .gdscr = 0x75004,
> + .gds_hw_ctrl = 0x0,
> + .pd = {
> + .name = "ufs_gdsc",
> + },
> + .pwrsts = PWRSTS_OFF_ON,
> + .flags = VOTABLE,
> +};
> +
> +static struct gdsc usb_30_gdsc = {
> + .gdscr = 0xf004,
> + .gds_hw_ctrl = 0x0,
> + .pd = {
> + .name = "usb_30_gdsc",
> + },
> + .pwrsts = PWRSTS_OFF_ON,
> + .flags = VOTABLE,
> +};
> +
> +static struct gdsc pcie_0_gdsc = {
> + .gdscr = 0x6b004,
> + .gds_hw_ctrl = 0x0,
> + .pd = {
> + .name = "pcie_0_gdsc",
> + },
> + .pwrsts = PWRSTS_OFF_ON,
> + .flags = VOTABLE,
> +};
> +
> +struct clk_hw *gcc_sdm660_hws[] = {
> + [GCC_XO] = &xo.hw,
> + [GCC_GPLL0_EARLY_DIV] = &gpll0_early_div.hw,
> + [GCC_GPLL1_EARLY_DIV] = &gpll1_early_div.hw,
> +};
> +
> +static struct clk_regmap *gcc_660_clocks[] = {
> + [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
> + [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
> + [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
> + [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
> + [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
> + [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
> + [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
> + [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
> + [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
> + [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
> + [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
> + [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
> + [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
> + [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
> + [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
> + [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
> + [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
> + [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
> + [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
> + [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
> + [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
> + [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
> + [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
> + [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,
> + [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,
> + [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
> + [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
> + [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
> + [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
> + [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
> + [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
> + [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
> + [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
> + [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
> + [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
> + [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
> + [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
> + [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
> + [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
> + [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
> + [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
> + [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
> + [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
> + [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
> + [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
> + [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
> + [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
> + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
> + [GCC_CFG_NOC_USB2_AXI_CLK] = &gcc_cfg_noc_usb2_axi_clk.clkr,
> + [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,
> + [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
> + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
> + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
> + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
> + [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
> + [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
> + [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,
> + [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,
> + [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr,
> + [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
> + [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,
> + [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
> + [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
> + [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,
> + [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
> + [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
> + [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
> + [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
> + [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
> + [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
> + [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
> + [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
> + [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
> + [GCC_RX0_USB2_CLKREF_CLK] = &gcc_rx0_usb2_clkref_clk.clkr,
> + [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
> + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
> + [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
> + [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
> + [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
> + [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
> + [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
> + [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
> + [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
> + [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
> + [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,
> + [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
> + [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
> + [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
> + [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
> + [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
> + [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
> + [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
> + [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
> + [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
> + [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
> + [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
> + [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
> + [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
> + [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
> + [GP1_CLK_SRC] = &gp1_clk_src.clkr,
> + [GP2_CLK_SRC] = &gp2_clk_src.clkr,
> + [GP3_CLK_SRC] = &gp3_clk_src.clkr,
> + [GPLL0] = &gpll0.clkr,
> + [GPLL0_EARLY] = &gpll0_early.clkr,
> + [GPLL1] = &gpll1.clkr,
> + [GPLL1_EARLY] = &gpll1_early.clkr,
> + [GPLL1] = &gpll1.clkr,
> + [GPLL4_EARLY] = &gpll4_early.clkr,
> + [GPLL4] = &gpll4.clkr,
> + [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
> + [HMSS_GPLL4_CLK_SRC] = &hmss_gpll4_clk_src.clkr,
> + [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
> + [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
> + [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
> + [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
> + [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
> + [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
> + [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
> + [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
> + [UFS_PHY_AUX_CLK_SRC] = &ufs_phy_aux_clk_src.clkr,
> + [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr,
> + [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
> + [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
> + [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
> + [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
> + [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
> +};
> +
> +static struct gdsc *gcc_660_gdscs[] = {
> + [UFS_GDSC] = &ufs_gdsc,
> + [USB_30_GDSC] = &usb_30_gdsc,
> + [PCIE_0_GDSC] = &pcie_0_gdsc,
> +};
> +
> +static const struct qcom_reset_map gcc_660_resets[] = {
> + [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
> + [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
> + [GCC_UFS_BCR] = { 0x75000 },
> + [GCC_USB3_DP_PHY_BCR] = { 0x50028 },
> + [GCC_USB3_PHY_BCR] = { 0x50020 },
> + [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
> + [GCC_USB_20_BCR] = { 0x2f000 },
> + [GCC_USB_30_BCR] = { 0xf000 },
> + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
> +};
> +
> +static const struct regmap_config gcc_660_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .max_register = 0x94000,
> + .fast_io = true,
> +};
> +
> +static const struct qcom_cc_desc gcc_660_desc = {
> + .config = &gcc_660_regmap_config,
> + .clks = gcc_660_clocks,
> + .num_clks = ARRAY_SIZE(gcc_660_clocks),
> + .resets = gcc_660_resets,
> + .num_resets = ARRAY_SIZE(gcc_660_resets),
> + .gdscs = gcc_660_gdscs,
> + .num_gdscs = ARRAY_SIZE(gcc_660_gdscs),
> +};
> +
> +static const struct of_device_id gcc_660_match_table[] = {
> + { .compatible = "qcom,gcc-sdm660" },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, gcc_660_match_table);
> +
> +static int gcc_660_probe(struct platform_device *pdev)
> +{
> + int i, ret = 0;
> + struct regmap *regmap;
> +
> + regmap = qcom_cc_map(pdev, &gcc_660_desc);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + /*
> + * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
> + * turned off by hardware during certain apps low power modes.
> + */
> + ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
> + if (ret)
> + return ret;
> +
> + /* Register the hws */
> + for (i = 0; i < ARRAY_SIZE(gcc_sdm660_hws); i++) {
> + ret = devm_clk_hw_register(&pdev->dev, gcc_sdm660_hws[i]);
> + if (ret)
> + return ret;
> + }
> +
> + return qcom_cc_really_probe(pdev, &gcc_660_desc, regmap);
> +}
> +
> +static struct platform_driver gcc_660_driver = {
> + .probe = gcc_660_probe,
> + .driver = {
> + .name = "gcc-sdm660",
> + .of_match_table = gcc_660_match_table,
> + },
> +};
> +
> +static int __init gcc_660_init(void)
> +{
> + return platform_driver_register(&gcc_660_driver);
> +}
> +core_initcall_sync(gcc_660_init);
> +
> +static void __exit gcc_660_exit(void)
> +{
> + platform_driver_unregister(&gcc_660_driver);
> +}
> +module_exit(gcc_660_exit);
> +
> +MODULE_DESCRIPTION("QCOM GCC sdm660 Driver");
> diff --git a/include/dt-bindings/clock/qcom,gcc-sdm660.h b/include/dt-bindings/clock/qcom,gcc-sdm660.h
> new file mode 100644
> index 000000000000..76aabcc5e7e3
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,gcc-sdm660.h
> @@ -0,0 +1,159 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2018, Craig Tatlor.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H
> +#define _DT_BINDINGS_CLK_MSM_GCC_660_H
> +
> +#define GCC_XO 0
> +#define GCC_GPLL0_EARLY_DIV 1
> +#define GCC_GPLL1_EARLY_DIV 2
> +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 3
> +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 4
> +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 5
> +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 6
> +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 7
> +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 8
> +#define BLSP1_QUP4_I2C_APPS_CLK_SRC 9
> +#define BLSP1_QUP4_SPI_APPS_CLK_SRC 10
> +#define BLSP1_UART1_APPS_CLK_SRC 11
> +#define BLSP1_UART2_APPS_CLK_SRC 12
> +#define BLSP2_QUP1_I2C_APPS_CLK_SRC 13
> +#define BLSP2_QUP1_SPI_APPS_CLK_SRC 14
> +#define BLSP2_QUP2_I2C_APPS_CLK_SRC 15
> +#define BLSP2_QUP2_SPI_APPS_CLK_SRC 16
> +#define BLSP2_QUP3_I2C_APPS_CLK_SRC 17
> +#define BLSP2_QUP3_SPI_APPS_CLK_SRC 18
> +#define BLSP2_QUP4_I2C_APPS_CLK_SRC 19
> +#define BLSP2_QUP4_SPI_APPS_CLK_SRC 20
> +#define BLSP2_UART1_APPS_CLK_SRC 21
> +#define BLSP2_UART2_APPS_CLK_SRC 22
> +#define GCC_AGGRE2_UFS_AXI_CLK 23
> +#define GCC_AGGRE2_USB3_AXI_CLK 24
> +#define GCC_BIMC_GFX_CLK 25
> +#define GCC_BIMC_HMSS_AXI_CLK 26
> +#define GCC_BIMC_MSS_Q6_AXI_CLK 27
> +#define GCC_BLSP1_AHB_CLK 28
> +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 29
> +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 30
> +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 31
> +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 32
> +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 33
> +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 34
> +#define GCC_BLSP1_QUP4_I2C_APPS_CLK 35
> +#define GCC_BLSP1_QUP4_SPI_APPS_CLK 36
> +#define GCC_BLSP1_UART1_APPS_CLK 37
> +#define GCC_BLSP1_UART2_APPS_CLK 38
> +#define GCC_BLSP2_AHB_CLK 39
> +#define GCC_BLSP2_QUP1_I2C_APPS_CLK 40
> +#define GCC_BLSP2_QUP1_SPI_APPS_CLK 41
> +#define GCC_BLSP2_QUP2_I2C_APPS_CLK 42
> +#define GCC_BLSP2_QUP2_SPI_APPS_CLK 43
> +#define GCC_BLSP2_QUP3_I2C_APPS_CLK 44
> +#define GCC_BLSP2_QUP3_SPI_APPS_CLK 46
> +#define GCC_BLSP2_QUP4_I2C_APPS_CLK 45
> +#define GCC_BLSP2_QUP4_SPI_APPS_CLK 46
> +#define GCC_BLSP2_UART1_APPS_CLK 47
> +#define GCC_BLSP2_UART2_APPS_CLK 48
> +#define GCC_BOOT_ROM_AHB_CLK 49
> +#define GCC_CFG_NOC_USB2_AXI_CLK 50
> +#define GCC_CFG_NOC_USB3_AXI_CLK 51
> +#define GCC_DCC_AHB_CLK 52
> +#define GCC_GP1_CLK 53
> +#define GCC_GP2_CLK 54
> +#define GCC_GP3_CLK 55
> +#define GCC_GPU_BIMC_GFX_CLK 56
> +#define GCC_GPU_CFG_AHB_CLK 57
> +#define GCC_GPU_GPLL0_CLK 58
> +#define GCC_GPU_GPLL0_DIV_CLK 59
> +#define GCC_HMSS_DVM_BUS_CLK 60
> +#define GCC_HMSS_RBCPR_CLK 61
> +#define GCC_MMSS_GPLL0_CLK 62
> +#define GCC_MMSS_GPLL0_DIV_CLK 63
> +#define GCC_MMSS_NOC_CFG_AHB_CLK 64
> +#define GCC_MMSS_SYS_NOC_AXI_CLK 65
> +#define GCC_MSS_CFG_AHB_CLK 66
> +#define GCC_MSS_GPLL0_DIV_CLK 67
> +#define GCC_MSS_MNOC_BIMC_AXI_CLK 68
> +#define GCC_MSS_Q6_BIMC_AXI_CLK 69
> +#define GCC_MSS_SNOC_AXI_CLK 70
> +#define GCC_PDM2_CLK 71
> +#define GCC_PDM_AHB_CLK 72
> +#define GCC_PRNG_AHB_CLK 73
> +#define GCC_QSPI_AHB_CLK 74
> +#define GCC_QSPI_SER_CLK 75
> +#define GCC_SDCC1_AHB_CLK 76
> +#define GCC_SDCC1_APPS_CLK 77
> +#define GCC_SDCC1_ICE_CORE_CLK 78
> +#define GCC_SDCC2_AHB_CLK 79
> +#define GCC_SDCC2_APPS_CLK 80
> +#define GCC_UFS_AHB_CLK 81
> +#define GCC_UFS_AXI_CLK 82
> +#define GCC_UFS_CLKREF_CLK 83
> +#define GCC_UFS_ICE_CORE_CLK 84
> +#define GCC_UFS_PHY_AUX_CLK 85
> +#define GCC_UFS_RX_SYMBOL_0_CLK 86
> +#define GCC_UFS_RX_SYMBOL_1_CLK 87
> +#define GCC_UFS_TX_SYMBOL_0_CLK 88
> +#define GCC_UFS_UNIPRO_CORE_CLK 89
> +#define GCC_USB20_MASTER_CLK 90
> +#define GCC_USB20_MOCK_UTMI_CLK 91
> +#define GCC_USB20_SLEEP_CLK 92
> +#define GCC_USB30_MASTER_CLK 93
> +#define GCC_USB30_MOCK_UTMI_CLK 94
> +#define GCC_USB30_SLEEP_CLK 95
> +#define GCC_USB3_CLKREF_CLK 96
> +#define GCC_USB3_PHY_AUX_CLK 97
> +#define GCC_USB3_PHY_PIPE_CLK 98
> +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 99
> +#define GP1_CLK_SRC 100
> +#define GP2_CLK_SRC 101
> +#define GP3_CLK_SRC 102
> +#define GPLL0 103
> +#define GPLL0_EARLY 104
> +#define GPLL1 105
> +#define GPLL1_EARLY 106
> +#define GPLL4 107
> +#define GPLL4_EARLY 108
> +#define HMSS_GPLL0_CLK_SRC 109
> +#define HMSS_GPLL4_CLK_SRC 110
> +#define HMSS_RBCPR_CLK_SRC 111
> +#define PDM2_CLK_SRC 112
> +#define QSPI_SER_CLK_SRC 113
> +#define SDCC1_APPS_CLK_SRC 114
> +#define SDCC1_ICE_CORE_CLK_SRC 115
> +#define SDCC2_APPS_CLK_SRC 116
> +#define UFS_AXI_CLK_SRC 117
> +#define UFS_ICE_CORE_CLK_SRC 118
> +#define UFS_PHY_AUX_CLK_SRC 119
> +#define UFS_UNIPRO_CORE_CLK_SRC 120
> +#define USB20_MASTER_CLK_SRC 121
> +#define USB20_MOCK_UTMI_CLK_SRC 122
> +#define USB30_MASTER_CLK_SRC 123
> +#define USB30_MOCK_UTMI_CLK_SRC 124
> +#define USB3_PHY_AUX_CLK_SRC 125
> +#define GPLL0_OUT_MSSCC 126
> +#define GCC_UFS_AXI_HW_CTL_CLK 127
> +#define GCC_UFS_ICE_CORE_HW_CTL_CLK 128
> +#define GCC_UFS_PHY_AUX_HW_CTL_CLK 129
> +#define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 130
> +#define GCC_RX0_USB2_CLKREF_CLK 131
> +#define GCC_RX1_USB2_CLKREF_CLK 132
> +
> +#define PCIE_0_GDSC 0
> +#define UFS_GDSC 1
> +#define USB_30_GDSC 2
> +
> +#define GCC_QUSB2PHY_PRIM_BCR 0
> +#define GCC_QUSB2PHY_SEC_BCR 1
> +#define GCC_UFS_BCR 2
> +#define GCC_USB3_DP_PHY_BCR 3
> +#define GCC_USB3_PHY_BCR 4
> +#define GCC_USB3PHY_PHY_BCR 5
> +#define GCC_USB_20_BCR 6
> +#define GCC_USB_30_BCR 7
> +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 8
> +
> +#endif
>
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
--
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] clk: qcom: Add Global Clock controller (GCC) driver for SDM660
2018-08-13 6:55 ` [PATCH] clk: qcom: Add Global Clock controller (GCC) driver for SDM660 Taniya Das
@ 2018-08-13 7:45 ` Craig Tatlor
2018-09-24 12:44 ` Heiko Stuebner
2018-08-13 9:44 ` Craig Tatlor
1 sibling, 1 reply; 18+ messages in thread
From: Craig Tatlor @ 2018-08-13 7:45 UTC (permalink / raw)
To: Taniya Das
Cc: linux-arm-msm, Michael Turquette, Stephen Boyd, Rob Herring,
Mark Rutland, Andy Gross, David Brown, linux-clk, devicetree,
linux-kernel, linux-soc
On 13 August 2018 07:55:34 BST, Taniya Das <tdas@codeaurora=2Eorg> wrote:
>Hello Craig,
>
>Could you please correct the authorship and also provide the reference=20
>to code where this is picked from?
Okay,=20
Got code from here https://github=2Ecom/sonyxperiadev/kernel/blob/aosp/LA=
=2EUM=2E6=2E4=2Er1/drivers/clk/qcom/gcc-sdm660=2Ec
but changed it quite a bit for upstream,
Should I change the commit author and add your signed off by and say I did=
cleanups on my signed off by=2E
Also, hey, you wrote the original driver :)
>
>On 8/11/2018 1:51 AM, Craig Tatlor wrote:
>> Add support for the global clock controller found on SDM660
>> based devices=2E This should allow most non-multimedia device
>> drivers to probe and control their clocks=2E
>> Based on CAF implementation=2E
>>=20
>> Signed-off-by: Craig Tatlor <ctatlor97@gmail=2Ecom>
>> ---
>> =2E=2E=2E/devicetree/bindings/clock/qcom,gcc=2Etxt | 1 +
>> drivers/clk/qcom/Kconfig | 9 +
>> drivers/clk/qcom/Makefile | 1 +
>> drivers/clk/qcom/gcc-sdm660=2Ec | 2479
>+++++++++++++++++
>> include/dt-bindings/clock/qcom,gcc-sdm660=2Eh | 159 ++
>> 5 files changed, 2649 insertions(+)
>> create mode 100644 drivers/clk/qcom/gcc-sdm660=2Ec
>> create mode 100644 include/dt-bindings/clock/qcom,gcc-sdm660=2Eh
>>=20
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc=2Etxt
>b/Documentation/devicetree/bindings/clock/qcom,gcc=2Etxt
>> index 664ea1fd6c76=2E=2Ee498ad2e8db8 100644
>> --- a/Documentation/devicetree/bindings/clock/qcom,gcc=2Etxt
>> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc=2Etxt
>> @@ -19,6 +19,7 @@ Required properties :
>> "qcom,gcc-msm8996"
>> "qcom,gcc-msm8998"
>> "qcom,gcc-mdm9615"
>> + "qcom,gcc-sdm660"
>> "qcom,gcc-sdm845"
>> =20
>> - reg : shall contain base register location and length
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index 9c3480dcc38a=2E=2Ec4bda6d24c1f 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -226,6 +226,15 @@ config MSM_GCC_8998
>> Say Y if you want to use peripheral devices such as UART, SPI,
>> i2c, USB, UFS, SD/eMMC, PCIe, etc=2E
>> =20
>> +config SDM_GCC_660
>> + tristate "SDM660 Global Clock Controller"
>> + select QCOM_GDSC
>> + depends on COMMON_CLK_QCOM
>> + help
>> + Support for the global clock controller on SDM660 devices=2E
>> + Say Y if you want to use peripheral devices such as UART, SPI,
>> + i2C, USB, UFS, SDDC, PCIe, etc=2E
>> +
>> config SDM_GCC_845
>> tristate "SDM845 Global Clock Controller"
>> select QCOM_GDSC
>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>> index 762c01137c2f=2E=2E6e37d30d7c02 100644
>> --- a/drivers/clk/qcom/Makefile
>> +++ b/drivers/clk/qcom/Makefile
>> @@ -38,6 +38,7 @@ obj-$(CONFIG_QCOM_A53PLL) +=3D a53-pll=2Eo
>> obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) +=3D apcs-msm8916=2Eo
>> obj-$(CONFIG_QCOM_CLK_RPM) +=3D clk-rpm=2Eo
>> obj-$(CONFIG_QCOM_CLK_SMD_RPM) +=3D clk-smd-rpm=2Eo
>> +obj-$(CONFIG_SDM_GCC_660) +=3D gcc-sdm660=2Eo
>> obj-$(CONFIG_SDM_GCC_845) +=3D gcc-sdm845=2Eo
>> obj-$(CONFIG_SDM_VIDEOCC_845) +=3D videocc-sdm845=2Eo
>> obj-$(CONFIG_SPMI_PMIC_CLKDIV) +=3D clk-spmi-pmic-div=2Eo
>> diff --git a/drivers/clk/qcom/gcc-sdm660=2Ec
>b/drivers/clk/qcom/gcc-sdm660=2Ec
>> new file mode 100644
>> index 000000000000=2E=2Ebdb445aa4baa
>> --- /dev/null
>> +++ b/drivers/clk/qcom/gcc-sdm660=2Ec
>> @@ -0,0 +1,2479 @@
>> +// SPDX-License-Identifier: GPL-2=2E0
>> +/*
>> + * Copyright (c) 2016-2017, The Linux Foundation=2E All rights
>reserved=2E
>> + * Copyright (c) 2018, Craig Tatlor=2E
>> + */
>> +
>> +#include <linux/kernel=2Eh>
>> +#include <linux/bitops=2Eh>
>> +#include <linux/err=2Eh>
>> +#include <linux/platform_device=2Eh>
>> +#include <linux/module=2Eh>
>> +#include <linux/of=2Eh>
>> +#include <linux/of_device=2Eh>
>> +#include <linux/clk-provider=2Eh>
>> +#include <linux/regmap=2Eh>
>> +#include <linux/reset-controller=2Eh>
>> +
>> +#include <dt-bindings/clock/qcom,gcc-sdm660=2Eh>
>> +
>> +#include "common=2Eh"
>> +#include "clk-regmap=2Eh"
>> +#include "clk-alpha-pll=2Eh"
>> +#include "clk-rcg=2Eh"
>> +#include "clk-branch=2Eh"
>> +#include "reset=2Eh"
>> +#include "gdsc=2Eh"
>> +
>> +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
>> +
>> +enum {
>> + P_XO,
>> + P_SLEEP_CLK,
>> + P_GPLL0,
>> + P_GPLL1,
>> + P_GPLL4,
>> + P_GPLL0_EARLY_DIV,
>> + P_GPLL1_EARLY_DIV,
>> +};
>> +
>> +static const struct parent_map
>gcc_parent_map_xo_gpll0_gpll0_early_div[] =3D {
>> + { P_XO, 0 },
>> + { P_GPLL0, 1 },
>> + { P_GPLL0_EARLY_DIV, 6 },
>> +};
>> +
>> +static const char * const
>gcc_parent_names_xo_gpll0_gpll0_early_div[] =3D {
>> + "xo",
>> + "gpll0",
>> + "gpll0_early_div",
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_xo_gpll0[] =3D {
>> + { P_XO, 0 },
>> + { P_GPLL0, 1 },
>> +};
>> +
>> +static const char * const gcc_parent_names_xo_gpll0[] =3D {
>> + "xo",
>> + "gpll0",
>> +};
>> +
>> +static const struct parent_map
>gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] =3D {
>> + { P_XO, 0 },
>> + { P_GPLL0, 1 },
>> + { P_SLEEP_CLK, 5 },
>> + { P_GPLL0_EARLY_DIV, 6 },
>> +};
>> +
>> +static const char * const
>gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div[] =3D {
>> + "xo",
>> + "gpll0",
>> + "sleep_clk",
>> + "gpll0_early_div",
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_xo_sleep_clk[] =3D {
>> + { P_XO, 0 },
>> + { P_SLEEP_CLK, 5 },
>> +};
>> +
>> +static const char * const gcc_parent_names_xo_sleep_clk[] =3D {
>> + "xo",
>> + "sleep_clk",
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_xo_gpll4[] =3D {
>> + { P_XO, 0 },
>> + { P_GPLL4, 5 },
>> +};
>> +
>> +static const char * const gcc_parent_names_xo_gpll4[] =3D {
>> + "xo",
>> + "gpll4",
>> +};
>> +
>> +static const struct parent_map
>gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] =3D
>{
>> + { P_XO, 0 },
>> + { P_GPLL0, 1 },
>> + { P_GPLL0_EARLY_DIV, 3 },
>> + { P_GPLL1, 4 },
>> + { P_GPLL4, 5 },
>> + { P_GPLL1_EARLY_DIV, 6 },
>> +};
>> +
>> +static const char * const
>gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[]
>=3D {
>> + "xo",
>> + "gpll0",
>> + "gpll0_early_div",
>> + "gpll1",
>> + "gpll4",
>> + "gpll1_early_div",
>> +};
>> +
>> +static const struct parent_map
>gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] =3D {
>> + { P_XO, 0 },
>> + { P_GPLL0, 1 },
>> + { P_GPLL4, 5 },
>> + { P_GPLL0_EARLY_DIV, 6 },
>> +};
>> +
>> +static const char * const
>gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div[] =3D {
>> + "xo",
>> + "gpll0",
>> + "gpll4",
>> + "gpll0_early_div",
>> +};
>> +
>> +static const struct parent_map
>gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] =3D {
>> + { P_XO, 0 },
>> + { P_GPLL0, 1 },
>> + { P_GPLL0_EARLY_DIV, 2 },
>> + { P_GPLL4, 5 },
>> +};
>> +
>> +static const char * const
>gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4[] =3D {
>> + "xo",
>> + "gpll0",
>> + "gpll0_early_div",
>> + "gpll4",
>> +};
>> +
>> +static struct clk_fixed_factor xo =3D {
>> + =2Emult =3D 1,
>> + =2Ediv =3D 1,
>> + =2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "xo",
>> + =2Eparent_names =3D (const char *[]){ "xo_board" },
>> + =2Enum_parents =3D 1,
>> + =2Eops =3D &clk_fixed_factor_ops,
>> + },
>> +};
>> +
>> +static struct clk_alpha_pll gpll0_early =3D {
>> + =2Eoffset =3D 0x0,
>> + =2Eregs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> + =2Eclkr =3D {
>> + =2Eenable_reg =3D 0x52000,
>> + =2Eenable_mask =3D BIT(0),
>> + =2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "gpll0_early",
>> + =2Eparent_names =3D (const char *[]){ "xo" },
>> + =2Enum_parents =3D 1,
>> + =2Eops =3D &clk_alpha_pll_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor gpll0_early_div =3D {
>> + =2Emult =3D 1,
>> + =2Ediv =3D 2,
>> + =2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "gpll0_early_div",
>> + =2Eparent_names =3D (const char *[]){ "gpll0_early" },
>> + =2Enum_parents =3D 1,
>> + =2Eops =3D &clk_fixed_factor_ops,
>> + },
>> +};
>> +
>> +static struct clk_alpha_pll_postdiv gpll0 =3D {
>> + =2Eoffset =3D 0x00000,
>> + =2Eregs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "gpll0",
>> + =2Eparent_names =3D (const char *[]){ "gpll0_early" },
>> + =2Enum_parents =3D 1,
>> + =2Eops =3D &clk_alpha_pll_postdiv_ops,
>> + },
>> +};
>> +
>> +static struct clk_alpha_pll gpll1_early =3D {
>> + =2Eoffset =3D 0x1000,
>> + =2Eregs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> + =2Eclkr =3D {
>> + =2Eenable_reg =3D 0x52000,
>> + =2Eenable_mask =3D BIT(1),
>> + =2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "gpll1_early",
>> + =2Eparent_names =3D (const char *[]){ "xo" },
>> + =2Enum_parents =3D 1,
>> + =2Eops =3D &clk_alpha_pll_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor gpll1_early_div =3D {
>> + =2Emult =3D 1,
>> + =2Ediv =3D 2,
>> + =2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "gpll1_early_div",
>> + =2Eparent_names =3D (const char *[]){ "gpll1_early" },
>> + =2Enum_parents =3D 1,
>> + =2Eops =3D &clk_fixed_factor_ops,
>> + },
>> +};
>> +
>> +static struct clk_alpha_pll_postdiv gpll1 =3D {
>> + =2Eoffset =3D 0x1000,
>> + =2Eregs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "gpll1",
>> + =2Eparent_names =3D (const char *[]){ "gpll1_early" },
>> + =2Enum_parents =3D 1,
>> + =2Eops =3D &clk_alpha_pll_postdiv_ops,
>> + },
>> +};
>> +
>> +static struct clk_alpha_pll gpll4_early =3D {
>> + =2Eoffset =3D 0x77000,
>> + =2Eregs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> + =2Eclkr =3D {
>> + =2Eenable_reg =3D 0x52000,
>> + =2Eenable_mask =3D BIT(4),
>> + =2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "gpll4_early",
>> + =2Eparent_names =3D (const char *[]){ "xo" },
>> + =2Enum_parents =3D 1,
>> + =2Eops =3D &clk_alpha_pll_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_alpha_pll_postdiv gpll4 =3D {
>> + =2Eoffset =3D 0x77000,
>> + =2Eregs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data)
>> + {
>> + =2Ename =3D "gpll4",
>> + =2Eparent_names =3D (const char *[]) { "gpll4_early" },
>> + =2Enum_parents =3D 1,
>> + =2Eops =3D &clk_alpha_pll_postdiv_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] =3D {
>> + F(19200000, P_XO, 1, 0, 0),
>> + F(50000000, P_GPLL0, 12, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x19020,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_i2c_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp1_qup1_i2c_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] =3D {
>> + F(960000, P_XO, 10, 1, 2),
>> + F(4800000, P_XO, 4, 0, 0),
>> + F(9600000, P_XO, 2, 0, 0),
>> + F(15000000, P_GPLL0, 10, 1, 4),
>> + F(19200000, P_XO, 1, 0, 0),
>> + F(25000000, P_GPLL0, 12, 1, 2),
>> + F(50000000, P_GPLL0, 12, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x1900c,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_spi_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp1_qup1_spi_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x1b020,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_i2c_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp1_qup2_i2c_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x1b00c,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_spi_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp1_qup2_spi_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x1d020,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_i2c_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp1_qup3_i2c_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x1d00c,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_spi_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp1_qup3_spi_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x1f020,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_i2c_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp1_qup4_i2c_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x1f00c,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_spi_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp1_qup4_spi_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] =3D {
>> + F(3686400, P_GPLL0, 1, 96, 15625),
>> + F(7372800, P_GPLL0, 1, 192, 15625),
>> + F(14745600, P_GPLL0, 1, 384, 15625),
>> + F(16000000, P_GPLL0, 5, 2, 15),
>> + F(19200000, P_XO, 1, 0, 0),
>> + F(24000000, P_GPLL0, 5, 1, 5),
>> + F(32000000, P_GPLL0, 1, 4, 75),
>> + F(40000000, P_GPLL0, 15, 0, 0),
>> + F(46400000, P_GPLL0, 1, 29, 375),
>> + F(48000000, P_GPLL0, 12=2E5, 0, 0),
>> + F(51200000, P_GPLL0, 1, 32, 375),
>> + F(56000000, P_GPLL0, 1, 7, 75),
>> + F(58982400, P_GPLL0, 1, 1536, 15625),
>> + F(60000000, P_GPLL0, 10, 0, 0),
>> + F(63157895, P_GPLL0, 9=2E5, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 blsp1_uart1_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x1a00c,
>> + =2Emnd_width =3D 16,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_uart1_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp1_uart1_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp1_uart2_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x1c00c,
>> + =2Emnd_width =3D 16,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_uart1_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp1_uart2_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x26020,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_i2c_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp2_qup1_i2c_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x2600c,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_spi_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp2_qup1_spi_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x28020,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_i2c_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp2_qup2_i2c_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x2800c,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_spi_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp2_qup2_spi_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x2a020,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_i2c_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp2_qup3_i2c_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x2a00c,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_spi_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp2_qup3_spi_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x2c020,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_i2c_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp2_qup4_i2c_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x2c00c,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_spi_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp2_qup4_spi_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp2_uart1_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x2700c,
>> + =2Emnd_width =3D 16,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_uart1_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp2_uart1_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp2_uart2_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x2900c,
>> + =2Emnd_width =3D 16,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_uart1_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp2_uart2_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gp1_clk_src[] =3D {
>> + F(19200000, P_XO, 1, 0, 0),
>> + F(100000000, P_GPLL0, 6, 0, 0),
>> + F(200000000, P_GPLL0, 3, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gp1_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x64004,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_gp1_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "gp1_clk_src",
>> + =2Eparent_names =3D
>gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
>> + =2Enum_parents =3D 4,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 gp2_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x65004,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_gp1_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "gp2_clk_src",
>> + =2Eparent_names =3D
>gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
>> + =2Enum_parents =3D 4,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 gp3_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x66004,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_gp1_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "gp3_clk_src",
>> + =2Eparent_names =3D
>gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
>> + =2Enum_parents =3D 4,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] =3D {
>> + F(300000000, P_GPLL0, 2, 0, 0),
>> + F(600000000, P_GPLL0, 1, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 hmss_gpll0_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x4805c,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_hmss_gpll0_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "hmss_gpll0_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_hmss_gpll4_clk_src[] =3D {
>> + F(384000000, P_GPLL4, 4, 0, 0),
>> + F(768000000, P_GPLL4, 2, 0, 0),
>> + F(1536000000, P_GPLL4, 1, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 hmss_gpll4_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x48074,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll4,
>> + =2Efreq_tbl =3D ftbl_hmss_gpll4_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "hmss_gpll4_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll4,
>> + =2Enum_parents =3D 2,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] =3D {
>> + F(19200000, P_XO, 1, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 hmss_rbcpr_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x48044,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_hmss_rbcpr_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "hmss_rbcpr_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0,
>> + =2Enum_parents =3D 2,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_pdm2_clk_src[] =3D {
>> + F(60000000, P_GPLL0, 10, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 pdm2_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x33010,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_pdm2_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "pdm2_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_qspi_ser_clk_src[] =3D {
>> + F(19200000, P_XO, 1, 0, 0),
>> + F(80200000, P_GPLL1_EARLY_DIV, 5, 0, 0),
>> + F(160400000, P_GPLL1, 5, 0, 0),
>> + F(267333333, P_GPLL1, 3, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 qspi_ser_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x4d00c,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D
>gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
>> + =2Efreq_tbl =3D ftbl_qspi_ser_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "qspi_ser_clk_src",
>> + =2Eparent_names =3D
>gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
>> + =2Enum_parents =3D 6,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] =3D {
>> + F(144000, P_XO, 16, 3, 25),
>> + F(400000, P_XO, 12, 1, 4),
>> + F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
>> + F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
>> + F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
>> + F(100000000, P_GPLL0, 6, 0, 0),
>> + F(192000000, P_GPLL4, 8, 0, 0),
>> + F(384000000, P_GPLL4, 4, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 sdcc1_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x1602c,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_sdcc1_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "sdcc1_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div,
>> + =2Enum_parents =3D 4,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] =3D {
>> + F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
>> + F(150000000, P_GPLL0, 4, 0, 0),
>> + F(200000000, P_GPLL0, 3, 0, 0),
>> + F(300000000, P_GPLL0, 2, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 sdcc1_ice_core_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x16010,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_sdcc1_ice_core_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "sdcc1_ice_core_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] =3D {
>> + F(144000, P_XO, 16, 3, 25),
>> + F(400000, P_XO, 12, 1, 4),
>> + F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
>> + F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
>> + F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
>> + F(100000000, P_GPLL0, 6, 0, 0),
>> + F(192000000, P_GPLL4, 8, 0, 0),
>> + F(200000000, P_GPLL0, 3, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 sdcc2_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x14010,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4,
>> + =2Efreq_tbl =3D ftbl_sdcc2_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "sdcc2_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4,
>> + =2Enum_parents =3D 4,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_ufs_axi_clk_src[] =3D {
>> + F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
>> + F(100000000, P_GPLL0, 6, 0, 0),
>> + F(150000000, P_GPLL0, 4, 0, 0),
>> + F(200000000, P_GPLL0, 3, 0, 0),
>> + F(240000000, P_GPLL0, 2=2E5, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 ufs_axi_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x75018,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_ufs_axi_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "ufs_axi_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] =3D {
>> + F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
>> + F(150000000, P_GPLL0, 4, 0, 0),
>> + F(300000000, P_GPLL0, 2, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 ufs_ice_core_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x76010,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_ufs_ice_core_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "ufs_ice_core_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 ufs_phy_aux_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x76044,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_sleep_clk,
>> + =2Efreq_tbl =3D ftbl_hmss_rbcpr_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "ufs_phy_aux_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_sleep_clk,
>> + =2Enum_parents =3D 2,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] =3D {
>> + F(37500000, P_GPLL0_EARLY_DIV, 8, 0, 0),
>> + F(75000000, P_GPLL0, 8, 0, 0),
>> + F(150000000, P_GPLL0, 4, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 ufs_unipro_core_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x76028,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_ufs_unipro_core_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "ufs_unipro_core_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_usb20_master_clk_src[] =3D {
>> + F(19200000, P_XO, 1, 0, 0),
>> + F(60000000, P_GPLL0, 10, 0, 0),
>> + F(120000000, P_GPLL0, 5, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 usb20_master_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x2f010,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_usb20_master_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "usb20_master_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_usb20_mock_utmi_clk_src[] =3D {
>> + F(19200000, P_XO, 1, 0, 0),
>> + F(60000000, P_GPLL0, 10, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 usb20_mock_utmi_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x2f024,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_usb20_mock_utmi_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "usb20_mock_utmi_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_usb30_master_clk_src[] =3D {
>> + F(19200000, P_XO, 1, 0, 0),
>> + F(66666667, P_GPLL0_EARLY_DIV, 4=2E5, 0, 0),
>> + F(120000000, P_GPLL0, 5, 0, 0),
>> + F(133333333, P_GPLL0, 4=2E5, 0, 0),
>> + F(150000000, P_GPLL0, 4, 0, 0),
>> + F(200000000, P_GPLL0, 3, 0, 0),
>> + F(240000000, P_GPLL0, 2=2E5, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 usb30_master_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0xf014,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_usb30_master_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "usb30_master_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] =3D {
>> + F(19200000, P_XO, 1, 0, 0),
>> + F(40000000, P_GPLL0_EARLY_DIV, 7=2E5, 0, 0),
>> + F(60000000, P_GPLL0, 10, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 usb30_mock_utmi_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0xf028,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_usb30_mock_utmi_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "usb30_mock_utmi_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] =3D {
>> + F(1200000, P_XO, 16, 0, 0),
>> + F(19200000, P_XO, 1, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 usb3_phy_aux_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x5000c,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_sleep_clk,
>> + =2Efreq_tbl =3D ftbl_usb3_phy_aux_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "usb3_phy_aux_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_sleep_clk,
>> + =2Enum_parents =3D 2,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_aggre2_ufs_axi_clk =3D {
>> + =2Eha
--=20
Sent from my Android device with K-9 Mail=2E Please excuse my brevity=2E
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] clk: qcom: Add Global Clock controller (GCC) driver for SDM660
2018-08-13 6:55 ` [PATCH] clk: qcom: Add Global Clock controller (GCC) driver for SDM660 Taniya Das
2018-08-13 7:45 ` Craig Tatlor
@ 2018-08-13 9:44 ` Craig Tatlor
1 sibling, 0 replies; 18+ messages in thread
From: Craig Tatlor @ 2018-08-13 9:44 UTC (permalink / raw)
To: Taniya Das
Cc: linux-arm-msm, Michael Turquette, Stephen Boyd, Rob Herring,
Mark Rutland, Andy Gross, David Brown, linux-clk, devicetree,
linux-kernel, linux-soc
On 13 August 2018 07:55:34 BST, Taniya Das <tdas@codeaurora=2Eorg> wrote:
>Hello Craig,
>
>Could you please correct the authorship and also provide the reference=20
>to code where this is picked from?
>
Also, don't you have a program that just spits out the clock setup?
And I did leave copyright in file=2E
>On 8/11/2018 1:51 AM, Craig Tatlor wrote:
>> Add support for the global clock controller found on SDM660
>> based devices=2E This should allow most non-multimedia device
>> drivers to probe and control their clocks=2E
>> Based on CAF implementation=2E
>>=20
>> Signed-off-by: Craig Tatlor <ctatlor97@gmail=2Ecom>
>> ---
>> =2E=2E=2E/devicetree/bindings/clock/qcom,gcc=2Etxt | 1 +
>> drivers/clk/qcom/Kconfig | 9 +
>> drivers/clk/qcom/Makefile | 1 +
>> drivers/clk/qcom/gcc-sdm660=2Ec | 2479
>+++++++++++++++++
>> include/dt-bindings/clock/qcom,gcc-sdm660=2Eh | 159 ++
>> 5 files changed, 2649 insertions(+)
>> create mode 100644 drivers/clk/qcom/gcc-sdm660=2Ec
>> create mode 100644 include/dt-bindings/clock/qcom,gcc-sdm660=2Eh
>>=20
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc=2Etxt
>b/Documentation/devicetree/bindings/clock/qcom,gcc=2Etxt
>> index 664ea1fd6c76=2E=2Ee498ad2e8db8 100644
>> --- a/Documentation/devicetree/bindings/clock/qcom,gcc=2Etxt
>> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc=2Etxt
>> @@ -19,6 +19,7 @@ Required properties :
>> "qcom,gcc-msm8996"
>> "qcom,gcc-msm8998"
>> "qcom,gcc-mdm9615"
>> + "qcom,gcc-sdm660"
>> "qcom,gcc-sdm845"
>> =20
>> - reg : shall contain base register location and length
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index 9c3480dcc38a=2E=2Ec4bda6d24c1f 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -226,6 +226,15 @@ config MSM_GCC_8998
>> Say Y if you want to use peripheral devices such as UART, SPI,
>> i2c, USB, UFS, SD/eMMC, PCIe, etc=2E
>> =20
>> +config SDM_GCC_660
>> + tristate "SDM660 Global Clock Controller"
>> + select QCOM_GDSC
>> + depends on COMMON_CLK_QCOM
>> + help
>> + Support for the global clock controller on SDM660 devices=2E
>> + Say Y if you want to use peripheral devices such as UART, SPI,
>> + i2C, USB, UFS, SDDC, PCIe, etc=2E
>> +
>> config SDM_GCC_845
>> tristate "SDM845 Global Clock Controller"
>> select QCOM_GDSC
>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>> index 762c01137c2f=2E=2E6e37d30d7c02 100644
>> --- a/drivers/clk/qcom/Makefile
>> +++ b/drivers/clk/qcom/Makefile
>> @@ -38,6 +38,7 @@ obj-$(CONFIG_QCOM_A53PLL) +=3D a53-pll=2Eo
>> obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) +=3D apcs-msm8916=2Eo
>> obj-$(CONFIG_QCOM_CLK_RPM) +=3D clk-rpm=2Eo
>> obj-$(CONFIG_QCOM_CLK_SMD_RPM) +=3D clk-smd-rpm=2Eo
>> +obj-$(CONFIG_SDM_GCC_660) +=3D gcc-sdm660=2Eo
>> obj-$(CONFIG_SDM_GCC_845) +=3D gcc-sdm845=2Eo
>> obj-$(CONFIG_SDM_VIDEOCC_845) +=3D videocc-sdm845=2Eo
>> obj-$(CONFIG_SPMI_PMIC_CLKDIV) +=3D clk-spmi-pmic-div=2Eo
>> diff --git a/drivers/clk/qcom/gcc-sdm660=2Ec
>b/drivers/clk/qcom/gcc-sdm660=2Ec
>> new file mode 100644
>> index 000000000000=2E=2Ebdb445aa4baa
>> --- /dev/null
>> +++ b/drivers/clk/qcom/gcc-sdm660=2Ec
>> @@ -0,0 +1,2479 @@
>> +// SPDX-License-Identifier: GPL-2=2E0
>> +/*
>> + * Copyright (c) 2016-2017, The Linux Foundation=2E All rights
>reserved=2E
>> + * Copyright (c) 2018, Craig Tatlor=2E
>> + */
>> +
>> +#include <linux/kernel=2Eh>
>> +#include <linux/bitops=2Eh>
>> +#include <linux/err=2Eh>
>> +#include <linux/platform_device=2Eh>
>> +#include <linux/module=2Eh>
>> +#include <linux/of=2Eh>
>> +#include <linux/of_device=2Eh>
>> +#include <linux/clk-provider=2Eh>
>> +#include <linux/regmap=2Eh>
>> +#include <linux/reset-controller=2Eh>
>> +
>> +#include <dt-bindings/clock/qcom,gcc-sdm660=2Eh>
>> +
>> +#include "common=2Eh"
>> +#include "clk-regmap=2Eh"
>> +#include "clk-alpha-pll=2Eh"
>> +#include "clk-rcg=2Eh"
>> +#include "clk-branch=2Eh"
>> +#include "reset=2Eh"
>> +#include "gdsc=2Eh"
>> +
>> +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
>> +
>> +enum {
>> + P_XO,
>> + P_SLEEP_CLK,
>> + P_GPLL0,
>> + P_GPLL1,
>> + P_GPLL4,
>> + P_GPLL0_EARLY_DIV,
>> + P_GPLL1_EARLY_DIV,
>> +};
>> +
>> +static const struct parent_map
>gcc_parent_map_xo_gpll0_gpll0_early_div[] =3D {
>> + { P_XO, 0 },
>> + { P_GPLL0, 1 },
>> + { P_GPLL0_EARLY_DIV, 6 },
>> +};
>> +
>> +static const char * const
>gcc_parent_names_xo_gpll0_gpll0_early_div[] =3D {
>> + "xo",
>> + "gpll0",
>> + "gpll0_early_div",
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_xo_gpll0[] =3D {
>> + { P_XO, 0 },
>> + { P_GPLL0, 1 },
>> +};
>> +
>> +static const char * const gcc_parent_names_xo_gpll0[] =3D {
>> + "xo",
>> + "gpll0",
>> +};
>> +
>> +static const struct parent_map
>gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] =3D {
>> + { P_XO, 0 },
>> + { P_GPLL0, 1 },
>> + { P_SLEEP_CLK, 5 },
>> + { P_GPLL0_EARLY_DIV, 6 },
>> +};
>> +
>> +static const char * const
>gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div[] =3D {
>> + "xo",
>> + "gpll0",
>> + "sleep_clk",
>> + "gpll0_early_div",
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_xo_sleep_clk[] =3D {
>> + { P_XO, 0 },
>> + { P_SLEEP_CLK, 5 },
>> +};
>> +
>> +static const char * const gcc_parent_names_xo_sleep_clk[] =3D {
>> + "xo",
>> + "sleep_clk",
>> +};
>> +
>> +static const struct parent_map gcc_parent_map_xo_gpll4[] =3D {
>> + { P_XO, 0 },
>> + { P_GPLL4, 5 },
>> +};
>> +
>> +static const char * const gcc_parent_names_xo_gpll4[] =3D {
>> + "xo",
>> + "gpll4",
>> +};
>> +
>> +static const struct parent_map
>gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] =3D
>{
>> + { P_XO, 0 },
>> + { P_GPLL0, 1 },
>> + { P_GPLL0_EARLY_DIV, 3 },
>> + { P_GPLL1, 4 },
>> + { P_GPLL4, 5 },
>> + { P_GPLL1_EARLY_DIV, 6 },
>> +};
>> +
>> +static const char * const
>gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[]
>=3D {
>> + "xo",
>> + "gpll0",
>> + "gpll0_early_div",
>> + "gpll1",
>> + "gpll4",
>> + "gpll1_early_div",
>> +};
>> +
>> +static const struct parent_map
>gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] =3D {
>> + { P_XO, 0 },
>> + { P_GPLL0, 1 },
>> + { P_GPLL4, 5 },
>> + { P_GPLL0_EARLY_DIV, 6 },
>> +};
>> +
>> +static const char * const
>gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div[] =3D {
>> + "xo",
>> + "gpll0",
>> + "gpll4",
>> + "gpll0_early_div",
>> +};
>> +
>> +static const struct parent_map
>gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] =3D {
>> + { P_XO, 0 },
>> + { P_GPLL0, 1 },
>> + { P_GPLL0_EARLY_DIV, 2 },
>> + { P_GPLL4, 5 },
>> +};
>> +
>> +static const char * const
>gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4[] =3D {
>> + "xo",
>> + "gpll0",
>> + "gpll0_early_div",
>> + "gpll4",
>> +};
>> +
>> +static struct clk_fixed_factor xo =3D {
>> + =2Emult =3D 1,
>> + =2Ediv =3D 1,
>> + =2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "xo",
>> + =2Eparent_names =3D (const char *[]){ "xo_board" },
>> + =2Enum_parents =3D 1,
>> + =2Eops =3D &clk_fixed_factor_ops,
>> + },
>> +};
>> +
>> +static struct clk_alpha_pll gpll0_early =3D {
>> + =2Eoffset =3D 0x0,
>> + =2Eregs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> + =2Eclkr =3D {
>> + =2Eenable_reg =3D 0x52000,
>> + =2Eenable_mask =3D BIT(0),
>> + =2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "gpll0_early",
>> + =2Eparent_names =3D (const char *[]){ "xo" },
>> + =2Enum_parents =3D 1,
>> + =2Eops =3D &clk_alpha_pll_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor gpll0_early_div =3D {
>> + =2Emult =3D 1,
>> + =2Ediv =3D 2,
>> + =2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "gpll0_early_div",
>> + =2Eparent_names =3D (const char *[]){ "gpll0_early" },
>> + =2Enum_parents =3D 1,
>> + =2Eops =3D &clk_fixed_factor_ops,
>> + },
>> +};
>> +
>> +static struct clk_alpha_pll_postdiv gpll0 =3D {
>> + =2Eoffset =3D 0x00000,
>> + =2Eregs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "gpll0",
>> + =2Eparent_names =3D (const char *[]){ "gpll0_early" },
>> + =2Enum_parents =3D 1,
>> + =2Eops =3D &clk_alpha_pll_postdiv_ops,
>> + },
>> +};
>> +
>> +static struct clk_alpha_pll gpll1_early =3D {
>> + =2Eoffset =3D 0x1000,
>> + =2Eregs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> + =2Eclkr =3D {
>> + =2Eenable_reg =3D 0x52000,
>> + =2Eenable_mask =3D BIT(1),
>> + =2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "gpll1_early",
>> + =2Eparent_names =3D (const char *[]){ "xo" },
>> + =2Enum_parents =3D 1,
>> + =2Eops =3D &clk_alpha_pll_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor gpll1_early_div =3D {
>> + =2Emult =3D 1,
>> + =2Ediv =3D 2,
>> + =2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "gpll1_early_div",
>> + =2Eparent_names =3D (const char *[]){ "gpll1_early" },
>> + =2Enum_parents =3D 1,
>> + =2Eops =3D &clk_fixed_factor_ops,
>> + },
>> +};
>> +
>> +static struct clk_alpha_pll_postdiv gpll1 =3D {
>> + =2Eoffset =3D 0x1000,
>> + =2Eregs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "gpll1",
>> + =2Eparent_names =3D (const char *[]){ "gpll1_early" },
>> + =2Enum_parents =3D 1,
>> + =2Eops =3D &clk_alpha_pll_postdiv_ops,
>> + },
>> +};
>> +
>> +static struct clk_alpha_pll gpll4_early =3D {
>> + =2Eoffset =3D 0x77000,
>> + =2Eregs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> + =2Eclkr =3D {
>> + =2Eenable_reg =3D 0x52000,
>> + =2Eenable_mask =3D BIT(4),
>> + =2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "gpll4_early",
>> + =2Eparent_names =3D (const char *[]){ "xo" },
>> + =2Enum_parents =3D 1,
>> + =2Eops =3D &clk_alpha_pll_ops,
>> + },
>> + },
>> +};
>> +
>> +static struct clk_alpha_pll_postdiv gpll4 =3D {
>> + =2Eoffset =3D 0x77000,
>> + =2Eregs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data)
>> + {
>> + =2Ename =3D "gpll4",
>> + =2Eparent_names =3D (const char *[]) { "gpll4_early" },
>> + =2Enum_parents =3D 1,
>> + =2Eops =3D &clk_alpha_pll_postdiv_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] =3D {
>> + F(19200000, P_XO, 1, 0, 0),
>> + F(50000000, P_GPLL0, 12, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x19020,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_i2c_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp1_qup1_i2c_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] =3D {
>> + F(960000, P_XO, 10, 1, 2),
>> + F(4800000, P_XO, 4, 0, 0),
>> + F(9600000, P_XO, 2, 0, 0),
>> + F(15000000, P_GPLL0, 10, 1, 4),
>> + F(19200000, P_XO, 1, 0, 0),
>> + F(25000000, P_GPLL0, 12, 1, 2),
>> + F(50000000, P_GPLL0, 12, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x1900c,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_spi_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp1_qup1_spi_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x1b020,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_i2c_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp1_qup2_i2c_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x1b00c,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_spi_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp1_qup2_spi_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x1d020,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_i2c_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp1_qup3_i2c_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x1d00c,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_spi_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp1_qup3_spi_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x1f020,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_i2c_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp1_qup4_i2c_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x1f00c,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_spi_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp1_qup4_spi_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] =3D {
>> + F(3686400, P_GPLL0, 1, 96, 15625),
>> + F(7372800, P_GPLL0, 1, 192, 15625),
>> + F(14745600, P_GPLL0, 1, 384, 15625),
>> + F(16000000, P_GPLL0, 5, 2, 15),
>> + F(19200000, P_XO, 1, 0, 0),
>> + F(24000000, P_GPLL0, 5, 1, 5),
>> + F(32000000, P_GPLL0, 1, 4, 75),
>> + F(40000000, P_GPLL0, 15, 0, 0),
>> + F(46400000, P_GPLL0, 1, 29, 375),
>> + F(48000000, P_GPLL0, 12=2E5, 0, 0),
>> + F(51200000, P_GPLL0, 1, 32, 375),
>> + F(56000000, P_GPLL0, 1, 7, 75),
>> + F(58982400, P_GPLL0, 1, 1536, 15625),
>> + F(60000000, P_GPLL0, 10, 0, 0),
>> + F(63157895, P_GPLL0, 9=2E5, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 blsp1_uart1_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x1a00c,
>> + =2Emnd_width =3D 16,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_uart1_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp1_uart1_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp1_uart2_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x1c00c,
>> + =2Emnd_width =3D 16,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_uart1_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp1_uart2_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x26020,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_i2c_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp2_qup1_i2c_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x2600c,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_spi_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp2_qup1_spi_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x28020,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_i2c_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp2_qup2_i2c_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x2800c,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_spi_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp2_qup2_spi_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x2a020,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_i2c_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp2_qup3_i2c_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x2a00c,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_spi_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp2_qup3_spi_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x2c020,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_i2c_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp2_qup4_i2c_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x2c00c,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_qup1_spi_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp2_qup4_spi_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp2_uart1_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x2700c,
>> + =2Emnd_width =3D 16,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_uart1_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp2_uart1_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 blsp2_uart2_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x2900c,
>> + =2Emnd_width =3D 16,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_blsp1_uart1_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "blsp2_uart2_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_gp1_clk_src[] =3D {
>> + F(19200000, P_XO, 1, 0, 0),
>> + F(100000000, P_GPLL0, 6, 0, 0),
>> + F(200000000, P_GPLL0, 3, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 gp1_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x64004,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_gp1_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "gp1_clk_src",
>> + =2Eparent_names =3D
>gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
>> + =2Enum_parents =3D 4,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 gp2_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x65004,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_gp1_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "gp2_clk_src",
>> + =2Eparent_names =3D
>gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
>> + =2Enum_parents =3D 4,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 gp3_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x66004,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_gp1_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "gp3_clk_src",
>> + =2Eparent_names =3D
>gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
>> + =2Enum_parents =3D 4,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] =3D {
>> + F(300000000, P_GPLL0, 2, 0, 0),
>> + F(600000000, P_GPLL0, 1, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 hmss_gpll0_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x4805c,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_hmss_gpll0_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "hmss_gpll0_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_hmss_gpll4_clk_src[] =3D {
>> + F(384000000, P_GPLL4, 4, 0, 0),
>> + F(768000000, P_GPLL4, 2, 0, 0),
>> + F(1536000000, P_GPLL4, 1, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 hmss_gpll4_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x48074,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll4,
>> + =2Efreq_tbl =3D ftbl_hmss_gpll4_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "hmss_gpll4_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll4,
>> + =2Enum_parents =3D 2,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] =3D {
>> + F(19200000, P_XO, 1, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 hmss_rbcpr_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x48044,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_hmss_rbcpr_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "hmss_rbcpr_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0,
>> + =2Enum_parents =3D 2,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_pdm2_clk_src[] =3D {
>> + F(60000000, P_GPLL0, 10, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 pdm2_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x33010,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_pdm2_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "pdm2_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_qspi_ser_clk_src[] =3D {
>> + F(19200000, P_XO, 1, 0, 0),
>> + F(80200000, P_GPLL1_EARLY_DIV, 5, 0, 0),
>> + F(160400000, P_GPLL1, 5, 0, 0),
>> + F(267333333, P_GPLL1, 3, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 qspi_ser_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x4d00c,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D
>gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
>> + =2Efreq_tbl =3D ftbl_qspi_ser_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "qspi_ser_clk_src",
>> + =2Eparent_names =3D
>gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
>> + =2Enum_parents =3D 6,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] =3D {
>> + F(144000, P_XO, 16, 3, 25),
>> + F(400000, P_XO, 12, 1, 4),
>> + F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
>> + F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
>> + F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
>> + F(100000000, P_GPLL0, 6, 0, 0),
>> + F(192000000, P_GPLL4, 8, 0, 0),
>> + F(384000000, P_GPLL4, 4, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 sdcc1_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x1602c,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_sdcc1_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "sdcc1_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div,
>> + =2Enum_parents =3D 4,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] =3D {
>> + F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
>> + F(150000000, P_GPLL0, 4, 0, 0),
>> + F(200000000, P_GPLL0, 3, 0, 0),
>> + F(300000000, P_GPLL0, 2, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 sdcc1_ice_core_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x16010,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_sdcc1_ice_core_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "sdcc1_ice_core_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] =3D {
>> + F(144000, P_XO, 16, 3, 25),
>> + F(400000, P_XO, 12, 1, 4),
>> + F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
>> + F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
>> + F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
>> + F(100000000, P_GPLL0, 6, 0, 0),
>> + F(192000000, P_GPLL4, 8, 0, 0),
>> + F(200000000, P_GPLL0, 3, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 sdcc2_apps_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x14010,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4,
>> + =2Efreq_tbl =3D ftbl_sdcc2_apps_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "sdcc2_apps_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4,
>> + =2Enum_parents =3D 4,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_ufs_axi_clk_src[] =3D {
>> + F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
>> + F(100000000, P_GPLL0, 6, 0, 0),
>> + F(150000000, P_GPLL0, 4, 0, 0),
>> + F(200000000, P_GPLL0, 3, 0, 0),
>> + F(240000000, P_GPLL0, 2=2E5, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 ufs_axi_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x75018,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_ufs_axi_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "ufs_axi_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] =3D {
>> + F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
>> + F(150000000, P_GPLL0, 4, 0, 0),
>> + F(300000000, P_GPLL0, 2, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 ufs_ice_core_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x76010,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_ufs_ice_core_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "ufs_ice_core_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_rcg2 ufs_phy_aux_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x76044,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_sleep_clk,
>> + =2Efreq_tbl =3D ftbl_hmss_rbcpr_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "ufs_phy_aux_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_sleep_clk,
>> + =2Enum_parents =3D 2,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] =3D {
>> + F(37500000, P_GPLL0_EARLY_DIV, 8, 0, 0),
>> + F(75000000, P_GPLL0, 8, 0, 0),
>> + F(150000000, P_GPLL0, 4, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 ufs_unipro_core_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x76028,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_ufs_unipro_core_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "ufs_unipro_core_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_usb20_master_clk_src[] =3D {
>> + F(19200000, P_XO, 1, 0, 0),
>> + F(60000000, P_GPLL0, 10, 0, 0),
>> + F(120000000, P_GPLL0, 5, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 usb20_master_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x2f010,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_usb20_master_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "usb20_master_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_usb20_mock_utmi_clk_src[] =3D {
>> + F(19200000, P_XO, 1, 0, 0),
>> + F(60000000, P_GPLL0, 10, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 usb20_mock_utmi_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x2f024,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_usb20_mock_utmi_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "usb20_mock_utmi_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_usb30_master_clk_src[] =3D {
>> + F(19200000, P_XO, 1, 0, 0),
>> + F(66666667, P_GPLL0_EARLY_DIV, 4=2E5, 0, 0),
>> + F(120000000, P_GPLL0, 5, 0, 0),
>> + F(133333333, P_GPLL0, 4=2E5, 0, 0),
>> + F(150000000, P_GPLL0, 4, 0, 0),
>> + F(200000000, P_GPLL0, 3, 0, 0),
>> + F(240000000, P_GPLL0, 2=2E5, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 usb30_master_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0xf014,
>> + =2Emnd_width =3D 8,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_usb30_master_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "usb30_master_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] =3D {
>> + F(19200000, P_XO, 1, 0, 0),
>> + F(40000000, P_GPLL0_EARLY_DIV, 7=2E5, 0, 0),
>> + F(60000000, P_GPLL0, 10, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 usb30_mock_utmi_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0xf028,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_gpll0_gpll0_early_div,
>> + =2Efreq_tbl =3D ftbl_usb30_mock_utmi_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "usb30_mock_utmi_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_gpll0_gpll0_early_div,
>> + =2Enum_parents =3D 3,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] =3D {
>> + F(1200000, P_XO, 16, 0, 0),
>> + F(19200000, P_XO, 1, 0, 0),
>> + { }
>> +};
>> +
>> +static struct clk_rcg2 usb3_phy_aux_clk_src =3D {
>> + =2Ecmd_rcgr =3D 0x5000c,
>> + =2Emnd_width =3D 0,
>> + =2Ehid_width =3D 5,
>> + =2Eparent_map =3D gcc_parent_map_xo_sleep_clk,
>> + =2Efreq_tbl =3D ftbl_usb3_phy_aux_clk_src,
>> + =2Eclkr=2Ehw=2Einit =3D &(struct clk_init_data){
>> + =2Ename =3D "usb3_phy_aux_clk_src",
>> + =2Eparent_names =3D gcc_parent_names_xo_sleep_clk,
>> + =2Enum_parents =3D 2,
>> + =2Eops =3D &clk_rcg2_ops,
>> + },
>> +};
>> +
>> +static struct clk_branch gcc_aggre2_ufs_axi_clk =3D {
>> + =2Eha
--=20
Sent from my Android device with K-9 Mail=2E Please excuse my brevity=2E
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] clk: qcom: Add Global Clock controller (GCC) driver for SDM660
2018-08-13 7:45 ` Craig Tatlor
@ 2018-09-24 12:44 ` Heiko Stuebner
2018-09-24 12:44 ` Heiko Stuebner
2018-09-24 14:33 ` Craig
0 siblings, 2 replies; 18+ messages in thread
From: Heiko Stuebner @ 2018-09-24 12:44 UTC (permalink / raw)
To: Craig Tatlor
Cc: Taniya Das, linux-arm-msm, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Andy Gross, David Brown, linux-clk,
devicetree, linux-kernel, linux-soc
Hi Craig,
Am Montag, 13. August 2018, 09:45:09 CEST schrieb Craig Tatlor:
> On 13 August 2018 07:55:34 BST, Taniya Das <tdas@codeaurora.org> wrote:
> >Hello Craig,
> >
> >Could you please correct the authorship and also provide the reference
> >to code where this is picked from?
> Okay,
> Got code from here https://github.com/sonyxperiadev/kernel/blob/aosp/LA.UM.6.4.r1/drivers/clk/qcom/gcc-sdm660.c
> but changed it quite a bit for upstream,
> Should I change the commit author and add your signed off by and say I did cleanups on my signed off by.
yep, for something this huge it is really the correct way to keep the
original authorship intact as Taniya did the initial big work, and just
add you change-description, so something like
---- 8< ------
Add support for the global clock controller found on SDM660
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Based on CAF implementation.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
[ description of changes ... often seen in these brackets ]
Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
---- 8< ------
Also, do you plan to continue working on this, as I would be interessted
in the clock driver for a sdm660-based phone as well.
Thanks
Heiko
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] clk: qcom: Add Global Clock controller (GCC) driver for SDM660
2018-09-24 12:44 ` Heiko Stuebner
@ 2018-09-24 12:44 ` Heiko Stuebner
2018-09-24 14:33 ` Craig
1 sibling, 0 replies; 18+ messages in thread
From: Heiko Stuebner @ 2018-09-24 12:44 UTC (permalink / raw)
To: Craig Tatlor
Cc: Taniya Das, linux-arm-msm, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Andy Gross, David Brown, linux-clk,
devicetree, linux-kernel, linux-soc
Hi Craig,
Am Montag, 13. August 2018, 09:45:09 CEST schrieb Craig Tatlor:
> On 13 August 2018 07:55:34 BST, Taniya Das <tdas@codeaurora.org> wrote:
> >Hello Craig,
> >
> >Could you please correct the authorship and also provide the reference
> >to code where this is picked from?
> Okay,
> Got code from here https://github.com/sonyxperiadev/kernel/blob/aosp/LA.UM.6.4.r1/drivers/clk/qcom/gcc-sdm660.c
> but changed it quite a bit for upstream,
> Should I change the commit author and add your signed off by and say I did cleanups on my signed off by.
yep, for something this huge it is really the correct way to keep the
original authorship intact as Taniya did the initial big work, and just
add you change-description, so something like
---- 8< ------
Add support for the global clock controller found on SDM660
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Based on CAF implementation.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
[ description of changes ... often seen in these brackets ]
Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
---- 8< ------
Also, do you plan to continue working on this, as I would be interessted
in the clock driver for a sdm660-based phone as well.
Thanks
Heiko
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] clk: qcom: Add Global Clock controller (GCC) driver for SDM660
2018-09-24 12:44 ` Heiko Stuebner
2018-09-24 12:44 ` Heiko Stuebner
@ 2018-09-24 14:33 ` Craig
2018-09-24 14:33 ` Craig
1 sibling, 1 reply; 18+ messages in thread
From: Craig @ 2018-09-24 14:33 UTC (permalink / raw)
To: Heiko Stuebner
Cc: Taniya Das, linux-arm-msm, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Andy Gross, David Brown, linux-clk,
devicetree, linux-kernel, linux-soc
On 24 September 2018 13:44:33 BST, Heiko Stuebner <heiko@sntech=2Ede> wrot=
e:
>Hi Craig,
>
>Am Montag, 13=2E August 2018, 09:45:09 CEST schrieb Craig Tatlor:
>> On 13 August 2018 07:55:34 BST, Taniya Das <tdas@codeaurora=2Eorg>
>wrote:
>> >Hello Craig,
>> >
>> >Could you please correct the authorship and also provide the
>reference=20
>> >to code where this is picked from?
>> Okay,=20
>> Got code from here
>https://github=2Ecom/sonyxperiadev/kernel/blob/aosp/LA=2EUM=2E6=2E4=2Er1/=
drivers/clk/qcom/gcc-sdm660=2Ec
>> but changed it quite a bit for upstream,
>> Should I change the commit author and add your signed off by and say
>I did cleanups on my signed off by=2E
>
>yep, for something this huge it is really the correct way to keep the
>original authorship intact as Taniya did the initial big work, and just
>add you change-description, so something like
>
>---- 8< ------
>Add support for the global clock controller found on SDM660
>based devices=2E This should allow most non-multimedia device
>drivers to probe and control their clocks=2E
>Based on CAF implementation=2E
>
>Signed-off-by: Taniya Das <tdas@codeaurora=2Eorg>
>[ description of changes =2E=2E=2E often seen in these brackets ]
>Signed-off-by: Craig Tatlor <ctatlor97@gmail=2Ecom>
>---- 8< ------
>
Sure, will do, though I'm sure qcom have a program to generate the drivers=
:)
>Also, do you plan to continue working on this, as I would be
>interessted
>in the clock driver for a sdm660-based phone as well
Yup, was really just waiting for reply to this question,
>
>
>Thanks
>Heiko
--=20
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH] clk: qcom: Add Global Clock controller (GCC) driver for SDM660
2018-09-24 14:33 ` Craig
@ 2018-09-24 14:33 ` Craig
0 siblings, 0 replies; 18+ messages in thread
From: Craig @ 2018-09-24 14:33 UTC (permalink / raw)
To: Heiko Stuebner
Cc: Taniya Das, linux-arm-msm, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Andy Gross, David Brown, linux-clk,
devicetree, linux-kernel, linux-soc
On 24 September 2018 13:44:33 BST, Heiko Stuebner <heiko@sntech.de> wrote:
>Hi Craig,
>
>Am Montag, 13. August 2018, 09:45:09 CEST schrieb Craig Tatlor:
>> On 13 August 2018 07:55:34 BST, Taniya Das <tdas@codeaurora.org>
>wrote:
>> >Hello Craig,
>> >
>> >Could you please correct the authorship and also provide the
>reference
>> >to code where this is picked from?
>> Okay,
>> Got code from here
>https://github.com/sonyxperiadev/kernel/blob/aosp/LA.UM.6.4.r1/drivers/clk/qcom/gcc-sdm660.c
>> but changed it quite a bit for upstream,
>> Should I change the commit author and add your signed off by and say
>I did cleanups on my signed off by.
>
>yep, for something this huge it is really the correct way to keep the
>original authorship intact as Taniya did the initial big work, and just
>add you change-description, so something like
>
>---- 8< ------
>Add support for the global clock controller found on SDM660
>based devices. This should allow most non-multimedia device
>drivers to probe and control their clocks.
>Based on CAF implementation.
>
>Signed-off-by: Taniya Das <tdas@codeaurora.org>
>[ description of changes ... often seen in these brackets ]
>Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
>---- 8< ------
>
Sure, will do, though I'm sure qcom have a program to generate the drivers :)
>Also, do you plan to continue working on this, as I would be
>interessted
>in the clock driver for a sdm660-based phone as well
Yup, was really just waiting for reply to this question,
>
>
>Thanks
>Heiko
--
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v2] clk: qcom: Add Global Clock controller (GCC) driver for SDM660
2018-08-10 20:21 ` [PATCH] clk: qcom: Add Global Clock controller (GCC) driver for SDM660 Craig Tatlor
` (2 preceding siblings ...)
2018-08-13 6:55 ` [PATCH] clk: qcom: Add Global Clock controller (GCC) driver for SDM660 Taniya Das
@ 2018-09-25 16:35 ` Craig Tatlor
2018-09-25 16:35 ` Craig Tatlor
2018-09-25 17:35 ` [PATCH v3] " Craig Tatlor
4 siblings, 1 reply; 18+ messages in thread
From: Craig Tatlor @ 2018-09-25 16:35 UTC (permalink / raw)
Cc: ctatlor97, linux-arm-msm, Taniya Das, Michael Turquette,
Stephen Boyd, Rob Herring, Mark Rutland, Andy Gross, David Brown,
linux-clk, devicetree, linux-kernel, linux-soc
From: Taniya Das <tdas@codeaurora.org>
Add support for the global clock controller found on SDM660
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Based on CAF implementation.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
[craig: rename parents to fit upstream, and other cleanups]
Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
---
.../devicetree/bindings/clock/qcom,gcc.txt | 1 +
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-sdm660.c | 2479 +++++++++++++++++
include/dt-bindings/clock/qcom,gcc-sdm660.h | 159 ++
5 files changed, 2649 insertions(+)
create mode 100644 drivers/clk/qcom/gcc-sdm660.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-sdm660.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 664ea1fd6c76..e498ad2e8db8 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -19,6 +19,7 @@ Required properties :
"qcom,gcc-msm8996"
"qcom,gcc-msm8998"
"qcom,gcc-mdm9615"
+ "qcom,gcc-sdm660"
"qcom,gcc-sdm845"
- reg : shall contain base register location and length
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 5b181b182f40..4d478b261dfe 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -243,6 +243,15 @@ config SDM_CAMCC_845
Support for the camera clock controller on SDM845 devices.
Say Y if you want to support camera devices and camera functionality.
+config SDM_GCC_660
+ tristate "SDM660 Global Clock Controller"
+ select QCOM_GDSC
+ depends on COMMON_CLK_QCOM
+ help
+ Support for the global clock controller on SDM660 devices.
+ Say Y if you want to use peripheral devices such as UART, SPI,
+ i2C, USB, UFS, SDDC, PCIe, etc.
+
config SDM_GCC_845
tristate "SDM845 Global Clock Controller"
select QCOM_GDSC
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 935f142bc155..ab892f6d847c 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o
obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o
obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
+obj-$(CONFIG_SDM_GCC_660) += gcc-sdm660.o
obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
new file mode 100644
index 000000000000..cec8b4145b71
--- /dev/null
+++ b/drivers/clk/qcom/gcc-sdm660.c
@@ -0,0 +1,2479 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018, Craig Tatlor.
+ */
+
+#include <linux/kernel.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/clock/qcom,gcc-sdm660.h>
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-alpha-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "reset.h"
+#include "gdsc.h"
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+enum {
+ P_XO,
+ P_SLEEP_CLK,
+ P_GPLL0,
+ P_GPLL1,
+ P_GPLL4,
+ P_GPLL0_EARLY_DIV,
+ P_GPLL1_EARLY_DIV,
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_EARLY_DIV, 6 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div[] = {
+ "xo",
+ "gpll0",
+ "gpll0_early_div",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0[] = {
+ "xo",
+ "gpll0",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_SLEEP_CLK, 5 },
+ { P_GPLL0_EARLY_DIV, 6 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div[] = {
+ "xo",
+ "gpll0",
+ "sleep_clk",
+ "gpll0_early_div",
+};
+
+static const struct parent_map gcc_parent_map_xo_sleep_clk[] = {
+ { P_XO, 0 },
+ { P_SLEEP_CLK, 5 },
+};
+
+static const char * const gcc_parent_names_xo_sleep_clk[] = {
+ "xo",
+ "sleep_clk",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll4[] = {
+ { P_XO, 0 },
+ { P_GPLL4, 5 },
+};
+
+static const char * const gcc_parent_names_xo_gpll4[] = {
+ "xo",
+ "gpll4",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_EARLY_DIV, 3 },
+ { P_GPLL1, 4 },
+ { P_GPLL4, 5 },
+ { P_GPLL1_EARLY_DIV, 6 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
+ "xo",
+ "gpll0",
+ "gpll0_early_div",
+ "gpll1",
+ "gpll4",
+ "gpll1_early_div",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL4, 5 },
+ { P_GPLL0_EARLY_DIV, 6 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div[] = {
+ "xo",
+ "gpll0",
+ "gpll4",
+ "gpll0_early_div",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_EARLY_DIV, 2 },
+ { P_GPLL4, 5 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4[] = {
+ "xo",
+ "gpll0",
+ "gpll0_early_div",
+ "gpll4",
+};
+
+static struct clk_fixed_factor xo = {
+ .mult = 1,
+ .div = 1,
+ .hw.init = &(struct clk_init_data){
+ .name = "xo",
+ .parent_names = (const char *[]){ "xo_board" },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll0_early = {
+ .offset = 0x0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_early",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor gpll0_early_div = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_early_div",
+ .parent_names = (const char *[]){ "gpll0_early" },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll0 = {
+ .offset = 0x00000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll0",
+ .parent_names = (const char *[]){ "gpll0_early" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll1_early = {
+ .offset = 0x1000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll1_early",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor gpll1_early_div = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll1_early_div",
+ .parent_names = (const char *[]){ "gpll1_early" },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll1 = {
+ .offset = 0x1000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll1",
+ .parent_names = (const char *[]){ "gpll1_early" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll4_early = {
+ .offset = 0x77000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll4_early",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll4 = {
+ .offset = 0x77000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "gpll4",
+ .parent_names = (const char *[]) { "gpll4_early" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(50000000, P_GPLL0, 12, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x19020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup1_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(50000000, P_GPLL0, 12, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
+ .cmd_rcgr = 0x1900c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup1_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x1b020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup2_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
+ .cmd_rcgr = 0x1b00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup2_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x1d020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup3_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
+ .cmd_rcgr = 0x1d00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup3_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x1f020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup4_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
+ .cmd_rcgr = 0x1f00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup4_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
+ F(3686400, P_GPLL0, 1, 96, 15625),
+ F(7372800, P_GPLL0, 1, 192, 15625),
+ F(14745600, P_GPLL0, 1, 384, 15625),
+ F(16000000, P_GPLL0, 5, 2, 15),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 5, 1, 5),
+ F(32000000, P_GPLL0, 1, 4, 75),
+ F(40000000, P_GPLL0, 15, 0, 0),
+ F(46400000, P_GPLL0, 1, 29, 375),
+ F(48000000, P_GPLL0, 12.5, 0, 0),
+ F(51200000, P_GPLL0, 1, 32, 375),
+ F(56000000, P_GPLL0, 1, 7, 75),
+ F(58982400, P_GPLL0, 1, 1536, 15625),
+ F(60000000, P_GPLL0, 10, 0, 0),
+ F(63157895, P_GPLL0, 9.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
+ .cmd_rcgr = 0x1a00c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart1_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
+ .cmd_rcgr = 0x1c00c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart2_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x26020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup1_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
+ .cmd_rcgr = 0x2600c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup1_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x28020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup2_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
+ .cmd_rcgr = 0x2800c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup2_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x2a020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup3_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
+ .cmd_rcgr = 0x2a00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup3_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x2c020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup4_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
+ .cmd_rcgr = 0x2c00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup4_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
+ .cmd_rcgr = 0x2700c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_uart1_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
+ .cmd_rcgr = 0x2900c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_uart2_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gp1_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gp1_clk_src = {
+ .cmd_rcgr = 0x64004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
+ .freq_tbl = ftbl_gp1_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp1_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gp2_clk_src = {
+ .cmd_rcgr = 0x65004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
+ .freq_tbl = ftbl_gp1_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp2_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gp3_clk_src = {
+ .cmd_rcgr = 0x66004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
+ .freq_tbl = ftbl_gp1_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp3_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] = {
+ F(300000000, P_GPLL0, 2, 0, 0),
+ F(600000000, P_GPLL0, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 hmss_gpll0_clk_src = {
+ .cmd_rcgr = 0x4805c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_hmss_gpll0_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "hmss_gpll0_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_hmss_gpll4_clk_src[] = {
+ F(384000000, P_GPLL4, 4, 0, 0),
+ F(768000000, P_GPLL4, 2, 0, 0),
+ F(1536000000, P_GPLL4, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 hmss_gpll4_clk_src = {
+ .cmd_rcgr = 0x48074,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll4,
+ .freq_tbl = ftbl_hmss_gpll4_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "hmss_gpll4_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll4,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 hmss_rbcpr_clk_src = {
+ .cmd_rcgr = 0x48044,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_hmss_rbcpr_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "hmss_rbcpr_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_pdm2_clk_src[] = {
+ F(60000000, P_GPLL0, 10, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 pdm2_clk_src = {
+ .cmd_rcgr = 0x33010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_pdm2_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pdm2_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(80200000, P_GPLL1_EARLY_DIV, 5, 0, 0),
+ F(160400000, P_GPLL1, 5, 0, 0),
+ F(267333333, P_GPLL1, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 qspi_ser_clk_src = {
+ .cmd_rcgr = 0x4d00c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
+ .freq_tbl = ftbl_qspi_ser_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "qspi_ser_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
+ .num_parents = 6,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
+ F(144000, P_XO, 16, 3, 25),
+ F(400000, P_XO, 12, 1, 4),
+ F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
+ F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
+ F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(192000000, P_GPLL4, 8, 0, 0),
+ F(384000000, P_GPLL4, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 sdcc1_apps_clk_src = {
+ .cmd_rcgr = 0x1602c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div,
+ .freq_tbl = ftbl_sdcc1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc1_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
+ F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ F(300000000, P_GPLL0, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 sdcc1_ice_core_clk_src = {
+ .cmd_rcgr = 0x16010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc1_ice_core_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
+ F(144000, P_XO, 16, 3, 25),
+ F(400000, P_XO, 12, 1, 4),
+ F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
+ F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
+ F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(192000000, P_GPLL4, 8, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 sdcc2_apps_clk_src = {
+ .cmd_rcgr = 0x14010,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4,
+ .freq_tbl = ftbl_sdcc2_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc2_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
+ F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ F(240000000, P_GPLL0, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ufs_axi_clk_src = {
+ .cmd_rcgr = 0x75018,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_ufs_axi_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ufs_axi_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
+ F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ F(300000000, P_GPLL0, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ufs_ice_core_clk_src = {
+ .cmd_rcgr = 0x76010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_ufs_ice_core_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ufs_ice_core_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 ufs_phy_aux_clk_src = {
+ .cmd_rcgr = 0x76044,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_sleep_clk,
+ .freq_tbl = ftbl_hmss_rbcpr_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ufs_phy_aux_clk_src",
+ .parent_names = gcc_parent_names_xo_sleep_clk,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = {
+ F(37500000, P_GPLL0_EARLY_DIV, 8, 0, 0),
+ F(75000000, P_GPLL0, 8, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ufs_unipro_core_clk_src = {
+ .cmd_rcgr = 0x76028,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_ufs_unipro_core_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ufs_unipro_core_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(60000000, P_GPLL0, 10, 0, 0),
+ F(120000000, P_GPLL0, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb20_master_clk_src = {
+ .cmd_rcgr = 0x2f010,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_usb20_master_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb20_master_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb20_mock_utmi_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(60000000, P_GPLL0, 10, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb20_mock_utmi_clk_src = {
+ .cmd_rcgr = 0x2f024,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_usb20_mock_utmi_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb20_mock_utmi_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(66666667, P_GPLL0_EARLY_DIV, 4.5, 0, 0),
+ F(120000000, P_GPLL0, 5, 0, 0),
+ F(133333333, P_GPLL0, 4.5, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ F(240000000, P_GPLL0, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb30_master_clk_src = {
+ .cmd_rcgr = 0xf014,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_usb30_master_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb30_master_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(40000000, P_GPLL0_EARLY_DIV, 7.5, 0, 0),
+ F(60000000, P_GPLL0, 10, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb30_mock_utmi_clk_src = {
+ .cmd_rcgr = 0xf028,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb30_mock_utmi_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
+ F(1200000, P_XO, 16, 0, 0),
+ F(19200000, P_XO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb3_phy_aux_clk_src = {
+ .cmd_rcgr = 0x5000c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_sleep_clk,
+ .freq_tbl = ftbl_usb3_phy_aux_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb3_phy_aux_clk_src",
+ .parent_names = gcc_parent_names_xo_sleep_clk,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_branch gcc_aggre2_ufs_axi_clk = {
+ .halt_reg = 0x75034,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x75034,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_aggre2_ufs_axi_clk",
+ .parent_names = (const char *[]){
+ "ufs_axi_clk_src",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_aggre2_usb3_axi_clk = {
+ .halt_reg = 0xf03c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf03c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_aggre2_usb3_axi_clk",
+ .parent_names = (const char *[]){
+ "usb30_master_clk_src",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_bimc_gfx_clk = {
+ .halt_reg = 0x7106c,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x7106c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_bimc_gfx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_bimc_hmss_axi_clk = {
+ .halt_reg = 0x48004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(22),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_bimc_hmss_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
+ .halt_reg = 0x4401c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4401c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_bimc_mss_q6_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_ahb_clk = {
+ .halt_reg = 0x17004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(17),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
+ .halt_reg = 0x19008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x19008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup1_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup1_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
+ .halt_reg = 0x19004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x19004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup1_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup1_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
+ .halt_reg = 0x1b008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1b008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup2_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup2_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
+ .halt_reg = 0x1b004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1b004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup2_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup2_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
+ .halt_reg = 0x1d008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1d008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup3_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup3_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
+ .halt_reg = 0x1d004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1d004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup3_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup3_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
+ .halt_reg = 0x1f008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1f008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup4_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup4_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
+ .halt_reg = 0x1f004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1f004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup4_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup4_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart1_apps_clk = {
+ .halt_reg = 0x1a004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart1_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_uart1_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart2_apps_clk = {
+ .halt_reg = 0x1c004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1c004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart2_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_uart2_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_ahb_clk = {
+ .halt_reg = 0x25004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(15),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
+ .halt_reg = 0x26008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x26008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup1_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup1_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
+ .halt_reg = 0x26004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x26004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup1_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup1_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
+ .halt_reg = 0x28008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup2_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup2_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
+ .halt_reg = 0x28004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup2_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup2_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
+ .halt_reg = 0x2a008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2a008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup3_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup3_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
+ .halt_reg = 0x2a004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup3_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup3_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
+ .halt_reg = 0x2c008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2c008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup4_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup4_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
+ .halt_reg = 0x2c004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2c004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup4_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup4_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_uart1_apps_clk = {
+ .halt_reg = 0x27004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x27004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_uart1_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_uart1_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_uart2_apps_clk = {
+ .halt_reg = 0x29004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x29004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_uart2_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_uart2_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_boot_rom_ahb_clk = {
+ .halt_reg = 0x38004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(10),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_boot_rom_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cfg_noc_usb2_axi_clk = {
+ .halt_reg = 0x5058,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5058,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_cfg_noc_usb2_axi_clk",
+ .parent_names = (const char *[]){
+ "usb20_master_clk_src",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
+ .halt_reg = 0x5018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_cfg_noc_usb3_axi_clk",
+ .parent_names = (const char *[]){
+ "usb30_master_clk_src",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_dcc_ahb_clk = {
+ .halt_reg = 0x84004,
+ .clkr = {
+ .enable_reg = 0x84004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_dcc_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp1_clk = {
+ .halt_reg = 0x64000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x64000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp1_clk",
+ .parent_names = (const char *[]){
+ "gp1_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp2_clk = {
+ .halt_reg = 0x65000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x65000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp2_clk",
+ .parent_names = (const char *[]){
+ "gp2_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp3_clk = {
+ .halt_reg = 0x66000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x66000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp3_clk",
+ .parent_names = (const char *[]){
+ "gp3_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_bimc_gfx_clk = {
+ .halt_reg = 0x71010,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x71010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_bimc_gfx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_cfg_ahb_clk = {
+ .halt_reg = 0x71004,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x71004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_gpll0_clk = {
+ .halt_reg = 0x5200c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_gpll0_clk",
+ .parent_names = (const char *[]){
+ "gpll0",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_gpll0_div_clk = {
+ .halt_reg = 0x5200c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(3),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_gpll0_div_clk",
+ .parent_names = (const char *[]){
+ "gpll0_early_div",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_hmss_dvm_bus_clk = {
+ .halt_reg = 0x4808c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4808c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_hmss_dvm_bus_clk",
+ .ops = &clk_branch2_ops,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ },
+};
+
+static struct clk_branch gcc_hmss_rbcpr_clk = {
+ .halt_reg = 0x48008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x48008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_hmss_rbcpr_clk",
+ .parent_names = (const char *[]){
+ "hmss_rbcpr_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mmss_gpll0_clk = {
+ .halt_reg = 0x5200c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mmss_gpll0_clk",
+ .parent_names = (const char *[]){
+ "gpll0",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mmss_gpll0_div_clk = {
+ .halt_reg = 0x5200c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mmss_gpll0_div_clk",
+ .parent_names = (const char *[]){
+ "gpll0_early_div",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
+ .halt_reg = 0x9004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mmss_noc_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
+ .halt_reg = 0x9000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mmss_sys_noc_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mss_cfg_ahb_clk = {
+ .halt_reg = 0x8a000,
+ .clkr = {
+ .enable_reg = 0x8a000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mss_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
+ .halt_reg = 0x8a004,
+ .clkr = {
+ .enable_reg = 0x8a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mss_mnoc_bimc_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
+ .halt_reg = 0x8a040,
+ .clkr = {
+ .enable_reg = 0x8a040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mss_q6_bimc_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mss_snoc_axi_clk = {
+ .halt_reg = 0x8a03c,
+ .clkr = {
+ .enable_reg = 0x8a03c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mss_snoc_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pdm2_clk = {
+ .halt_reg = 0x3300c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3300c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pdm2_clk",
+ .parent_names = (const char *[]){
+ "pdm2_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pdm_ahb_clk = {
+ .halt_reg = 0x33004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x33004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pdm_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_prng_ahb_clk = {
+ .halt_reg = 0x34004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(13),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_prng_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qspi_ahb_clk = {
+ .halt_reg = 0x4d004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4d004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qspi_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qspi_ser_clk = {
+ .halt_reg = 0x4d008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4d008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qspi_ser_clk",
+ .parent_names = (const char *[]){
+ "qspi_ser_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_rx0_usb2_clkref_clk = {
+ .halt_reg = 0x88018,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x88018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_rx0_usb2_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_rx1_usb2_clkref_clk = {
+ .halt_reg = 0x88014,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x88014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_rx1_usb2_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_ahb_clk = {
+ .halt_reg = 0x16008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x16008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_apps_clk = {
+ .halt_reg = 0x16004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x16004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_apps_clk",
+ .parent_names = (const char *[]){
+ "sdcc1_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_ice_core_clk = {
+ .halt_reg = 0x1600c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1600c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_ice_core_clk",
+ .parent_names = (const char *[]){
+ "sdcc1_ice_core_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc2_ahb_clk = {
+ .halt_reg = 0x14008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x14008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc2_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc2_apps_clk = {
+ .halt_reg = 0x14004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x14004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc2_apps_clk",
+ .parent_names = (const char *[]){
+ "sdcc2_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_ahb_clk = {
+ .halt_reg = 0x7500c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x7500c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_axi_clk = {
+ .halt_reg = 0x75008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x75008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_axi_clk",
+ .parent_names = (const char *[]){
+ "ufs_axi_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_clkref_clk = {
+ .halt_reg = 0x88008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x88008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_ice_core_clk = {
+ .halt_reg = 0x7600c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x7600c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_ice_core_clk",
+ .parent_names = (const char *[]){
+ "ufs_ice_core_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_phy_aux_clk = {
+ .halt_reg = 0x76040,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x76040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_phy_aux_clk",
+ .parent_names = (const char *[]){
+ "ufs_phy_aux_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
+ .halt_reg = 0x75014,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x75014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_rx_symbol_0_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
+ .halt_reg = 0x7605c,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x7605c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_rx_symbol_1_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
+ .halt_reg = 0x75010,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x75010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_tx_symbol_0_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_unipro_core_clk = {
+ .halt_reg = 0x76008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x76008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_unipro_core_clk",
+ .parent_names = (const char *[]){
+ "ufs_unipro_core_clk_src",
+ },
+ .flags = CLK_SET_RATE_PARENT,
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb20_master_clk = {
+ .halt_reg = 0x2f004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2f004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb20_master_clk",
+ .parent_names = (const char *[]){
+ "usb20_master_clk_src"
+ },
+ .flags = CLK_SET_RATE_PARENT,
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb20_mock_utmi_clk = {
+ .halt_reg = 0x2f00c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2f00c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb20_mock_utmi_clk",
+ .parent_names = (const char *[]){
+ "usb20_mock_utmi_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb20_sleep_clk = {
+ .halt_reg = 0x2f008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2f008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb20_sleep_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_master_clk = {
+ .halt_reg = 0xf008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb30_master_clk",
+ .parent_names = (const char *[]){
+ "usb30_master_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_mock_utmi_clk = {
+ .halt_reg = 0xf010,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb30_mock_utmi_clk",
+ .parent_names = (const char *[]){
+ "usb30_mock_utmi_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_sleep_clk = {
+ .halt_reg = 0xf00c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf00c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb30_sleep_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_clkref_clk = {
+ .halt_reg = 0x8800c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x8800c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb3_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_phy_aux_clk = {
+ .halt_reg = 0x50000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x50000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb3_phy_aux_clk",
+ .parent_names = (const char *[]){
+ "usb3_phy_aux_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_phy_pipe_clk = {
+ .halt_reg = 0x50004,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x50004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb3_phy_pipe_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
+ .halt_reg = 0x6a004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb_phy_cfg_ahb2phy_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct gdsc ufs_gdsc = {
+ .gdscr = 0x75004,
+ .gds_hw_ctrl = 0x0,
+ .pd = {
+ .name = "ufs_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc usb_30_gdsc = {
+ .gdscr = 0xf004,
+ .gds_hw_ctrl = 0x0,
+ .pd = {
+ .name = "usb_30_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc pcie_0_gdsc = {
+ .gdscr = 0x6b004,
+ .gds_hw_ctrl = 0x0,
+ .pd = {
+ .name = "pcie_0_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct clk_hw *gcc_sdm660_hws[] = {
+ [GCC_XO] = &xo.hw,
+ [GCC_GPLL0_EARLY_DIV] = &gpll0_early_div.hw,
+ [GCC_GPLL1_EARLY_DIV] = &gpll1_early_div.hw,
+};
+
+static struct clk_regmap *gcc_660_clocks[] = {
+ [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
+ [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
+ [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
+ [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
+ [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
+ [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
+ [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
+ [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
+ [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
+ [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
+ [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
+ [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
+ [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
+ [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
+ [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
+ [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,
+ [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,
+ [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
+ [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
+ [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
+ [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
+ [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
+ [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
+ [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
+ [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
+ [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
+ [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
+ [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
+ [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
+ [GCC_CFG_NOC_USB2_AXI_CLK] = &gcc_cfg_noc_usb2_axi_clk.clkr,
+ [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,
+ [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
+ [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
+ [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
+ [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
+ [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
+ [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
+ [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,
+ [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,
+ [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr,
+ [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
+ [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,
+ [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
+ [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
+ [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,
+ [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
+ [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
+ [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
+ [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
+ [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
+ [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
+ [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
+ [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
+ [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
+ [GCC_RX0_USB2_CLKREF_CLK] = &gcc_rx0_usb2_clkref_clk.clkr,
+ [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
+ [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
+ [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
+ [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
+ [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
+ [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
+ [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
+ [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
+ [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
+ [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
+ [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,
+ [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
+ [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
+ [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
+ [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
+ [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
+ [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
+ [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
+ [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
+ [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
+ [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
+ [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
+ [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
+ [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
+ [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
+ [GP1_CLK_SRC] = &gp1_clk_src.clkr,
+ [GP2_CLK_SRC] = &gp2_clk_src.clkr,
+ [GP3_CLK_SRC] = &gp3_clk_src.clkr,
+ [GPLL0] = &gpll0.clkr,
+ [GPLL0_EARLY] = &gpll0_early.clkr,
+ [GPLL1] = &gpll1.clkr,
+ [GPLL1_EARLY] = &gpll1_early.clkr,
+ [GPLL1] = &gpll1.clkr,
+ [GPLL4_EARLY] = &gpll4_early.clkr,
+ [GPLL4] = &gpll4.clkr,
+ [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
+ [HMSS_GPLL4_CLK_SRC] = &hmss_gpll4_clk_src.clkr,
+ [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
+ [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
+ [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
+ [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
+ [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
+ [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
+ [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
+ [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
+ [UFS_PHY_AUX_CLK_SRC] = &ufs_phy_aux_clk_src.clkr,
+ [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr,
+ [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
+ [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
+ [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
+ [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
+ [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
+};
+
+static struct gdsc *gcc_660_gdscs[] = {
+ [UFS_GDSC] = &ufs_gdsc,
+ [USB_30_GDSC] = &usb_30_gdsc,
+ [PCIE_0_GDSC] = &pcie_0_gdsc,
+};
+
+static const struct qcom_reset_map gcc_660_resets[] = {
+ [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
+ [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
+ [GCC_UFS_BCR] = { 0x75000 },
+ [GCC_USB3_DP_PHY_BCR] = { 0x50028 },
+ [GCC_USB3_PHY_BCR] = { 0x50020 },
+ [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
+ [GCC_USB_20_BCR] = { 0x2f000 },
+ [GCC_USB_30_BCR] = { 0xf000 },
+ [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
+};
+
+static const struct regmap_config gcc_660_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x94000,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc gcc_660_desc = {
+ .config = &gcc_660_regmap_config,
+ .clks = gcc_660_clocks,
+ .num_clks = ARRAY_SIZE(gcc_660_clocks),
+ .resets = gcc_660_resets,
+ .num_resets = ARRAY_SIZE(gcc_660_resets),
+ .gdscs = gcc_660_gdscs,
+ .num_gdscs = ARRAY_SIZE(gcc_660_gdscs),
+};
+
+static const struct of_device_id gcc_660_match_table[] = {
+ { .compatible = "qcom,gcc-sdm660" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, gcc_660_match_table);
+
+static int gcc_660_probe(struct platform_device *pdev)
+{
+ int i, ret = 0;
+ struct regmap *regmap;
+
+ regmap = qcom_cc_map(pdev, &gcc_660_desc);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ /*
+ * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
+ * turned off by hardware during certain apps low power modes.
+ */
+ ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
+ if (ret)
+ return ret;
+
+ /* Register the hws */
+ for (i = 0; i < ARRAY_SIZE(gcc_sdm660_hws); i++) {
+ ret = devm_clk_hw_register(&pdev->dev, gcc_sdm660_hws[i]);
+ if (ret)
+ return ret;
+ }
+
+ return qcom_cc_really_probe(pdev, &gcc_660_desc, regmap);
+}
+
+static struct platform_driver gcc_660_driver = {
+ .probe = gcc_660_probe,
+ .driver = {
+ .name = "gcc-sdm660",
+ .of_match_table = gcc_660_match_table,
+ },
+};
+
+static int __init gcc_660_init(void)
+{
+ return platform_driver_register(&gcc_660_driver);
+}
+core_initcall_sync(gcc_660_init);
+
+static void __exit gcc_660_exit(void)
+{
+ platform_driver_unregister(&gcc_660_driver);
+}
+module_exit(gcc_660_exit);
+
+MODULE_DESCRIPTION("QCOM GCC sdm660 Driver");
diff --git a/include/dt-bindings/clock/qcom,gcc-sdm660.h b/include/dt-bindings/clock/qcom,gcc-sdm660.h
new file mode 100644
index 000000000000..76aabcc5e7e3
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sdm660.h
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018, Craig Tatlor.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H
+#define _DT_BINDINGS_CLK_MSM_GCC_660_H
+
+#define GCC_XO 0
+#define GCC_GPLL0_EARLY_DIV 1
+#define GCC_GPLL1_EARLY_DIV 2
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 3
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 4
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 5
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 6
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 7
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 8
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC 9
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC 10
+#define BLSP1_UART1_APPS_CLK_SRC 11
+#define BLSP1_UART2_APPS_CLK_SRC 12
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC 13
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC 14
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC 15
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC 16
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC 17
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC 18
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC 19
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC 20
+#define BLSP2_UART1_APPS_CLK_SRC 21
+#define BLSP2_UART2_APPS_CLK_SRC 22
+#define GCC_AGGRE2_UFS_AXI_CLK 23
+#define GCC_AGGRE2_USB3_AXI_CLK 24
+#define GCC_BIMC_GFX_CLK 25
+#define GCC_BIMC_HMSS_AXI_CLK 26
+#define GCC_BIMC_MSS_Q6_AXI_CLK 27
+#define GCC_BLSP1_AHB_CLK 28
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 29
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 30
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 31
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 32
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 33
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 34
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 35
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 36
+#define GCC_BLSP1_UART1_APPS_CLK 37
+#define GCC_BLSP1_UART2_APPS_CLK 38
+#define GCC_BLSP2_AHB_CLK 39
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK 40
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK 41
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK 42
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK 43
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK 44
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK 46
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK 45
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK 46
+#define GCC_BLSP2_UART1_APPS_CLK 47
+#define GCC_BLSP2_UART2_APPS_CLK 48
+#define GCC_BOOT_ROM_AHB_CLK 49
+#define GCC_CFG_NOC_USB2_AXI_CLK 50
+#define GCC_CFG_NOC_USB3_AXI_CLK 51
+#define GCC_DCC_AHB_CLK 52
+#define GCC_GP1_CLK 53
+#define GCC_GP2_CLK 54
+#define GCC_GP3_CLK 55
+#define GCC_GPU_BIMC_GFX_CLK 56
+#define GCC_GPU_CFG_AHB_CLK 57
+#define GCC_GPU_GPLL0_CLK 58
+#define GCC_GPU_GPLL0_DIV_CLK 59
+#define GCC_HMSS_DVM_BUS_CLK 60
+#define GCC_HMSS_RBCPR_CLK 61
+#define GCC_MMSS_GPLL0_CLK 62
+#define GCC_MMSS_GPLL0_DIV_CLK 63
+#define GCC_MMSS_NOC_CFG_AHB_CLK 64
+#define GCC_MMSS_SYS_NOC_AXI_CLK 65
+#define GCC_MSS_CFG_AHB_CLK 66
+#define GCC_MSS_GPLL0_DIV_CLK 67
+#define GCC_MSS_MNOC_BIMC_AXI_CLK 68
+#define GCC_MSS_Q6_BIMC_AXI_CLK 69
+#define GCC_MSS_SNOC_AXI_CLK 70
+#define GCC_PDM2_CLK 71
+#define GCC_PDM_AHB_CLK 72
+#define GCC_PRNG_AHB_CLK 73
+#define GCC_QSPI_AHB_CLK 74
+#define GCC_QSPI_SER_CLK 75
+#define GCC_SDCC1_AHB_CLK 76
+#define GCC_SDCC1_APPS_CLK 77
+#define GCC_SDCC1_ICE_CORE_CLK 78
+#define GCC_SDCC2_AHB_CLK 79
+#define GCC_SDCC2_APPS_CLK 80
+#define GCC_UFS_AHB_CLK 81
+#define GCC_UFS_AXI_CLK 82
+#define GCC_UFS_CLKREF_CLK 83
+#define GCC_UFS_ICE_CORE_CLK 84
+#define GCC_UFS_PHY_AUX_CLK 85
+#define GCC_UFS_RX_SYMBOL_0_CLK 86
+#define GCC_UFS_RX_SYMBOL_1_CLK 87
+#define GCC_UFS_TX_SYMBOL_0_CLK 88
+#define GCC_UFS_UNIPRO_CORE_CLK 89
+#define GCC_USB20_MASTER_CLK 90
+#define GCC_USB20_MOCK_UTMI_CLK 91
+#define GCC_USB20_SLEEP_CLK 92
+#define GCC_USB30_MASTER_CLK 93
+#define GCC_USB30_MOCK_UTMI_CLK 94
+#define GCC_USB30_SLEEP_CLK 95
+#define GCC_USB3_CLKREF_CLK 96
+#define GCC_USB3_PHY_AUX_CLK 97
+#define GCC_USB3_PHY_PIPE_CLK 98
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK 99
+#define GP1_CLK_SRC 100
+#define GP2_CLK_SRC 101
+#define GP3_CLK_SRC 102
+#define GPLL0 103
+#define GPLL0_EARLY 104
+#define GPLL1 105
+#define GPLL1_EARLY 106
+#define GPLL4 107
+#define GPLL4_EARLY 108
+#define HMSS_GPLL0_CLK_SRC 109
+#define HMSS_GPLL4_CLK_SRC 110
+#define HMSS_RBCPR_CLK_SRC 111
+#define PDM2_CLK_SRC 112
+#define QSPI_SER_CLK_SRC 113
+#define SDCC1_APPS_CLK_SRC 114
+#define SDCC1_ICE_CORE_CLK_SRC 115
+#define SDCC2_APPS_CLK_SRC 116
+#define UFS_AXI_CLK_SRC 117
+#define UFS_ICE_CORE_CLK_SRC 118
+#define UFS_PHY_AUX_CLK_SRC 119
+#define UFS_UNIPRO_CORE_CLK_SRC 120
+#define USB20_MASTER_CLK_SRC 121
+#define USB20_MOCK_UTMI_CLK_SRC 122
+#define USB30_MASTER_CLK_SRC 123
+#define USB30_MOCK_UTMI_CLK_SRC 124
+#define USB3_PHY_AUX_CLK_SRC 125
+#define GPLL0_OUT_MSSCC 126
+#define GCC_UFS_AXI_HW_CTL_CLK 127
+#define GCC_UFS_ICE_CORE_HW_CTL_CLK 128
+#define GCC_UFS_PHY_AUX_HW_CTL_CLK 129
+#define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 130
+#define GCC_RX0_USB2_CLKREF_CLK 131
+#define GCC_RX1_USB2_CLKREF_CLK 132
+
+#define PCIE_0_GDSC 0
+#define UFS_GDSC 1
+#define USB_30_GDSC 2
+
+#define GCC_QUSB2PHY_PRIM_BCR 0
+#define GCC_QUSB2PHY_SEC_BCR 1
+#define GCC_UFS_BCR 2
+#define GCC_USB3_DP_PHY_BCR 3
+#define GCC_USB3_PHY_BCR 4
+#define GCC_USB3PHY_PHY_BCR 5
+#define GCC_USB_20_BCR 6
+#define GCC_USB_30_BCR 7
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR 8
+
+#endif
--
2.18.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v2] clk: qcom: Add Global Clock controller (GCC) driver for SDM660
2018-09-25 16:35 ` [PATCH v2] " Craig Tatlor
@ 2018-09-25 16:35 ` Craig Tatlor
0 siblings, 0 replies; 18+ messages in thread
From: Craig Tatlor @ 2018-09-25 16:35 UTC (permalink / raw)
Cc: ctatlor97, linux-arm-msm, Taniya Das, Michael Turquette,
Stephen Boyd, Rob Herring, Mark Rutland, Andy Gross, David Brown,
linux-clk, devicetree, linux-kernel, linux-soc
From: Taniya Das <tdas@codeaurora.org>
Add support for the global clock controller found on SDM660
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Based on CAF implementation.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
[craig: rename parents to fit upstream, and other cleanups]
Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
---
.../devicetree/bindings/clock/qcom,gcc.txt | 1 +
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-sdm660.c | 2479 +++++++++++++++++
include/dt-bindings/clock/qcom,gcc-sdm660.h | 159 ++
5 files changed, 2649 insertions(+)
create mode 100644 drivers/clk/qcom/gcc-sdm660.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-sdm660.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 664ea1fd6c76..e498ad2e8db8 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -19,6 +19,7 @@ Required properties :
"qcom,gcc-msm8996"
"qcom,gcc-msm8998"
"qcom,gcc-mdm9615"
+ "qcom,gcc-sdm660"
"qcom,gcc-sdm845"
- reg : shall contain base register location and length
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 5b181b182f40..4d478b261dfe 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -243,6 +243,15 @@ config SDM_CAMCC_845
Support for the camera clock controller on SDM845 devices.
Say Y if you want to support camera devices and camera functionality.
+config SDM_GCC_660
+ tristate "SDM660 Global Clock Controller"
+ select QCOM_GDSC
+ depends on COMMON_CLK_QCOM
+ help
+ Support for the global clock controller on SDM660 devices.
+ Say Y if you want to use peripheral devices such as UART, SPI,
+ i2C, USB, UFS, SDDC, PCIe, etc.
+
config SDM_GCC_845
tristate "SDM845 Global Clock Controller"
select QCOM_GDSC
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 935f142bc155..ab892f6d847c 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o
obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o
obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
+obj-$(CONFIG_SDM_GCC_660) += gcc-sdm660.o
obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
new file mode 100644
index 000000000000..cec8b4145b71
--- /dev/null
+++ b/drivers/clk/qcom/gcc-sdm660.c
@@ -0,0 +1,2479 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018, Craig Tatlor.
+ */
+
+#include <linux/kernel.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/clock/qcom,gcc-sdm660.h>
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-alpha-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "reset.h"
+#include "gdsc.h"
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+enum {
+ P_XO,
+ P_SLEEP_CLK,
+ P_GPLL0,
+ P_GPLL1,
+ P_GPLL4,
+ P_GPLL0_EARLY_DIV,
+ P_GPLL1_EARLY_DIV,
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_EARLY_DIV, 6 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div[] = {
+ "xo",
+ "gpll0",
+ "gpll0_early_div",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0[] = {
+ "xo",
+ "gpll0",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_SLEEP_CLK, 5 },
+ { P_GPLL0_EARLY_DIV, 6 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div[] = {
+ "xo",
+ "gpll0",
+ "sleep_clk",
+ "gpll0_early_div",
+};
+
+static const struct parent_map gcc_parent_map_xo_sleep_clk[] = {
+ { P_XO, 0 },
+ { P_SLEEP_CLK, 5 },
+};
+
+static const char * const gcc_parent_names_xo_sleep_clk[] = {
+ "xo",
+ "sleep_clk",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll4[] = {
+ { P_XO, 0 },
+ { P_GPLL4, 5 },
+};
+
+static const char * const gcc_parent_names_xo_gpll4[] = {
+ "xo",
+ "gpll4",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_EARLY_DIV, 3 },
+ { P_GPLL1, 4 },
+ { P_GPLL4, 5 },
+ { P_GPLL1_EARLY_DIV, 6 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
+ "xo",
+ "gpll0",
+ "gpll0_early_div",
+ "gpll1",
+ "gpll4",
+ "gpll1_early_div",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL4, 5 },
+ { P_GPLL0_EARLY_DIV, 6 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div[] = {
+ "xo",
+ "gpll0",
+ "gpll4",
+ "gpll0_early_div",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_EARLY_DIV, 2 },
+ { P_GPLL4, 5 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4[] = {
+ "xo",
+ "gpll0",
+ "gpll0_early_div",
+ "gpll4",
+};
+
+static struct clk_fixed_factor xo = {
+ .mult = 1,
+ .div = 1,
+ .hw.init = &(struct clk_init_data){
+ .name = "xo",
+ .parent_names = (const char *[]){ "xo_board" },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll0_early = {
+ .offset = 0x0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_early",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor gpll0_early_div = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_early_div",
+ .parent_names = (const char *[]){ "gpll0_early" },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll0 = {
+ .offset = 0x00000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll0",
+ .parent_names = (const char *[]){ "gpll0_early" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll1_early = {
+ .offset = 0x1000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll1_early",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor gpll1_early_div = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll1_early_div",
+ .parent_names = (const char *[]){ "gpll1_early" },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll1 = {
+ .offset = 0x1000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll1",
+ .parent_names = (const char *[]){ "gpll1_early" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll4_early = {
+ .offset = 0x77000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll4_early",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll4 = {
+ .offset = 0x77000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "gpll4",
+ .parent_names = (const char *[]) { "gpll4_early" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(50000000, P_GPLL0, 12, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x19020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup1_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(50000000, P_GPLL0, 12, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
+ .cmd_rcgr = 0x1900c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup1_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x1b020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup2_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
+ .cmd_rcgr = 0x1b00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup2_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x1d020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup3_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
+ .cmd_rcgr = 0x1d00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup3_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x1f020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup4_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
+ .cmd_rcgr = 0x1f00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup4_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
+ F(3686400, P_GPLL0, 1, 96, 15625),
+ F(7372800, P_GPLL0, 1, 192, 15625),
+ F(14745600, P_GPLL0, 1, 384, 15625),
+ F(16000000, P_GPLL0, 5, 2, 15),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 5, 1, 5),
+ F(32000000, P_GPLL0, 1, 4, 75),
+ F(40000000, P_GPLL0, 15, 0, 0),
+ F(46400000, P_GPLL0, 1, 29, 375),
+ F(48000000, P_GPLL0, 12.5, 0, 0),
+ F(51200000, P_GPLL0, 1, 32, 375),
+ F(56000000, P_GPLL0, 1, 7, 75),
+ F(58982400, P_GPLL0, 1, 1536, 15625),
+ F(60000000, P_GPLL0, 10, 0, 0),
+ F(63157895, P_GPLL0, 9.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
+ .cmd_rcgr = 0x1a00c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart1_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
+ .cmd_rcgr = 0x1c00c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart2_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x26020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup1_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
+ .cmd_rcgr = 0x2600c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup1_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x28020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup2_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
+ .cmd_rcgr = 0x2800c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup2_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x2a020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup3_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
+ .cmd_rcgr = 0x2a00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup3_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x2c020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup4_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
+ .cmd_rcgr = 0x2c00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup4_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
+ .cmd_rcgr = 0x2700c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_uart1_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
+ .cmd_rcgr = 0x2900c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_uart2_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gp1_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gp1_clk_src = {
+ .cmd_rcgr = 0x64004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
+ .freq_tbl = ftbl_gp1_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp1_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gp2_clk_src = {
+ .cmd_rcgr = 0x65004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
+ .freq_tbl = ftbl_gp1_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp2_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gp3_clk_src = {
+ .cmd_rcgr = 0x66004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
+ .freq_tbl = ftbl_gp1_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp3_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] = {
+ F(300000000, P_GPLL0, 2, 0, 0),
+ F(600000000, P_GPLL0, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 hmss_gpll0_clk_src = {
+ .cmd_rcgr = 0x4805c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_hmss_gpll0_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "hmss_gpll0_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_hmss_gpll4_clk_src[] = {
+ F(384000000, P_GPLL4, 4, 0, 0),
+ F(768000000, P_GPLL4, 2, 0, 0),
+ F(1536000000, P_GPLL4, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 hmss_gpll4_clk_src = {
+ .cmd_rcgr = 0x48074,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll4,
+ .freq_tbl = ftbl_hmss_gpll4_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "hmss_gpll4_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll4,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 hmss_rbcpr_clk_src = {
+ .cmd_rcgr = 0x48044,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_hmss_rbcpr_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "hmss_rbcpr_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_pdm2_clk_src[] = {
+ F(60000000, P_GPLL0, 10, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 pdm2_clk_src = {
+ .cmd_rcgr = 0x33010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_pdm2_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pdm2_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(80200000, P_GPLL1_EARLY_DIV, 5, 0, 0),
+ F(160400000, P_GPLL1, 5, 0, 0),
+ F(267333333, P_GPLL1, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 qspi_ser_clk_src = {
+ .cmd_rcgr = 0x4d00c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
+ .freq_tbl = ftbl_qspi_ser_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "qspi_ser_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
+ .num_parents = 6,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
+ F(144000, P_XO, 16, 3, 25),
+ F(400000, P_XO, 12, 1, 4),
+ F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
+ F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
+ F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(192000000, P_GPLL4, 8, 0, 0),
+ F(384000000, P_GPLL4, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 sdcc1_apps_clk_src = {
+ .cmd_rcgr = 0x1602c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div,
+ .freq_tbl = ftbl_sdcc1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc1_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
+ F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ F(300000000, P_GPLL0, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 sdcc1_ice_core_clk_src = {
+ .cmd_rcgr = 0x16010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc1_ice_core_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
+ F(144000, P_XO, 16, 3, 25),
+ F(400000, P_XO, 12, 1, 4),
+ F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
+ F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
+ F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(192000000, P_GPLL4, 8, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 sdcc2_apps_clk_src = {
+ .cmd_rcgr = 0x14010,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4,
+ .freq_tbl = ftbl_sdcc2_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc2_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
+ F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ F(240000000, P_GPLL0, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ufs_axi_clk_src = {
+ .cmd_rcgr = 0x75018,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_ufs_axi_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ufs_axi_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
+ F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ F(300000000, P_GPLL0, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ufs_ice_core_clk_src = {
+ .cmd_rcgr = 0x76010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_ufs_ice_core_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ufs_ice_core_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 ufs_phy_aux_clk_src = {
+ .cmd_rcgr = 0x76044,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_sleep_clk,
+ .freq_tbl = ftbl_hmss_rbcpr_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ufs_phy_aux_clk_src",
+ .parent_names = gcc_parent_names_xo_sleep_clk,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = {
+ F(37500000, P_GPLL0_EARLY_DIV, 8, 0, 0),
+ F(75000000, P_GPLL0, 8, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ufs_unipro_core_clk_src = {
+ .cmd_rcgr = 0x76028,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_ufs_unipro_core_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ufs_unipro_core_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(60000000, P_GPLL0, 10, 0, 0),
+ F(120000000, P_GPLL0, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb20_master_clk_src = {
+ .cmd_rcgr = 0x2f010,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_usb20_master_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb20_master_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb20_mock_utmi_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(60000000, P_GPLL0, 10, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb20_mock_utmi_clk_src = {
+ .cmd_rcgr = 0x2f024,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_usb20_mock_utmi_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb20_mock_utmi_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(66666667, P_GPLL0_EARLY_DIV, 4.5, 0, 0),
+ F(120000000, P_GPLL0, 5, 0, 0),
+ F(133333333, P_GPLL0, 4.5, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ F(240000000, P_GPLL0, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb30_master_clk_src = {
+ .cmd_rcgr = 0xf014,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_usb30_master_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb30_master_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(40000000, P_GPLL0_EARLY_DIV, 7.5, 0, 0),
+ F(60000000, P_GPLL0, 10, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb30_mock_utmi_clk_src = {
+ .cmd_rcgr = 0xf028,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb30_mock_utmi_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
+ F(1200000, P_XO, 16, 0, 0),
+ F(19200000, P_XO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb3_phy_aux_clk_src = {
+ .cmd_rcgr = 0x5000c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_sleep_clk,
+ .freq_tbl = ftbl_usb3_phy_aux_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb3_phy_aux_clk_src",
+ .parent_names = gcc_parent_names_xo_sleep_clk,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_branch gcc_aggre2_ufs_axi_clk = {
+ .halt_reg = 0x75034,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x75034,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_aggre2_ufs_axi_clk",
+ .parent_names = (const char *[]){
+ "ufs_axi_clk_src",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_aggre2_usb3_axi_clk = {
+ .halt_reg = 0xf03c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf03c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_aggre2_usb3_axi_clk",
+ .parent_names = (const char *[]){
+ "usb30_master_clk_src",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_bimc_gfx_clk = {
+ .halt_reg = 0x7106c,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x7106c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_bimc_gfx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_bimc_hmss_axi_clk = {
+ .halt_reg = 0x48004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(22),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_bimc_hmss_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
+ .halt_reg = 0x4401c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4401c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_bimc_mss_q6_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_ahb_clk = {
+ .halt_reg = 0x17004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(17),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
+ .halt_reg = 0x19008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x19008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup1_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup1_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
+ .halt_reg = 0x19004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x19004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup1_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup1_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
+ .halt_reg = 0x1b008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1b008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup2_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup2_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
+ .halt_reg = 0x1b004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1b004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup2_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup2_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
+ .halt_reg = 0x1d008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1d008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup3_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup3_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
+ .halt_reg = 0x1d004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1d004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup3_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup3_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
+ .halt_reg = 0x1f008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1f008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup4_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup4_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
+ .halt_reg = 0x1f004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1f004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup4_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup4_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart1_apps_clk = {
+ .halt_reg = 0x1a004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart1_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_uart1_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart2_apps_clk = {
+ .halt_reg = 0x1c004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1c004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart2_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_uart2_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_ahb_clk = {
+ .halt_reg = 0x25004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(15),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
+ .halt_reg = 0x26008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x26008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup1_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup1_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
+ .halt_reg = 0x26004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x26004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup1_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup1_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
+ .halt_reg = 0x28008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup2_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup2_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
+ .halt_reg = 0x28004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup2_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup2_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
+ .halt_reg = 0x2a008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2a008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup3_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup3_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
+ .halt_reg = 0x2a004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup3_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup3_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
+ .halt_reg = 0x2c008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2c008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup4_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup4_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
+ .halt_reg = 0x2c004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2c004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup4_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup4_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_uart1_apps_clk = {
+ .halt_reg = 0x27004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x27004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_uart1_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_uart1_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_uart2_apps_clk = {
+ .halt_reg = 0x29004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x29004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_uart2_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_uart2_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_boot_rom_ahb_clk = {
+ .halt_reg = 0x38004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(10),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_boot_rom_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cfg_noc_usb2_axi_clk = {
+ .halt_reg = 0x5058,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5058,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_cfg_noc_usb2_axi_clk",
+ .parent_names = (const char *[]){
+ "usb20_master_clk_src",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
+ .halt_reg = 0x5018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_cfg_noc_usb3_axi_clk",
+ .parent_names = (const char *[]){
+ "usb30_master_clk_src",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_dcc_ahb_clk = {
+ .halt_reg = 0x84004,
+ .clkr = {
+ .enable_reg = 0x84004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_dcc_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp1_clk = {
+ .halt_reg = 0x64000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x64000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp1_clk",
+ .parent_names = (const char *[]){
+ "gp1_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp2_clk = {
+ .halt_reg = 0x65000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x65000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp2_clk",
+ .parent_names = (const char *[]){
+ "gp2_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp3_clk = {
+ .halt_reg = 0x66000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x66000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp3_clk",
+ .parent_names = (const char *[]){
+ "gp3_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_bimc_gfx_clk = {
+ .halt_reg = 0x71010,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x71010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_bimc_gfx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_cfg_ahb_clk = {
+ .halt_reg = 0x71004,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x71004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_gpll0_clk = {
+ .halt_reg = 0x5200c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_gpll0_clk",
+ .parent_names = (const char *[]){
+ "gpll0",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_gpll0_div_clk = {
+ .halt_reg = 0x5200c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(3),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_gpll0_div_clk",
+ .parent_names = (const char *[]){
+ "gpll0_early_div",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_hmss_dvm_bus_clk = {
+ .halt_reg = 0x4808c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4808c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_hmss_dvm_bus_clk",
+ .ops = &clk_branch2_ops,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ },
+};
+
+static struct clk_branch gcc_hmss_rbcpr_clk = {
+ .halt_reg = 0x48008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x48008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_hmss_rbcpr_clk",
+ .parent_names = (const char *[]){
+ "hmss_rbcpr_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mmss_gpll0_clk = {
+ .halt_reg = 0x5200c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mmss_gpll0_clk",
+ .parent_names = (const char *[]){
+ "gpll0",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mmss_gpll0_div_clk = {
+ .halt_reg = 0x5200c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mmss_gpll0_div_clk",
+ .parent_names = (const char *[]){
+ "gpll0_early_div",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
+ .halt_reg = 0x9004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mmss_noc_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
+ .halt_reg = 0x9000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mmss_sys_noc_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mss_cfg_ahb_clk = {
+ .halt_reg = 0x8a000,
+ .clkr = {
+ .enable_reg = 0x8a000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mss_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
+ .halt_reg = 0x8a004,
+ .clkr = {
+ .enable_reg = 0x8a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mss_mnoc_bimc_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
+ .halt_reg = 0x8a040,
+ .clkr = {
+ .enable_reg = 0x8a040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mss_q6_bimc_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mss_snoc_axi_clk = {
+ .halt_reg = 0x8a03c,
+ .clkr = {
+ .enable_reg = 0x8a03c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mss_snoc_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pdm2_clk = {
+ .halt_reg = 0x3300c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3300c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pdm2_clk",
+ .parent_names = (const char *[]){
+ "pdm2_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pdm_ahb_clk = {
+ .halt_reg = 0x33004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x33004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pdm_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_prng_ahb_clk = {
+ .halt_reg = 0x34004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(13),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_prng_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qspi_ahb_clk = {
+ .halt_reg = 0x4d004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4d004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qspi_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qspi_ser_clk = {
+ .halt_reg = 0x4d008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4d008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qspi_ser_clk",
+ .parent_names = (const char *[]){
+ "qspi_ser_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_rx0_usb2_clkref_clk = {
+ .halt_reg = 0x88018,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x88018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_rx0_usb2_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_rx1_usb2_clkref_clk = {
+ .halt_reg = 0x88014,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x88014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_rx1_usb2_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_ahb_clk = {
+ .halt_reg = 0x16008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x16008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_apps_clk = {
+ .halt_reg = 0x16004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x16004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_apps_clk",
+ .parent_names = (const char *[]){
+ "sdcc1_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_ice_core_clk = {
+ .halt_reg = 0x1600c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1600c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_ice_core_clk",
+ .parent_names = (const char *[]){
+ "sdcc1_ice_core_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc2_ahb_clk = {
+ .halt_reg = 0x14008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x14008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc2_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc2_apps_clk = {
+ .halt_reg = 0x14004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x14004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc2_apps_clk",
+ .parent_names = (const char *[]){
+ "sdcc2_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_ahb_clk = {
+ .halt_reg = 0x7500c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x7500c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_axi_clk = {
+ .halt_reg = 0x75008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x75008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_axi_clk",
+ .parent_names = (const char *[]){
+ "ufs_axi_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_clkref_clk = {
+ .halt_reg = 0x88008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x88008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_ice_core_clk = {
+ .halt_reg = 0x7600c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x7600c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_ice_core_clk",
+ .parent_names = (const char *[]){
+ "ufs_ice_core_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_phy_aux_clk = {
+ .halt_reg = 0x76040,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x76040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_phy_aux_clk",
+ .parent_names = (const char *[]){
+ "ufs_phy_aux_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
+ .halt_reg = 0x75014,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x75014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_rx_symbol_0_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
+ .halt_reg = 0x7605c,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x7605c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_rx_symbol_1_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
+ .halt_reg = 0x75010,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x75010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_tx_symbol_0_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_unipro_core_clk = {
+ .halt_reg = 0x76008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x76008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_unipro_core_clk",
+ .parent_names = (const char *[]){
+ "ufs_unipro_core_clk_src",
+ },
+ .flags = CLK_SET_RATE_PARENT,
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb20_master_clk = {
+ .halt_reg = 0x2f004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2f004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb20_master_clk",
+ .parent_names = (const char *[]){
+ "usb20_master_clk_src"
+ },
+ .flags = CLK_SET_RATE_PARENT,
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb20_mock_utmi_clk = {
+ .halt_reg = 0x2f00c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2f00c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb20_mock_utmi_clk",
+ .parent_names = (const char *[]){
+ "usb20_mock_utmi_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb20_sleep_clk = {
+ .halt_reg = 0x2f008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2f008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb20_sleep_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_master_clk = {
+ .halt_reg = 0xf008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb30_master_clk",
+ .parent_names = (const char *[]){
+ "usb30_master_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_mock_utmi_clk = {
+ .halt_reg = 0xf010,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb30_mock_utmi_clk",
+ .parent_names = (const char *[]){
+ "usb30_mock_utmi_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_sleep_clk = {
+ .halt_reg = 0xf00c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf00c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb30_sleep_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_clkref_clk = {
+ .halt_reg = 0x8800c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x8800c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb3_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_phy_aux_clk = {
+ .halt_reg = 0x50000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x50000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb3_phy_aux_clk",
+ .parent_names = (const char *[]){
+ "usb3_phy_aux_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_phy_pipe_clk = {
+ .halt_reg = 0x50004,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x50004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb3_phy_pipe_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
+ .halt_reg = 0x6a004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb_phy_cfg_ahb2phy_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct gdsc ufs_gdsc = {
+ .gdscr = 0x75004,
+ .gds_hw_ctrl = 0x0,
+ .pd = {
+ .name = "ufs_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc usb_30_gdsc = {
+ .gdscr = 0xf004,
+ .gds_hw_ctrl = 0x0,
+ .pd = {
+ .name = "usb_30_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc pcie_0_gdsc = {
+ .gdscr = 0x6b004,
+ .gds_hw_ctrl = 0x0,
+ .pd = {
+ .name = "pcie_0_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct clk_hw *gcc_sdm660_hws[] = {
+ [GCC_XO] = &xo.hw,
+ [GCC_GPLL0_EARLY_DIV] = &gpll0_early_div.hw,
+ [GCC_GPLL1_EARLY_DIV] = &gpll1_early_div.hw,
+};
+
+static struct clk_regmap *gcc_660_clocks[] = {
+ [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
+ [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
+ [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
+ [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
+ [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
+ [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
+ [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
+ [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
+ [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
+ [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
+ [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
+ [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
+ [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
+ [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
+ [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
+ [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,
+ [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,
+ [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
+ [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
+ [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
+ [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
+ [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
+ [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
+ [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
+ [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
+ [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
+ [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
+ [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
+ [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
+ [GCC_CFG_NOC_USB2_AXI_CLK] = &gcc_cfg_noc_usb2_axi_clk.clkr,
+ [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,
+ [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
+ [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
+ [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
+ [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
+ [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
+ [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
+ [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,
+ [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,
+ [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr,
+ [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
+ [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,
+ [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
+ [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
+ [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,
+ [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
+ [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
+ [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
+ [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
+ [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
+ [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
+ [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
+ [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
+ [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
+ [GCC_RX0_USB2_CLKREF_CLK] = &gcc_rx0_usb2_clkref_clk.clkr,
+ [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
+ [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
+ [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
+ [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
+ [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
+ [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
+ [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
+ [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
+ [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
+ [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
+ [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,
+ [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
+ [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
+ [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
+ [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
+ [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
+ [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
+ [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
+ [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
+ [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
+ [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
+ [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
+ [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
+ [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
+ [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
+ [GP1_CLK_SRC] = &gp1_clk_src.clkr,
+ [GP2_CLK_SRC] = &gp2_clk_src.clkr,
+ [GP3_CLK_SRC] = &gp3_clk_src.clkr,
+ [GPLL0] = &gpll0.clkr,
+ [GPLL0_EARLY] = &gpll0_early.clkr,
+ [GPLL1] = &gpll1.clkr,
+ [GPLL1_EARLY] = &gpll1_early.clkr,
+ [GPLL1] = &gpll1.clkr,
+ [GPLL4_EARLY] = &gpll4_early.clkr,
+ [GPLL4] = &gpll4.clkr,
+ [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
+ [HMSS_GPLL4_CLK_SRC] = &hmss_gpll4_clk_src.clkr,
+ [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
+ [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
+ [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
+ [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
+ [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
+ [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
+ [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
+ [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
+ [UFS_PHY_AUX_CLK_SRC] = &ufs_phy_aux_clk_src.clkr,
+ [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr,
+ [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
+ [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
+ [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
+ [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
+ [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
+};
+
+static struct gdsc *gcc_660_gdscs[] = {
+ [UFS_GDSC] = &ufs_gdsc,
+ [USB_30_GDSC] = &usb_30_gdsc,
+ [PCIE_0_GDSC] = &pcie_0_gdsc,
+};
+
+static const struct qcom_reset_map gcc_660_resets[] = {
+ [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
+ [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
+ [GCC_UFS_BCR] = { 0x75000 },
+ [GCC_USB3_DP_PHY_BCR] = { 0x50028 },
+ [GCC_USB3_PHY_BCR] = { 0x50020 },
+ [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
+ [GCC_USB_20_BCR] = { 0x2f000 },
+ [GCC_USB_30_BCR] = { 0xf000 },
+ [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
+};
+
+static const struct regmap_config gcc_660_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x94000,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc gcc_660_desc = {
+ .config = &gcc_660_regmap_config,
+ .clks = gcc_660_clocks,
+ .num_clks = ARRAY_SIZE(gcc_660_clocks),
+ .resets = gcc_660_resets,
+ .num_resets = ARRAY_SIZE(gcc_660_resets),
+ .gdscs = gcc_660_gdscs,
+ .num_gdscs = ARRAY_SIZE(gcc_660_gdscs),
+};
+
+static const struct of_device_id gcc_660_match_table[] = {
+ { .compatible = "qcom,gcc-sdm660" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, gcc_660_match_table);
+
+static int gcc_660_probe(struct platform_device *pdev)
+{
+ int i, ret = 0;
+ struct regmap *regmap;
+
+ regmap = qcom_cc_map(pdev, &gcc_660_desc);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ /*
+ * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
+ * turned off by hardware during certain apps low power modes.
+ */
+ ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
+ if (ret)
+ return ret;
+
+ /* Register the hws */
+ for (i = 0; i < ARRAY_SIZE(gcc_sdm660_hws); i++) {
+ ret = devm_clk_hw_register(&pdev->dev, gcc_sdm660_hws[i]);
+ if (ret)
+ return ret;
+ }
+
+ return qcom_cc_really_probe(pdev, &gcc_660_desc, regmap);
+}
+
+static struct platform_driver gcc_660_driver = {
+ .probe = gcc_660_probe,
+ .driver = {
+ .name = "gcc-sdm660",
+ .of_match_table = gcc_660_match_table,
+ },
+};
+
+static int __init gcc_660_init(void)
+{
+ return platform_driver_register(&gcc_660_driver);
+}
+core_initcall_sync(gcc_660_init);
+
+static void __exit gcc_660_exit(void)
+{
+ platform_driver_unregister(&gcc_660_driver);
+}
+module_exit(gcc_660_exit);
+
+MODULE_DESCRIPTION("QCOM GCC sdm660 Driver");
diff --git a/include/dt-bindings/clock/qcom,gcc-sdm660.h b/include/dt-bindings/clock/qcom,gcc-sdm660.h
new file mode 100644
index 000000000000..76aabcc5e7e3
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sdm660.h
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018, Craig Tatlor.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H
+#define _DT_BINDINGS_CLK_MSM_GCC_660_H
+
+#define GCC_XO 0
+#define GCC_GPLL0_EARLY_DIV 1
+#define GCC_GPLL1_EARLY_DIV 2
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 3
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 4
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 5
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 6
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 7
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 8
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC 9
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC 10
+#define BLSP1_UART1_APPS_CLK_SRC 11
+#define BLSP1_UART2_APPS_CLK_SRC 12
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC 13
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC 14
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC 15
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC 16
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC 17
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC 18
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC 19
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC 20
+#define BLSP2_UART1_APPS_CLK_SRC 21
+#define BLSP2_UART2_APPS_CLK_SRC 22
+#define GCC_AGGRE2_UFS_AXI_CLK 23
+#define GCC_AGGRE2_USB3_AXI_CLK 24
+#define GCC_BIMC_GFX_CLK 25
+#define GCC_BIMC_HMSS_AXI_CLK 26
+#define GCC_BIMC_MSS_Q6_AXI_CLK 27
+#define GCC_BLSP1_AHB_CLK 28
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 29
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 30
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 31
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 32
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 33
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 34
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 35
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 36
+#define GCC_BLSP1_UART1_APPS_CLK 37
+#define GCC_BLSP1_UART2_APPS_CLK 38
+#define GCC_BLSP2_AHB_CLK 39
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK 40
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK 41
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK 42
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK 43
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK 44
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK 46
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK 45
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK 46
+#define GCC_BLSP2_UART1_APPS_CLK 47
+#define GCC_BLSP2_UART2_APPS_CLK 48
+#define GCC_BOOT_ROM_AHB_CLK 49
+#define GCC_CFG_NOC_USB2_AXI_CLK 50
+#define GCC_CFG_NOC_USB3_AXI_CLK 51
+#define GCC_DCC_AHB_CLK 52
+#define GCC_GP1_CLK 53
+#define GCC_GP2_CLK 54
+#define GCC_GP3_CLK 55
+#define GCC_GPU_BIMC_GFX_CLK 56
+#define GCC_GPU_CFG_AHB_CLK 57
+#define GCC_GPU_GPLL0_CLK 58
+#define GCC_GPU_GPLL0_DIV_CLK 59
+#define GCC_HMSS_DVM_BUS_CLK 60
+#define GCC_HMSS_RBCPR_CLK 61
+#define GCC_MMSS_GPLL0_CLK 62
+#define GCC_MMSS_GPLL0_DIV_CLK 63
+#define GCC_MMSS_NOC_CFG_AHB_CLK 64
+#define GCC_MMSS_SYS_NOC_AXI_CLK 65
+#define GCC_MSS_CFG_AHB_CLK 66
+#define GCC_MSS_GPLL0_DIV_CLK 67
+#define GCC_MSS_MNOC_BIMC_AXI_CLK 68
+#define GCC_MSS_Q6_BIMC_AXI_CLK 69
+#define GCC_MSS_SNOC_AXI_CLK 70
+#define GCC_PDM2_CLK 71
+#define GCC_PDM_AHB_CLK 72
+#define GCC_PRNG_AHB_CLK 73
+#define GCC_QSPI_AHB_CLK 74
+#define GCC_QSPI_SER_CLK 75
+#define GCC_SDCC1_AHB_CLK 76
+#define GCC_SDCC1_APPS_CLK 77
+#define GCC_SDCC1_ICE_CORE_CLK 78
+#define GCC_SDCC2_AHB_CLK 79
+#define GCC_SDCC2_APPS_CLK 80
+#define GCC_UFS_AHB_CLK 81
+#define GCC_UFS_AXI_CLK 82
+#define GCC_UFS_CLKREF_CLK 83
+#define GCC_UFS_ICE_CORE_CLK 84
+#define GCC_UFS_PHY_AUX_CLK 85
+#define GCC_UFS_RX_SYMBOL_0_CLK 86
+#define GCC_UFS_RX_SYMBOL_1_CLK 87
+#define GCC_UFS_TX_SYMBOL_0_CLK 88
+#define GCC_UFS_UNIPRO_CORE_CLK 89
+#define GCC_USB20_MASTER_CLK 90
+#define GCC_USB20_MOCK_UTMI_CLK 91
+#define GCC_USB20_SLEEP_CLK 92
+#define GCC_USB30_MASTER_CLK 93
+#define GCC_USB30_MOCK_UTMI_CLK 94
+#define GCC_USB30_SLEEP_CLK 95
+#define GCC_USB3_CLKREF_CLK 96
+#define GCC_USB3_PHY_AUX_CLK 97
+#define GCC_USB3_PHY_PIPE_CLK 98
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK 99
+#define GP1_CLK_SRC 100
+#define GP2_CLK_SRC 101
+#define GP3_CLK_SRC 102
+#define GPLL0 103
+#define GPLL0_EARLY 104
+#define GPLL1 105
+#define GPLL1_EARLY 106
+#define GPLL4 107
+#define GPLL4_EARLY 108
+#define HMSS_GPLL0_CLK_SRC 109
+#define HMSS_GPLL4_CLK_SRC 110
+#define HMSS_RBCPR_CLK_SRC 111
+#define PDM2_CLK_SRC 112
+#define QSPI_SER_CLK_SRC 113
+#define SDCC1_APPS_CLK_SRC 114
+#define SDCC1_ICE_CORE_CLK_SRC 115
+#define SDCC2_APPS_CLK_SRC 116
+#define UFS_AXI_CLK_SRC 117
+#define UFS_ICE_CORE_CLK_SRC 118
+#define UFS_PHY_AUX_CLK_SRC 119
+#define UFS_UNIPRO_CORE_CLK_SRC 120
+#define USB20_MASTER_CLK_SRC 121
+#define USB20_MOCK_UTMI_CLK_SRC 122
+#define USB30_MASTER_CLK_SRC 123
+#define USB30_MOCK_UTMI_CLK_SRC 124
+#define USB3_PHY_AUX_CLK_SRC 125
+#define GPLL0_OUT_MSSCC 126
+#define GCC_UFS_AXI_HW_CTL_CLK 127
+#define GCC_UFS_ICE_CORE_HW_CTL_CLK 128
+#define GCC_UFS_PHY_AUX_HW_CTL_CLK 129
+#define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 130
+#define GCC_RX0_USB2_CLKREF_CLK 131
+#define GCC_RX1_USB2_CLKREF_CLK 132
+
+#define PCIE_0_GDSC 0
+#define UFS_GDSC 1
+#define USB_30_GDSC 2
+
+#define GCC_QUSB2PHY_PRIM_BCR 0
+#define GCC_QUSB2PHY_SEC_BCR 1
+#define GCC_UFS_BCR 2
+#define GCC_USB3_DP_PHY_BCR 3
+#define GCC_USB3_PHY_BCR 4
+#define GCC_USB3PHY_PHY_BCR 5
+#define GCC_USB_20_BCR 6
+#define GCC_USB_30_BCR 7
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR 8
+
+#endif
--
2.18.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3] clk: qcom: Add Global Clock controller (GCC) driver for SDM660
2018-08-10 20:21 ` [PATCH] clk: qcom: Add Global Clock controller (GCC) driver for SDM660 Craig Tatlor
` (3 preceding siblings ...)
2018-09-25 16:35 ` [PATCH v2] " Craig Tatlor
@ 2018-09-25 17:35 ` Craig Tatlor
2018-09-25 17:35 ` Craig Tatlor
` (3 more replies)
4 siblings, 4 replies; 18+ messages in thread
From: Craig Tatlor @ 2018-09-25 17:35 UTC (permalink / raw)
Cc: ctatlor97, linux-arm-msm, Taniya Das, Michael Turquette,
Stephen Boyd, Rob Herring, Mark Rutland, Andy Gross, David Brown,
linux-clk, devicetree, linux-kernel, linux-soc
From: Taniya Das <tdas@codeaurora.org>
Add support for the global clock controller found on SDM660
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Based on CAF implementation.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
[craig: rename parents to fit upstream, and other cleanups]
Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
---
Changes from V1:
Change authorship
Add sdm630 compatible
.../devicetree/bindings/clock/qcom,gcc.txt | 1 +
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-sdm660.c | 2480 +++++++++++++++++
include/dt-bindings/clock/qcom,gcc-sdm660.h | 159 ++
5 files changed, 2650 insertions(+)
create mode 100644 drivers/clk/qcom/gcc-sdm660.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-sdm660.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 664ea1fd6c76..e498ad2e8db8 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -38,6 +38,8 @@ Required properties :
"qcom,gcc-msm8996"
"qcom,gcc-msm8998"
"qcom,gcc-mdm9615"
+ "qcom,gcc-sdm630"
+ "qcom,gcc-sdm660"
"qcom,gcc-sdm845"
- reg : shall contain base register location and length
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 5b181b182f40..4d478b261dfe 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -243,6 +243,15 @@ config SDM_CAMCC_845
Support for the camera clock controller on SDM845 devices.
Say Y if you want to support camera devices and camera functionality.
+config SDM_GCC_660
+ tristate "SDM660 Global Clock Controller"
+ select QCOM_GDSC
+ depends on COMMON_CLK_QCOM
+ help
+ Support for the global clock controller on SDM660 devices.
+ Say Y if you want to use peripheral devices such as UART, SPI,
+ i2C, USB, UFS, SDDC, PCIe, etc.
+
config SDM_GCC_845
tristate "SDM845 Global Clock Controller"
select QCOM_GDSC
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 935f142bc155..ab892f6d847c 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o
obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o
obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
+obj-$(CONFIG_SDM_GCC_660) += gcc-sdm660.o
obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
new file mode 100644
index 000000000000..641bba611b5f
--- /dev/null
+++ b/drivers/clk/qcom/gcc-sdm660.c
@@ -0,0 +1,2480 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018, Craig Tatlor.
+ */
+
+#include <linux/kernel.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/clock/qcom,gcc-sdm660.h>
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-alpha-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "reset.h"
+#include "gdsc.h"
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+enum {
+ P_XO,
+ P_SLEEP_CLK,
+ P_GPLL0,
+ P_GPLL1,
+ P_GPLL4,
+ P_GPLL0_EARLY_DIV,
+ P_GPLL1_EARLY_DIV,
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_EARLY_DIV, 6 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div[] = {
+ "xo",
+ "gpll0",
+ "gpll0_early_div",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0[] = {
+ "xo",
+ "gpll0",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_SLEEP_CLK, 5 },
+ { P_GPLL0_EARLY_DIV, 6 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div[] = {
+ "xo",
+ "gpll0",
+ "sleep_clk",
+ "gpll0_early_div",
+};
+
+static const struct parent_map gcc_parent_map_xo_sleep_clk[] = {
+ { P_XO, 0 },
+ { P_SLEEP_CLK, 5 },
+};
+
+static const char * const gcc_parent_names_xo_sleep_clk[] = {
+ "xo",
+ "sleep_clk",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll4[] = {
+ { P_XO, 0 },
+ { P_GPLL4, 5 },
+};
+
+static const char * const gcc_parent_names_xo_gpll4[] = {
+ "xo",
+ "gpll4",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_EARLY_DIV, 3 },
+ { P_GPLL1, 4 },
+ { P_GPLL4, 5 },
+ { P_GPLL1_EARLY_DIV, 6 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
+ "xo",
+ "gpll0",
+ "gpll0_early_div",
+ "gpll1",
+ "gpll4",
+ "gpll1_early_div",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL4, 5 },
+ { P_GPLL0_EARLY_DIV, 6 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div[] = {
+ "xo",
+ "gpll0",
+ "gpll4",
+ "gpll0_early_div",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_EARLY_DIV, 2 },
+ { P_GPLL4, 5 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4[] = {
+ "xo",
+ "gpll0",
+ "gpll0_early_div",
+ "gpll4",
+};
+
+static struct clk_fixed_factor xo = {
+ .mult = 1,
+ .div = 1,
+ .hw.init = &(struct clk_init_data){
+ .name = "xo",
+ .parent_names = (const char *[]){ "xo_board" },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll0_early = {
+ .offset = 0x0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_early",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor gpll0_early_div = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_early_div",
+ .parent_names = (const char *[]){ "gpll0_early" },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll0 = {
+ .offset = 0x00000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll0",
+ .parent_names = (const char *[]){ "gpll0_early" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll1_early = {
+ .offset = 0x1000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll1_early",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor gpll1_early_div = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll1_early_div",
+ .parent_names = (const char *[]){ "gpll1_early" },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll1 = {
+ .offset = 0x1000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll1",
+ .parent_names = (const char *[]){ "gpll1_early" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll4_early = {
+ .offset = 0x77000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll4_early",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll4 = {
+ .offset = 0x77000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "gpll4",
+ .parent_names = (const char *[]) { "gpll4_early" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(50000000, P_GPLL0, 12, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x19020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup1_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(50000000, P_GPLL0, 12, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
+ .cmd_rcgr = 0x1900c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup1_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x1b020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup2_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
+ .cmd_rcgr = 0x1b00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup2_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x1d020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup3_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
+ .cmd_rcgr = 0x1d00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup3_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x1f020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup4_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
+ .cmd_rcgr = 0x1f00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup4_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
+ F(3686400, P_GPLL0, 1, 96, 15625),
+ F(7372800, P_GPLL0, 1, 192, 15625),
+ F(14745600, P_GPLL0, 1, 384, 15625),
+ F(16000000, P_GPLL0, 5, 2, 15),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 5, 1, 5),
+ F(32000000, P_GPLL0, 1, 4, 75),
+ F(40000000, P_GPLL0, 15, 0, 0),
+ F(46400000, P_GPLL0, 1, 29, 375),
+ F(48000000, P_GPLL0, 12.5, 0, 0),
+ F(51200000, P_GPLL0, 1, 32, 375),
+ F(56000000, P_GPLL0, 1, 7, 75),
+ F(58982400, P_GPLL0, 1, 1536, 15625),
+ F(60000000, P_GPLL0, 10, 0, 0),
+ F(63157895, P_GPLL0, 9.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
+ .cmd_rcgr = 0x1a00c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart1_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
+ .cmd_rcgr = 0x1c00c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart2_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x26020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup1_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
+ .cmd_rcgr = 0x2600c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup1_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x28020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup2_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
+ .cmd_rcgr = 0x2800c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup2_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x2a020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup3_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
+ .cmd_rcgr = 0x2a00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup3_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x2c020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup4_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
+ .cmd_rcgr = 0x2c00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup4_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
+ .cmd_rcgr = 0x2700c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_uart1_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
+ .cmd_rcgr = 0x2900c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_uart2_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gp1_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gp1_clk_src = {
+ .cmd_rcgr = 0x64004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
+ .freq_tbl = ftbl_gp1_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp1_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gp2_clk_src = {
+ .cmd_rcgr = 0x65004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
+ .freq_tbl = ftbl_gp1_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp2_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gp3_clk_src = {
+ .cmd_rcgr = 0x66004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
+ .freq_tbl = ftbl_gp1_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp3_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] = {
+ F(300000000, P_GPLL0, 2, 0, 0),
+ F(600000000, P_GPLL0, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 hmss_gpll0_clk_src = {
+ .cmd_rcgr = 0x4805c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_hmss_gpll0_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "hmss_gpll0_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_hmss_gpll4_clk_src[] = {
+ F(384000000, P_GPLL4, 4, 0, 0),
+ F(768000000, P_GPLL4, 2, 0, 0),
+ F(1536000000, P_GPLL4, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 hmss_gpll4_clk_src = {
+ .cmd_rcgr = 0x48074,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll4,
+ .freq_tbl = ftbl_hmss_gpll4_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "hmss_gpll4_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll4,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 hmss_rbcpr_clk_src = {
+ .cmd_rcgr = 0x48044,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_hmss_rbcpr_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "hmss_rbcpr_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_pdm2_clk_src[] = {
+ F(60000000, P_GPLL0, 10, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 pdm2_clk_src = {
+ .cmd_rcgr = 0x33010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_pdm2_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pdm2_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(80200000, P_GPLL1_EARLY_DIV, 5, 0, 0),
+ F(160400000, P_GPLL1, 5, 0, 0),
+ F(267333333, P_GPLL1, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 qspi_ser_clk_src = {
+ .cmd_rcgr = 0x4d00c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
+ .freq_tbl = ftbl_qspi_ser_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "qspi_ser_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
+ .num_parents = 6,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
+ F(144000, P_XO, 16, 3, 25),
+ F(400000, P_XO, 12, 1, 4),
+ F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
+ F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
+ F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(192000000, P_GPLL4, 8, 0, 0),
+ F(384000000, P_GPLL4, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 sdcc1_apps_clk_src = {
+ .cmd_rcgr = 0x1602c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div,
+ .freq_tbl = ftbl_sdcc1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc1_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
+ F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ F(300000000, P_GPLL0, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 sdcc1_ice_core_clk_src = {
+ .cmd_rcgr = 0x16010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc1_ice_core_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
+ F(144000, P_XO, 16, 3, 25),
+ F(400000, P_XO, 12, 1, 4),
+ F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
+ F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
+ F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(192000000, P_GPLL4, 8, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 sdcc2_apps_clk_src = {
+ .cmd_rcgr = 0x14010,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4,
+ .freq_tbl = ftbl_sdcc2_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc2_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
+ F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ F(240000000, P_GPLL0, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ufs_axi_clk_src = {
+ .cmd_rcgr = 0x75018,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_ufs_axi_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ufs_axi_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
+ F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ F(300000000, P_GPLL0, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ufs_ice_core_clk_src = {
+ .cmd_rcgr = 0x76010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_ufs_ice_core_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ufs_ice_core_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 ufs_phy_aux_clk_src = {
+ .cmd_rcgr = 0x76044,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_sleep_clk,
+ .freq_tbl = ftbl_hmss_rbcpr_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ufs_phy_aux_clk_src",
+ .parent_names = gcc_parent_names_xo_sleep_clk,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = {
+ F(37500000, P_GPLL0_EARLY_DIV, 8, 0, 0),
+ F(75000000, P_GPLL0, 8, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ufs_unipro_core_clk_src = {
+ .cmd_rcgr = 0x76028,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_ufs_unipro_core_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ufs_unipro_core_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(60000000, P_GPLL0, 10, 0, 0),
+ F(120000000, P_GPLL0, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb20_master_clk_src = {
+ .cmd_rcgr = 0x2f010,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_usb20_master_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb20_master_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb20_mock_utmi_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(60000000, P_GPLL0, 10, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb20_mock_utmi_clk_src = {
+ .cmd_rcgr = 0x2f024,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_usb20_mock_utmi_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb20_mock_utmi_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(66666667, P_GPLL0_EARLY_DIV, 4.5, 0, 0),
+ F(120000000, P_GPLL0, 5, 0, 0),
+ F(133333333, P_GPLL0, 4.5, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ F(240000000, P_GPLL0, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb30_master_clk_src = {
+ .cmd_rcgr = 0xf014,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_usb30_master_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb30_master_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(40000000, P_GPLL0_EARLY_DIV, 7.5, 0, 0),
+ F(60000000, P_GPLL0, 10, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb30_mock_utmi_clk_src = {
+ .cmd_rcgr = 0xf028,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb30_mock_utmi_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
+ F(1200000, P_XO, 16, 0, 0),
+ F(19200000, P_XO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb3_phy_aux_clk_src = {
+ .cmd_rcgr = 0x5000c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_sleep_clk,
+ .freq_tbl = ftbl_usb3_phy_aux_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb3_phy_aux_clk_src",
+ .parent_names = gcc_parent_names_xo_sleep_clk,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_branch gcc_aggre2_ufs_axi_clk = {
+ .halt_reg = 0x75034,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x75034,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_aggre2_ufs_axi_clk",
+ .parent_names = (const char *[]){
+ "ufs_axi_clk_src",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_aggre2_usb3_axi_clk = {
+ .halt_reg = 0xf03c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf03c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_aggre2_usb3_axi_clk",
+ .parent_names = (const char *[]){
+ "usb30_master_clk_src",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_bimc_gfx_clk = {
+ .halt_reg = 0x7106c,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x7106c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_bimc_gfx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_bimc_hmss_axi_clk = {
+ .halt_reg = 0x48004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(22),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_bimc_hmss_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
+ .halt_reg = 0x4401c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4401c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_bimc_mss_q6_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_ahb_clk = {
+ .halt_reg = 0x17004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(17),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
+ .halt_reg = 0x19008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x19008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup1_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup1_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
+ .halt_reg = 0x19004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x19004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup1_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup1_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
+ .halt_reg = 0x1b008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1b008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup2_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup2_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
+ .halt_reg = 0x1b004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1b004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup2_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup2_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
+ .halt_reg = 0x1d008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1d008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup3_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup3_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
+ .halt_reg = 0x1d004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1d004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup3_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup3_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
+ .halt_reg = 0x1f008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1f008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup4_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup4_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
+ .halt_reg = 0x1f004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1f004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup4_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup4_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart1_apps_clk = {
+ .halt_reg = 0x1a004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart1_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_uart1_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart2_apps_clk = {
+ .halt_reg = 0x1c004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1c004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart2_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_uart2_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_ahb_clk = {
+ .halt_reg = 0x25004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(15),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
+ .halt_reg = 0x26008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x26008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup1_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup1_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
+ .halt_reg = 0x26004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x26004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup1_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup1_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
+ .halt_reg = 0x28008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup2_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup2_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
+ .halt_reg = 0x28004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup2_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup2_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
+ .halt_reg = 0x2a008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2a008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup3_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup3_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
+ .halt_reg = 0x2a004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup3_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup3_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
+ .halt_reg = 0x2c008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2c008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup4_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup4_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
+ .halt_reg = 0x2c004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2c004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup4_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup4_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_uart1_apps_clk = {
+ .halt_reg = 0x27004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x27004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_uart1_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_uart1_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_uart2_apps_clk = {
+ .halt_reg = 0x29004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x29004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_uart2_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_uart2_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_boot_rom_ahb_clk = {
+ .halt_reg = 0x38004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(10),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_boot_rom_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cfg_noc_usb2_axi_clk = {
+ .halt_reg = 0x5058,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5058,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_cfg_noc_usb2_axi_clk",
+ .parent_names = (const char *[]){
+ "usb20_master_clk_src",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
+ .halt_reg = 0x5018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_cfg_noc_usb3_axi_clk",
+ .parent_names = (const char *[]){
+ "usb30_master_clk_src",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_dcc_ahb_clk = {
+ .halt_reg = 0x84004,
+ .clkr = {
+ .enable_reg = 0x84004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_dcc_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp1_clk = {
+ .halt_reg = 0x64000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x64000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp1_clk",
+ .parent_names = (const char *[]){
+ "gp1_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp2_clk = {
+ .halt_reg = 0x65000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x65000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp2_clk",
+ .parent_names = (const char *[]){
+ "gp2_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp3_clk = {
+ .halt_reg = 0x66000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x66000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp3_clk",
+ .parent_names = (const char *[]){
+ "gp3_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_bimc_gfx_clk = {
+ .halt_reg = 0x71010,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x71010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_bimc_gfx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_cfg_ahb_clk = {
+ .halt_reg = 0x71004,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x71004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_gpll0_clk = {
+ .halt_reg = 0x5200c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_gpll0_clk",
+ .parent_names = (const char *[]){
+ "gpll0",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_gpll0_div_clk = {
+ .halt_reg = 0x5200c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(3),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_gpll0_div_clk",
+ .parent_names = (const char *[]){
+ "gpll0_early_div",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_hmss_dvm_bus_clk = {
+ .halt_reg = 0x4808c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4808c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_hmss_dvm_bus_clk",
+ .ops = &clk_branch2_ops,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ },
+};
+
+static struct clk_branch gcc_hmss_rbcpr_clk = {
+ .halt_reg = 0x48008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x48008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_hmss_rbcpr_clk",
+ .parent_names = (const char *[]){
+ "hmss_rbcpr_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mmss_gpll0_clk = {
+ .halt_reg = 0x5200c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mmss_gpll0_clk",
+ .parent_names = (const char *[]){
+ "gpll0",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mmss_gpll0_div_clk = {
+ .halt_reg = 0x5200c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mmss_gpll0_div_clk",
+ .parent_names = (const char *[]){
+ "gpll0_early_div",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
+ .halt_reg = 0x9004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mmss_noc_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
+ .halt_reg = 0x9000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mmss_sys_noc_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mss_cfg_ahb_clk = {
+ .halt_reg = 0x8a000,
+ .clkr = {
+ .enable_reg = 0x8a000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mss_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
+ .halt_reg = 0x8a004,
+ .clkr = {
+ .enable_reg = 0x8a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mss_mnoc_bimc_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
+ .halt_reg = 0x8a040,
+ .clkr = {
+ .enable_reg = 0x8a040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mss_q6_bimc_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mss_snoc_axi_clk = {
+ .halt_reg = 0x8a03c,
+ .clkr = {
+ .enable_reg = 0x8a03c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mss_snoc_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pdm2_clk = {
+ .halt_reg = 0x3300c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3300c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pdm2_clk",
+ .parent_names = (const char *[]){
+ "pdm2_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pdm_ahb_clk = {
+ .halt_reg = 0x33004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x33004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pdm_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_prng_ahb_clk = {
+ .halt_reg = 0x34004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(13),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_prng_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qspi_ahb_clk = {
+ .halt_reg = 0x4d004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4d004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qspi_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qspi_ser_clk = {
+ .halt_reg = 0x4d008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4d008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qspi_ser_clk",
+ .parent_names = (const char *[]){
+ "qspi_ser_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_rx0_usb2_clkref_clk = {
+ .halt_reg = 0x88018,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x88018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_rx0_usb2_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_rx1_usb2_clkref_clk = {
+ .halt_reg = 0x88014,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x88014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_rx1_usb2_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_ahb_clk = {
+ .halt_reg = 0x16008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x16008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_apps_clk = {
+ .halt_reg = 0x16004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x16004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_apps_clk",
+ .parent_names = (const char *[]){
+ "sdcc1_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_ice_core_clk = {
+ .halt_reg = 0x1600c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1600c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_ice_core_clk",
+ .parent_names = (const char *[]){
+ "sdcc1_ice_core_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc2_ahb_clk = {
+ .halt_reg = 0x14008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x14008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc2_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc2_apps_clk = {
+ .halt_reg = 0x14004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x14004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc2_apps_clk",
+ .parent_names = (const char *[]){
+ "sdcc2_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_ahb_clk = {
+ .halt_reg = 0x7500c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x7500c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_axi_clk = {
+ .halt_reg = 0x75008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x75008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_axi_clk",
+ .parent_names = (const char *[]){
+ "ufs_axi_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_clkref_clk = {
+ .halt_reg = 0x88008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x88008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_ice_core_clk = {
+ .halt_reg = 0x7600c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x7600c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_ice_core_clk",
+ .parent_names = (const char *[]){
+ "ufs_ice_core_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_phy_aux_clk = {
+ .halt_reg = 0x76040,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x76040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_phy_aux_clk",
+ .parent_names = (const char *[]){
+ "ufs_phy_aux_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
+ .halt_reg = 0x75014,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x75014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_rx_symbol_0_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
+ .halt_reg = 0x7605c,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x7605c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_rx_symbol_1_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
+ .halt_reg = 0x75010,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x75010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_tx_symbol_0_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_unipro_core_clk = {
+ .halt_reg = 0x76008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x76008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_unipro_core_clk",
+ .parent_names = (const char *[]){
+ "ufs_unipro_core_clk_src",
+ },
+ .flags = CLK_SET_RATE_PARENT,
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb20_master_clk = {
+ .halt_reg = 0x2f004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2f004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb20_master_clk",
+ .parent_names = (const char *[]){
+ "usb20_master_clk_src"
+ },
+ .flags = CLK_SET_RATE_PARENT,
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb20_mock_utmi_clk = {
+ .halt_reg = 0x2f00c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2f00c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb20_mock_utmi_clk",
+ .parent_names = (const char *[]){
+ "usb20_mock_utmi_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb20_sleep_clk = {
+ .halt_reg = 0x2f008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2f008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb20_sleep_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_master_clk = {
+ .halt_reg = 0xf008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb30_master_clk",
+ .parent_names = (const char *[]){
+ "usb30_master_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_mock_utmi_clk = {
+ .halt_reg = 0xf010,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb30_mock_utmi_clk",
+ .parent_names = (const char *[]){
+ "usb30_mock_utmi_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_sleep_clk = {
+ .halt_reg = 0xf00c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf00c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb30_sleep_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_clkref_clk = {
+ .halt_reg = 0x8800c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x8800c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb3_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_phy_aux_clk = {
+ .halt_reg = 0x50000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x50000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb3_phy_aux_clk",
+ .parent_names = (const char *[]){
+ "usb3_phy_aux_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_phy_pipe_clk = {
+ .halt_reg = 0x50004,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x50004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb3_phy_pipe_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
+ .halt_reg = 0x6a004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb_phy_cfg_ahb2phy_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct gdsc ufs_gdsc = {
+ .gdscr = 0x75004,
+ .gds_hw_ctrl = 0x0,
+ .pd = {
+ .name = "ufs_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc usb_30_gdsc = {
+ .gdscr = 0xf004,
+ .gds_hw_ctrl = 0x0,
+ .pd = {
+ .name = "usb_30_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc pcie_0_gdsc = {
+ .gdscr = 0x6b004,
+ .gds_hw_ctrl = 0x0,
+ .pd = {
+ .name = "pcie_0_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct clk_hw *gcc_sdm660_hws[] = {
+ [GCC_XO] = &xo.hw,
+ [GCC_GPLL0_EARLY_DIV] = &gpll0_early_div.hw,
+ [GCC_GPLL1_EARLY_DIV] = &gpll1_early_div.hw,
+};
+
+static struct clk_regmap *gcc_660_clocks[] = {
+ [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
+ [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
+ [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
+ [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
+ [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
+ [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
+ [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
+ [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
+ [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
+ [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
+ [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
+ [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
+ [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
+ [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
+ [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
+ [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,
+ [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,
+ [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
+ [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
+ [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
+ [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
+ [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
+ [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
+ [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
+ [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
+ [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
+ [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
+ [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
+ [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
+ [GCC_CFG_NOC_USB2_AXI_CLK] = &gcc_cfg_noc_usb2_axi_clk.clkr,
+ [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,
+ [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
+ [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
+ [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
+ [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
+ [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
+ [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
+ [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,
+ [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,
+ [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr,
+ [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
+ [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,
+ [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
+ [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
+ [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,
+ [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
+ [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
+ [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
+ [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
+ [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
+ [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
+ [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
+ [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
+ [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
+ [GCC_RX0_USB2_CLKREF_CLK] = &gcc_rx0_usb2_clkref_clk.clkr,
+ [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
+ [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
+ [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
+ [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
+ [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
+ [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
+ [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
+ [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
+ [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
+ [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
+ [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,
+ [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
+ [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
+ [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
+ [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
+ [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
+ [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
+ [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
+ [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
+ [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
+ [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
+ [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
+ [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
+ [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
+ [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
+ [GP1_CLK_SRC] = &gp1_clk_src.clkr,
+ [GP2_CLK_SRC] = &gp2_clk_src.clkr,
+ [GP3_CLK_SRC] = &gp3_clk_src.clkr,
+ [GPLL0] = &gpll0.clkr,
+ [GPLL0_EARLY] = &gpll0_early.clkr,
+ [GPLL1] = &gpll1.clkr,
+ [GPLL1_EARLY] = &gpll1_early.clkr,
+ [GPLL1] = &gpll1.clkr,
+ [GPLL4_EARLY] = &gpll4_early.clkr,
+ [GPLL4] = &gpll4.clkr,
+ [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
+ [HMSS_GPLL4_CLK_SRC] = &hmss_gpll4_clk_src.clkr,
+ [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
+ [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
+ [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
+ [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
+ [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
+ [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
+ [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
+ [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
+ [UFS_PHY_AUX_CLK_SRC] = &ufs_phy_aux_clk_src.clkr,
+ [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr,
+ [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
+ [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
+ [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
+ [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
+ [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
+};
+
+static struct gdsc *gcc_660_gdscs[] = {
+ [UFS_GDSC] = &ufs_gdsc,
+ [USB_30_GDSC] = &usb_30_gdsc,
+ [PCIE_0_GDSC] = &pcie_0_gdsc,
+};
+
+static const struct qcom_reset_map gcc_660_resets[] = {
+ [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
+ [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
+ [GCC_UFS_BCR] = { 0x75000 },
+ [GCC_USB3_DP_PHY_BCR] = { 0x50028 },
+ [GCC_USB3_PHY_BCR] = { 0x50020 },
+ [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
+ [GCC_USB_20_BCR] = { 0x2f000 },
+ [GCC_USB_30_BCR] = { 0xf000 },
+ [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
+};
+
+static const struct regmap_config gcc_660_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x94000,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc gcc_660_desc = {
+ .config = &gcc_660_regmap_config,
+ .clks = gcc_660_clocks,
+ .num_clks = ARRAY_SIZE(gcc_660_clocks),
+ .resets = gcc_660_resets,
+ .num_resets = ARRAY_SIZE(gcc_660_resets),
+ .gdscs = gcc_660_gdscs,
+ .num_gdscs = ARRAY_SIZE(gcc_660_gdscs),
+};
+
+static const struct of_device_id gcc_660_match_table[] = {
+ { .compatible = "qcom,gcc-sdm630" },
+ { .compatible = "qcom,gcc-sdm660" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, gcc_660_match_table);
+
+static int gcc_660_probe(struct platform_device *pdev)
+{
+ int i, ret = 0;
+ struct regmap *regmap;
+
+ regmap = qcom_cc_map(pdev, &gcc_660_desc);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ /*
+ * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
+ * turned off by hardware during certain apps low power modes.
+ */
+ ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
+ if (ret)
+ return ret;
+
+ /* Register the hws */
+ for (i = 0; i < ARRAY_SIZE(gcc_sdm660_hws); i++) {
+ ret = devm_clk_hw_register(&pdev->dev, gcc_sdm660_hws[i]);
+ if (ret)
+ return ret;
+ }
+
+ return qcom_cc_really_probe(pdev, &gcc_660_desc, regmap);
+}
+
+static struct platform_driver gcc_660_driver = {
+ .probe = gcc_660_probe,
+ .driver = {
+ .name = "gcc-sdm660",
+ .of_match_table = gcc_660_match_table,
+ },
+};
+
+static int __init gcc_660_init(void)
+{
+ return platform_driver_register(&gcc_660_driver);
+}
+core_initcall_sync(gcc_660_init);
+
+static void __exit gcc_660_exit(void)
+{
+ platform_driver_unregister(&gcc_660_driver);
+}
+module_exit(gcc_660_exit);
+
+MODULE_DESCRIPTION("QCOM GCC sdm660 Driver");
diff --git a/include/dt-bindings/clock/qcom,gcc-sdm660.h b/include/dt-bindings/clock/qcom,gcc-sdm660.h
new file mode 100644
index 000000000000..76aabcc5e7e3
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sdm660.h
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018, Craig Tatlor.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H
+#define _DT_BINDINGS_CLK_MSM_GCC_660_H
+
+#define GCC_XO 0
+#define GCC_GPLL0_EARLY_DIV 1
+#define GCC_GPLL1_EARLY_DIV 2
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 3
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 4
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 5
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 6
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 7
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 8
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC 9
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC 10
+#define BLSP1_UART1_APPS_CLK_SRC 11
+#define BLSP1_UART2_APPS_CLK_SRC 12
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC 13
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC 14
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC 15
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC 16
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC 17
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC 18
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC 19
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC 20
+#define BLSP2_UART1_APPS_CLK_SRC 21
+#define BLSP2_UART2_APPS_CLK_SRC 22
+#define GCC_AGGRE2_UFS_AXI_CLK 23
+#define GCC_AGGRE2_USB3_AXI_CLK 24
+#define GCC_BIMC_GFX_CLK 25
+#define GCC_BIMC_HMSS_AXI_CLK 26
+#define GCC_BIMC_MSS_Q6_AXI_CLK 27
+#define GCC_BLSP1_AHB_CLK 28
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 29
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 30
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 31
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 32
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 33
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 34
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 35
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 36
+#define GCC_BLSP1_UART1_APPS_CLK 37
+#define GCC_BLSP1_UART2_APPS_CLK 38
+#define GCC_BLSP2_AHB_CLK 39
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK 40
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK 41
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK 42
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK 43
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK 44
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK 46
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK 45
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK 46
+#define GCC_BLSP2_UART1_APPS_CLK 47
+#define GCC_BLSP2_UART2_APPS_CLK 48
+#define GCC_BOOT_ROM_AHB_CLK 49
+#define GCC_CFG_NOC_USB2_AXI_CLK 50
+#define GCC_CFG_NOC_USB3_AXI_CLK 51
+#define GCC_DCC_AHB_CLK 52
+#define GCC_GP1_CLK 53
+#define GCC_GP2_CLK 54
+#define GCC_GP3_CLK 55
+#define GCC_GPU_BIMC_GFX_CLK 56
+#define GCC_GPU_CFG_AHB_CLK 57
+#define GCC_GPU_GPLL0_CLK 58
+#define GCC_GPU_GPLL0_DIV_CLK 59
+#define GCC_HMSS_DVM_BUS_CLK 60
+#define GCC_HMSS_RBCPR_CLK 61
+#define GCC_MMSS_GPLL0_CLK 62
+#define GCC_MMSS_GPLL0_DIV_CLK 63
+#define GCC_MMSS_NOC_CFG_AHB_CLK 64
+#define GCC_MMSS_SYS_NOC_AXI_CLK 65
+#define GCC_MSS_CFG_AHB_CLK 66
+#define GCC_MSS_GPLL0_DIV_CLK 67
+#define GCC_MSS_MNOC_BIMC_AXI_CLK 68
+#define GCC_MSS_Q6_BIMC_AXI_CLK 69
+#define GCC_MSS_SNOC_AXI_CLK 70
+#define GCC_PDM2_CLK 71
+#define GCC_PDM_AHB_CLK 72
+#define GCC_PRNG_AHB_CLK 73
+#define GCC_QSPI_AHB_CLK 74
+#define GCC_QSPI_SER_CLK 75
+#define GCC_SDCC1_AHB_CLK 76
+#define GCC_SDCC1_APPS_CLK 77
+#define GCC_SDCC1_ICE_CORE_CLK 78
+#define GCC_SDCC2_AHB_CLK 79
+#define GCC_SDCC2_APPS_CLK 80
+#define GCC_UFS_AHB_CLK 81
+#define GCC_UFS_AXI_CLK 82
+#define GCC_UFS_CLKREF_CLK 83
+#define GCC_UFS_ICE_CORE_CLK 84
+#define GCC_UFS_PHY_AUX_CLK 85
+#define GCC_UFS_RX_SYMBOL_0_CLK 86
+#define GCC_UFS_RX_SYMBOL_1_CLK 87
+#define GCC_UFS_TX_SYMBOL_0_CLK 88
+#define GCC_UFS_UNIPRO_CORE_CLK 89
+#define GCC_USB20_MASTER_CLK 90
+#define GCC_USB20_MOCK_UTMI_CLK 91
+#define GCC_USB20_SLEEP_CLK 92
+#define GCC_USB30_MASTER_CLK 93
+#define GCC_USB30_MOCK_UTMI_CLK 94
+#define GCC_USB30_SLEEP_CLK 95
+#define GCC_USB3_CLKREF_CLK 96
+#define GCC_USB3_PHY_AUX_CLK 97
+#define GCC_USB3_PHY_PIPE_CLK 98
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK 99
+#define GP1_CLK_SRC 100
+#define GP2_CLK_SRC 101
+#define GP3_CLK_SRC 102
+#define GPLL0 103
+#define GPLL0_EARLY 104
+#define GPLL1 105
+#define GPLL1_EARLY 106
+#define GPLL4 107
+#define GPLL4_EARLY 108
+#define HMSS_GPLL0_CLK_SRC 109
+#define HMSS_GPLL4_CLK_SRC 110
+#define HMSS_RBCPR_CLK_SRC 111
+#define PDM2_CLK_SRC 112
+#define QSPI_SER_CLK_SRC 113
+#define SDCC1_APPS_CLK_SRC 114
+#define SDCC1_ICE_CORE_CLK_SRC 115
+#define SDCC2_APPS_CLK_SRC 116
+#define UFS_AXI_CLK_SRC 117
+#define UFS_ICE_CORE_CLK_SRC 118
+#define UFS_PHY_AUX_CLK_SRC 119
+#define UFS_UNIPRO_CORE_CLK_SRC 120
+#define USB20_MASTER_CLK_SRC 121
+#define USB20_MOCK_UTMI_CLK_SRC 122
+#define USB30_MASTER_CLK_SRC 123
+#define USB30_MOCK_UTMI_CLK_SRC 124
+#define USB3_PHY_AUX_CLK_SRC 125
+#define GPLL0_OUT_MSSCC 126
+#define GCC_UFS_AXI_HW_CTL_CLK 127
+#define GCC_UFS_ICE_CORE_HW_CTL_CLK 128
+#define GCC_UFS_PHY_AUX_HW_CTL_CLK 129
+#define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 130
+#define GCC_RX0_USB2_CLKREF_CLK 131
+#define GCC_RX1_USB2_CLKREF_CLK 132
+
+#define PCIE_0_GDSC 0
+#define UFS_GDSC 1
+#define USB_30_GDSC 2
+
+#define GCC_QUSB2PHY_PRIM_BCR 0
+#define GCC_QUSB2PHY_SEC_BCR 1
+#define GCC_UFS_BCR 2
+#define GCC_USB3_DP_PHY_BCR 3
+#define GCC_USB3_PHY_BCR 4
+#define GCC_USB3PHY_PHY_BCR 5
+#define GCC_USB_20_BCR 6
+#define GCC_USB_30_BCR 7
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR 8
+
+#endif
--
2.18.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3] clk: qcom: Add Global Clock controller (GCC) driver for SDM660
2018-09-25 17:35 ` [PATCH v3] " Craig Tatlor
@ 2018-09-25 17:35 ` Craig Tatlor
2018-09-27 19:51 ` Rob Herring
` (2 subsequent siblings)
3 siblings, 0 replies; 18+ messages in thread
From: Craig Tatlor @ 2018-09-25 17:35 UTC (permalink / raw)
Cc: ctatlor97, linux-arm-msm, Taniya Das, Michael Turquette,
Stephen Boyd, Rob Herring, Mark Rutland, Andy Gross, David Brown,
linux-clk, devicetree, linux-kernel, linux-soc
From: Taniya Das <tdas@codeaurora.org>
Add support for the global clock controller found on SDM660
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Based on CAF implementation.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
[craig: rename parents to fit upstream, and other cleanups]
Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
---
Changes from V1:
Change authorship
Add sdm630 compatible
.../devicetree/bindings/clock/qcom,gcc.txt | 1 +
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-sdm660.c | 2480 +++++++++++++++++
include/dt-bindings/clock/qcom,gcc-sdm660.h | 159 ++
5 files changed, 2650 insertions(+)
create mode 100644 drivers/clk/qcom/gcc-sdm660.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-sdm660.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
index 664ea1fd6c76..e498ad2e8db8 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
@@ -38,6 +38,8 @@ Required properties :
"qcom,gcc-msm8996"
"qcom,gcc-msm8998"
"qcom,gcc-mdm9615"
+ "qcom,gcc-sdm630"
+ "qcom,gcc-sdm660"
"qcom,gcc-sdm845"
- reg : shall contain base register location and length
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 5b181b182f40..4d478b261dfe 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -243,6 +243,15 @@ config SDM_CAMCC_845
Support for the camera clock controller on SDM845 devices.
Say Y if you want to support camera devices and camera functionality.
+config SDM_GCC_660
+ tristate "SDM660 Global Clock Controller"
+ select QCOM_GDSC
+ depends on COMMON_CLK_QCOM
+ help
+ Support for the global clock controller on SDM660 devices.
+ Say Y if you want to use peripheral devices such as UART, SPI,
+ i2C, USB, UFS, SDDC, PCIe, etc.
+
config SDM_GCC_845
tristate "SDM845 Global Clock Controller"
select QCOM_GDSC
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 935f142bc155..ab892f6d847c 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o
obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o
obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
+obj-$(CONFIG_SDM_GCC_660) += gcc-sdm660.o
obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
new file mode 100644
index 000000000000..641bba611b5f
--- /dev/null
+++ b/drivers/clk/qcom/gcc-sdm660.c
@@ -0,0 +1,2480 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018, Craig Tatlor.
+ */
+
+#include <linux/kernel.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/clock/qcom,gcc-sdm660.h>
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-alpha-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "reset.h"
+#include "gdsc.h"
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+enum {
+ P_XO,
+ P_SLEEP_CLK,
+ P_GPLL0,
+ P_GPLL1,
+ P_GPLL4,
+ P_GPLL0_EARLY_DIV,
+ P_GPLL1_EARLY_DIV,
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_EARLY_DIV, 6 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div[] = {
+ "xo",
+ "gpll0",
+ "gpll0_early_div",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0[] = {
+ "xo",
+ "gpll0",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_SLEEP_CLK, 5 },
+ { P_GPLL0_EARLY_DIV, 6 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div[] = {
+ "xo",
+ "gpll0",
+ "sleep_clk",
+ "gpll0_early_div",
+};
+
+static const struct parent_map gcc_parent_map_xo_sleep_clk[] = {
+ { P_XO, 0 },
+ { P_SLEEP_CLK, 5 },
+};
+
+static const char * const gcc_parent_names_xo_sleep_clk[] = {
+ "xo",
+ "sleep_clk",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll4[] = {
+ { P_XO, 0 },
+ { P_GPLL4, 5 },
+};
+
+static const char * const gcc_parent_names_xo_gpll4[] = {
+ "xo",
+ "gpll4",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_EARLY_DIV, 3 },
+ { P_GPLL1, 4 },
+ { P_GPLL4, 5 },
+ { P_GPLL1_EARLY_DIV, 6 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] = {
+ "xo",
+ "gpll0",
+ "gpll0_early_div",
+ "gpll1",
+ "gpll4",
+ "gpll1_early_div",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL4, 5 },
+ { P_GPLL0_EARLY_DIV, 6 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div[] = {
+ "xo",
+ "gpll0",
+ "gpll4",
+ "gpll0_early_div",
+};
+
+static const struct parent_map gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL0_EARLY_DIV, 2 },
+ { P_GPLL4, 5 },
+};
+
+static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4[] = {
+ "xo",
+ "gpll0",
+ "gpll0_early_div",
+ "gpll4",
+};
+
+static struct clk_fixed_factor xo = {
+ .mult = 1,
+ .div = 1,
+ .hw.init = &(struct clk_init_data){
+ .name = "xo",
+ .parent_names = (const char *[]){ "xo_board" },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll0_early = {
+ .offset = 0x0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_early",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor gpll0_early_div = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_early_div",
+ .parent_names = (const char *[]){ "gpll0_early" },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll0 = {
+ .offset = 0x00000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll0",
+ .parent_names = (const char *[]){ "gpll0_early" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll1_early = {
+ .offset = 0x1000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll1_early",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_fixed_factor gpll1_early_div = {
+ .mult = 1,
+ .div = 2,
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll1_early_div",
+ .parent_names = (const char *[]){ "gpll1_early" },
+ .num_parents = 1,
+ .ops = &clk_fixed_factor_ops,
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll1 = {
+ .offset = 0x1000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll1",
+ .parent_names = (const char *[]){ "gpll1_early" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ops,
+ },
+};
+
+static struct clk_alpha_pll gpll4_early = {
+ .offset = 0x77000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr = {
+ .enable_reg = 0x52000,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll4_early",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_ops,
+ },
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpll4 = {
+ .offset = 0x77000,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+ .clkr.hw.init = &(struct clk_init_data)
+ {
+ .name = "gpll4",
+ .parent_names = (const char *[]) { "gpll4_early" },
+ .num_parents = 1,
+ .ops = &clk_alpha_pll_postdiv_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(50000000, P_GPLL0, 12, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x19020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup1_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
+ F(960000, P_XO, 10, 1, 2),
+ F(4800000, P_XO, 4, 0, 0),
+ F(9600000, P_XO, 2, 0, 0),
+ F(15000000, P_GPLL0, 10, 1, 4),
+ F(19200000, P_XO, 1, 0, 0),
+ F(25000000, P_GPLL0, 12, 1, 2),
+ F(50000000, P_GPLL0, 12, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
+ .cmd_rcgr = 0x1900c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup1_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x1b020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup2_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
+ .cmd_rcgr = 0x1b00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup2_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x1d020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup3_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
+ .cmd_rcgr = 0x1d00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup3_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x1f020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup4_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
+ .cmd_rcgr = 0x1f00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_qup4_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
+ F(3686400, P_GPLL0, 1, 96, 15625),
+ F(7372800, P_GPLL0, 1, 192, 15625),
+ F(14745600, P_GPLL0, 1, 384, 15625),
+ F(16000000, P_GPLL0, 5, 2, 15),
+ F(19200000, P_XO, 1, 0, 0),
+ F(24000000, P_GPLL0, 5, 1, 5),
+ F(32000000, P_GPLL0, 1, 4, 75),
+ F(40000000, P_GPLL0, 15, 0, 0),
+ F(46400000, P_GPLL0, 1, 29, 375),
+ F(48000000, P_GPLL0, 12.5, 0, 0),
+ F(51200000, P_GPLL0, 1, 32, 375),
+ F(56000000, P_GPLL0, 1, 7, 75),
+ F(58982400, P_GPLL0, 1, 1536, 15625),
+ F(60000000, P_GPLL0, 10, 0, 0),
+ F(63157895, P_GPLL0, 9.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
+ .cmd_rcgr = 0x1a00c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart1_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
+ .cmd_rcgr = 0x1c00c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp1_uart2_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x26020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup1_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
+ .cmd_rcgr = 0x2600c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup1_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x28020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup2_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
+ .cmd_rcgr = 0x2800c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup2_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x2a020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup3_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
+ .cmd_rcgr = 0x2a00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup3_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
+ .cmd_rcgr = 0x2c020,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup4_i2c_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
+ .cmd_rcgr = 0x2c00c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_qup4_spi_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
+ .cmd_rcgr = 0x2700c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_uart1_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
+ .cmd_rcgr = 0x2900c,
+ .mnd_width = 16,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "blsp2_uart2_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_gp1_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 gp1_clk_src = {
+ .cmd_rcgr = 0x64004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
+ .freq_tbl = ftbl_gp1_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp1_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gp2_clk_src = {
+ .cmd_rcgr = 0x65004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
+ .freq_tbl = ftbl_gp1_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp2_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 gp3_clk_src = {
+ .cmd_rcgr = 0x66004,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
+ .freq_tbl = ftbl_gp1_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gp3_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] = {
+ F(300000000, P_GPLL0, 2, 0, 0),
+ F(600000000, P_GPLL0, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 hmss_gpll0_clk_src = {
+ .cmd_rcgr = 0x4805c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_hmss_gpll0_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "hmss_gpll0_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_hmss_gpll4_clk_src[] = {
+ F(384000000, P_GPLL4, 4, 0, 0),
+ F(768000000, P_GPLL4, 2, 0, 0),
+ F(1536000000, P_GPLL4, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 hmss_gpll4_clk_src = {
+ .cmd_rcgr = 0x48074,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll4,
+ .freq_tbl = ftbl_hmss_gpll4_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "hmss_gpll4_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll4,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 hmss_rbcpr_clk_src = {
+ .cmd_rcgr = 0x48044,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_hmss_rbcpr_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "hmss_rbcpr_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_pdm2_clk_src[] = {
+ F(60000000, P_GPLL0, 10, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 pdm2_clk_src = {
+ .cmd_rcgr = 0x33010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_pdm2_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pdm2_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(80200000, P_GPLL1_EARLY_DIV, 5, 0, 0),
+ F(160400000, P_GPLL1, 5, 0, 0),
+ F(267333333, P_GPLL1, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 qspi_ser_clk_src = {
+ .cmd_rcgr = 0x4d00c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
+ .freq_tbl = ftbl_qspi_ser_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "qspi_ser_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
+ .num_parents = 6,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
+ F(144000, P_XO, 16, 3, 25),
+ F(400000, P_XO, 12, 1, 4),
+ F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
+ F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
+ F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(192000000, P_GPLL4, 8, 0, 0),
+ F(384000000, P_GPLL4, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 sdcc1_apps_clk_src = {
+ .cmd_rcgr = 0x1602c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div,
+ .freq_tbl = ftbl_sdcc1_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc1_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
+ F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ F(300000000, P_GPLL0, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 sdcc1_ice_core_clk_src = {
+ .cmd_rcgr = 0x16010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc1_ice_core_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
+ F(144000, P_XO, 16, 3, 25),
+ F(400000, P_XO, 12, 1, 4),
+ F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
+ F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
+ F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(192000000, P_GPLL4, 8, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 sdcc2_apps_clk_src = {
+ .cmd_rcgr = 0x14010,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4,
+ .freq_tbl = ftbl_sdcc2_apps_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "sdcc2_apps_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4,
+ .num_parents = 4,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
+ F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
+ F(100000000, P_GPLL0, 6, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ F(240000000, P_GPLL0, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ufs_axi_clk_src = {
+ .cmd_rcgr = 0x75018,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_ufs_axi_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ufs_axi_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
+ F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ F(300000000, P_GPLL0, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ufs_ice_core_clk_src = {
+ .cmd_rcgr = 0x76010,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_ufs_ice_core_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ufs_ice_core_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 ufs_phy_aux_clk_src = {
+ .cmd_rcgr = 0x76044,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_sleep_clk,
+ .freq_tbl = ftbl_hmss_rbcpr_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ufs_phy_aux_clk_src",
+ .parent_names = gcc_parent_names_xo_sleep_clk,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = {
+ F(37500000, P_GPLL0_EARLY_DIV, 8, 0, 0),
+ F(75000000, P_GPLL0, 8, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 ufs_unipro_core_clk_src = {
+ .cmd_rcgr = 0x76028,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_ufs_unipro_core_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "ufs_unipro_core_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(60000000, P_GPLL0, 10, 0, 0),
+ F(120000000, P_GPLL0, 5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb20_master_clk_src = {
+ .cmd_rcgr = 0x2f010,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_usb20_master_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb20_master_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb20_mock_utmi_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(60000000, P_GPLL0, 10, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb20_mock_utmi_clk_src = {
+ .cmd_rcgr = 0x2f024,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_usb20_mock_utmi_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb20_mock_utmi_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(66666667, P_GPLL0_EARLY_DIV, 4.5, 0, 0),
+ F(120000000, P_GPLL0, 5, 0, 0),
+ F(133333333, P_GPLL0, 4.5, 0, 0),
+ F(150000000, P_GPLL0, 4, 0, 0),
+ F(200000000, P_GPLL0, 3, 0, 0),
+ F(240000000, P_GPLL0, 2.5, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb30_master_clk_src = {
+ .cmd_rcgr = 0xf014,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_usb30_master_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb30_master_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
+ F(19200000, P_XO, 1, 0, 0),
+ F(40000000, P_GPLL0_EARLY_DIV, 7.5, 0, 0),
+ F(60000000, P_GPLL0, 10, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb30_mock_utmi_clk_src = {
+ .cmd_rcgr = 0xf028,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
+ .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb30_mock_utmi_clk_src",
+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
+ .num_parents = 3,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
+ F(1200000, P_XO, 16, 0, 0),
+ F(19200000, P_XO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 usb3_phy_aux_clk_src = {
+ .cmd_rcgr = 0x5000c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_xo_sleep_clk,
+ .freq_tbl = ftbl_usb3_phy_aux_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "usb3_phy_aux_clk_src",
+ .parent_names = gcc_parent_names_xo_sleep_clk,
+ .num_parents = 2,
+ .ops = &clk_rcg2_ops,
+ },
+};
+
+static struct clk_branch gcc_aggre2_ufs_axi_clk = {
+ .halt_reg = 0x75034,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x75034,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_aggre2_ufs_axi_clk",
+ .parent_names = (const char *[]){
+ "ufs_axi_clk_src",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_aggre2_usb3_axi_clk = {
+ .halt_reg = 0xf03c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf03c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_aggre2_usb3_axi_clk",
+ .parent_names = (const char *[]){
+ "usb30_master_clk_src",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_bimc_gfx_clk = {
+ .halt_reg = 0x7106c,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x7106c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_bimc_gfx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_bimc_hmss_axi_clk = {
+ .halt_reg = 0x48004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(22),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_bimc_hmss_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
+ .halt_reg = 0x4401c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4401c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_bimc_mss_q6_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_ahb_clk = {
+ .halt_reg = 0x17004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(17),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
+ .halt_reg = 0x19008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x19008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup1_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup1_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
+ .halt_reg = 0x19004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x19004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup1_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup1_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
+ .halt_reg = 0x1b008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1b008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup2_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup2_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
+ .halt_reg = 0x1b004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1b004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup2_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup2_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
+ .halt_reg = 0x1d008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1d008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup3_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup3_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
+ .halt_reg = 0x1d004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1d004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup3_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup3_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
+ .halt_reg = 0x1f008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1f008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup4_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup4_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
+ .halt_reg = 0x1f004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1f004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_qup4_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_qup4_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart1_apps_clk = {
+ .halt_reg = 0x1a004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart1_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_uart1_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp1_uart2_apps_clk = {
+ .halt_reg = 0x1c004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1c004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp1_uart2_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp1_uart2_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_ahb_clk = {
+ .halt_reg = 0x25004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(15),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
+ .halt_reg = 0x26008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x26008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup1_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup1_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
+ .halt_reg = 0x26004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x26004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup1_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup1_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
+ .halt_reg = 0x28008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup2_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup2_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
+ .halt_reg = 0x28004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x28004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup2_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup2_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
+ .halt_reg = 0x2a008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2a008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup3_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup3_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
+ .halt_reg = 0x2a004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup3_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup3_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
+ .halt_reg = 0x2c008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2c008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup4_i2c_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup4_i2c_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
+ .halt_reg = 0x2c004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2c004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_qup4_spi_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_qup4_spi_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_uart1_apps_clk = {
+ .halt_reg = 0x27004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x27004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_uart1_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_uart1_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_blsp2_uart2_apps_clk = {
+ .halt_reg = 0x29004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x29004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_blsp2_uart2_apps_clk",
+ .parent_names = (const char *[]){
+ "blsp2_uart2_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_boot_rom_ahb_clk = {
+ .halt_reg = 0x38004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(10),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_boot_rom_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cfg_noc_usb2_axi_clk = {
+ .halt_reg = 0x5058,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5058,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_cfg_noc_usb2_axi_clk",
+ .parent_names = (const char *[]){
+ "usb20_master_clk_src",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
+ .halt_reg = 0x5018,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x5018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_cfg_noc_usb3_axi_clk",
+ .parent_names = (const char *[]){
+ "usb30_master_clk_src",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_dcc_ahb_clk = {
+ .halt_reg = 0x84004,
+ .clkr = {
+ .enable_reg = 0x84004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_dcc_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp1_clk = {
+ .halt_reg = 0x64000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x64000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp1_clk",
+ .parent_names = (const char *[]){
+ "gp1_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp2_clk = {
+ .halt_reg = 0x65000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x65000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp2_clk",
+ .parent_names = (const char *[]){
+ "gp2_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gp3_clk = {
+ .halt_reg = 0x66000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x66000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gp3_clk",
+ .parent_names = (const char *[]){
+ "gp3_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_bimc_gfx_clk = {
+ .halt_reg = 0x71010,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x71010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_bimc_gfx_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_cfg_ahb_clk = {
+ .halt_reg = 0x71004,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x71004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_gpll0_clk = {
+ .halt_reg = 0x5200c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_gpll0_clk",
+ .parent_names = (const char *[]){
+ "gpll0",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_gpu_gpll0_div_clk = {
+ .halt_reg = 0x5200c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(3),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_gpll0_div_clk",
+ .parent_names = (const char *[]){
+ "gpll0_early_div",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_hmss_dvm_bus_clk = {
+ .halt_reg = 0x4808c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4808c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_hmss_dvm_bus_clk",
+ .ops = &clk_branch2_ops,
+ .flags = CLK_IGNORE_UNUSED,
+ },
+ },
+};
+
+static struct clk_branch gcc_hmss_rbcpr_clk = {
+ .halt_reg = 0x48008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x48008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_hmss_rbcpr_clk",
+ .parent_names = (const char *[]){
+ "hmss_rbcpr_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mmss_gpll0_clk = {
+ .halt_reg = 0x5200c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mmss_gpll0_clk",
+ .parent_names = (const char *[]){
+ "gpll0",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mmss_gpll0_div_clk = {
+ .halt_reg = 0x5200c,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x5200c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mmss_gpll0_div_clk",
+ .parent_names = (const char *[]){
+ "gpll0_early_div",
+ },
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = {
+ .halt_reg = 0x9004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mmss_noc_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mmss_sys_noc_axi_clk = {
+ .halt_reg = 0x9000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x9000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mmss_sys_noc_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mss_cfg_ahb_clk = {
+ .halt_reg = 0x8a000,
+ .clkr = {
+ .enable_reg = 0x8a000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mss_cfg_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
+ .halt_reg = 0x8a004,
+ .clkr = {
+ .enable_reg = 0x8a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mss_mnoc_bimc_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
+ .halt_reg = 0x8a040,
+ .clkr = {
+ .enable_reg = 0x8a040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mss_q6_bimc_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_mss_snoc_axi_clk = {
+ .halt_reg = 0x8a03c,
+ .clkr = {
+ .enable_reg = 0x8a03c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_mss_snoc_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pdm2_clk = {
+ .halt_reg = 0x3300c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x3300c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pdm2_clk",
+ .parent_names = (const char *[]){
+ "pdm2_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pdm_ahb_clk = {
+ .halt_reg = 0x33004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x33004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pdm_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_prng_ahb_clk = {
+ .halt_reg = 0x34004,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(13),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_prng_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qspi_ahb_clk = {
+ .halt_reg = 0x4d004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4d004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qspi_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_qspi_ser_clk = {
+ .halt_reg = 0x4d008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x4d008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_qspi_ser_clk",
+ .parent_names = (const char *[]){
+ "qspi_ser_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_rx0_usb2_clkref_clk = {
+ .halt_reg = 0x88018,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x88018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_rx0_usb2_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_rx1_usb2_clkref_clk = {
+ .halt_reg = 0x88014,
+ .halt_check = BRANCH_HALT_VOTED,
+ .clkr = {
+ .enable_reg = 0x88014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_rx1_usb2_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_ahb_clk = {
+ .halt_reg = 0x16008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x16008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_apps_clk = {
+ .halt_reg = 0x16004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x16004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_apps_clk",
+ .parent_names = (const char *[]){
+ "sdcc1_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc1_ice_core_clk = {
+ .halt_reg = 0x1600c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x1600c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc1_ice_core_clk",
+ .parent_names = (const char *[]){
+ "sdcc1_ice_core_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc2_ahb_clk = {
+ .halt_reg = 0x14008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x14008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc2_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_sdcc2_apps_clk = {
+ .halt_reg = 0x14004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x14004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_sdcc2_apps_clk",
+ .parent_names = (const char *[]){
+ "sdcc2_apps_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_ahb_clk = {
+ .halt_reg = 0x7500c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x7500c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_ahb_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_axi_clk = {
+ .halt_reg = 0x75008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x75008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_axi_clk",
+ .parent_names = (const char *[]){
+ "ufs_axi_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_clkref_clk = {
+ .halt_reg = 0x88008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x88008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_ice_core_clk = {
+ .halt_reg = 0x7600c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x7600c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_ice_core_clk",
+ .parent_names = (const char *[]){
+ "ufs_ice_core_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_phy_aux_clk = {
+ .halt_reg = 0x76040,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x76040,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_phy_aux_clk",
+ .parent_names = (const char *[]){
+ "ufs_phy_aux_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
+ .halt_reg = 0x75014,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x75014,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_rx_symbol_0_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
+ .halt_reg = 0x7605c,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x7605c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_rx_symbol_1_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
+ .halt_reg = 0x75010,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x75010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_tx_symbol_0_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_ufs_unipro_core_clk = {
+ .halt_reg = 0x76008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x76008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_unipro_core_clk",
+ .parent_names = (const char *[]){
+ "ufs_unipro_core_clk_src",
+ },
+ .flags = CLK_SET_RATE_PARENT,
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb20_master_clk = {
+ .halt_reg = 0x2f004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2f004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb20_master_clk",
+ .parent_names = (const char *[]){
+ "usb20_master_clk_src"
+ },
+ .flags = CLK_SET_RATE_PARENT,
+ .num_parents = 1,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb20_mock_utmi_clk = {
+ .halt_reg = 0x2f00c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2f00c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb20_mock_utmi_clk",
+ .parent_names = (const char *[]){
+ "usb20_mock_utmi_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb20_sleep_clk = {
+ .halt_reg = 0x2f008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x2f008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb20_sleep_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_master_clk = {
+ .halt_reg = 0xf008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb30_master_clk",
+ .parent_names = (const char *[]){
+ "usb30_master_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_mock_utmi_clk = {
+ .halt_reg = 0xf010,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf010,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb30_mock_utmi_clk",
+ .parent_names = (const char *[]){
+ "usb30_mock_utmi_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb30_sleep_clk = {
+ .halt_reg = 0xf00c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xf00c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb30_sleep_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_clkref_clk = {
+ .halt_reg = 0x8800c,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x8800c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb3_clkref_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_phy_aux_clk = {
+ .halt_reg = 0x50000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x50000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb3_phy_aux_clk",
+ .parent_names = (const char *[]){
+ "usb3_phy_aux_clk_src",
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb3_phy_pipe_clk = {
+ .halt_reg = 0x50004,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x50004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb3_phy_pipe_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
+ .halt_reg = 0x6a004,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x6a004,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_usb_phy_cfg_ahb2phy_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct gdsc ufs_gdsc = {
+ .gdscr = 0x75004,
+ .gds_hw_ctrl = 0x0,
+ .pd = {
+ .name = "ufs_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc usb_30_gdsc = {
+ .gdscr = 0xf004,
+ .gds_hw_ctrl = 0x0,
+ .pd = {
+ .name = "usb_30_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct gdsc pcie_0_gdsc = {
+ .gdscr = 0x6b004,
+ .gds_hw_ctrl = 0x0,
+ .pd = {
+ .name = "pcie_0_gdsc",
+ },
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = VOTABLE,
+};
+
+static struct clk_hw *gcc_sdm660_hws[] = {
+ [GCC_XO] = &xo.hw,
+ [GCC_GPLL0_EARLY_DIV] = &gpll0_early_div.hw,
+ [GCC_GPLL1_EARLY_DIV] = &gpll1_early_div.hw,
+};
+
+static struct clk_regmap *gcc_660_clocks[] = {
+ [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
+ [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
+ [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
+ [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
+ [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
+ [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
+ [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
+ [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
+ [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
+ [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
+ [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
+ [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
+ [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
+ [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
+ [GCC_AGGRE2_UFS_AXI_CLK] = &gcc_aggre2_ufs_axi_clk.clkr,
+ [GCC_AGGRE2_USB3_AXI_CLK] = &gcc_aggre2_usb3_axi_clk.clkr,
+ [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
+ [GCC_BIMC_HMSS_AXI_CLK] = &gcc_bimc_hmss_axi_clk.clkr,
+ [GCC_BIMC_MSS_Q6_AXI_CLK] = &gcc_bimc_mss_q6_axi_clk.clkr,
+ [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
+ [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
+ [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
+ [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
+ [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
+ [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
+ [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
+ [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
+ [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
+ [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
+ [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
+ [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
+ [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
+ [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
+ [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
+ [GCC_CFG_NOC_USB2_AXI_CLK] = &gcc_cfg_noc_usb2_axi_clk.clkr,
+ [GCC_CFG_NOC_USB3_AXI_CLK] = &gcc_cfg_noc_usb3_axi_clk.clkr,
+ [GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
+ [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
+ [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
+ [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
+ [GCC_GPU_BIMC_GFX_CLK] = &gcc_gpu_bimc_gfx_clk.clkr,
+ [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
+ [GCC_GPU_GPLL0_CLK] = &gcc_gpu_gpll0_clk.clkr,
+ [GCC_GPU_GPLL0_DIV_CLK] = &gcc_gpu_gpll0_div_clk.clkr,
+ [GCC_HMSS_DVM_BUS_CLK] = &gcc_hmss_dvm_bus_clk.clkr,
+ [GCC_HMSS_RBCPR_CLK] = &gcc_hmss_rbcpr_clk.clkr,
+ [GCC_MMSS_GPLL0_CLK] = &gcc_mmss_gpll0_clk.clkr,
+ [GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
+ [GCC_MMSS_NOC_CFG_AHB_CLK] = &gcc_mmss_noc_cfg_ahb_clk.clkr,
+ [GCC_MMSS_SYS_NOC_AXI_CLK] = &gcc_mmss_sys_noc_axi_clk.clkr,
+ [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
+ [GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
+ [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
+ [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
+ [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
+ [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
+ [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
+ [GCC_QSPI_AHB_CLK] = &gcc_qspi_ahb_clk.clkr,
+ [GCC_QSPI_SER_CLK] = &gcc_qspi_ser_clk.clkr,
+ [GCC_RX0_USB2_CLKREF_CLK] = &gcc_rx0_usb2_clkref_clk.clkr,
+ [GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
+ [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
+ [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
+ [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
+ [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
+ [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
+ [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
+ [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
+ [GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
+ [GCC_UFS_ICE_CORE_CLK] = &gcc_ufs_ice_core_clk.clkr,
+ [GCC_UFS_PHY_AUX_CLK] = &gcc_ufs_phy_aux_clk.clkr,
+ [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
+ [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
+ [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
+ [GCC_UFS_UNIPRO_CORE_CLK] = &gcc_ufs_unipro_core_clk.clkr,
+ [GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
+ [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
+ [GCC_USB20_SLEEP_CLK] = &gcc_usb20_sleep_clk.clkr,
+ [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
+ [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
+ [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
+ [GCC_USB3_CLKREF_CLK] = &gcc_usb3_clkref_clk.clkr,
+ [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
+ [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
+ [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
+ [GP1_CLK_SRC] = &gp1_clk_src.clkr,
+ [GP2_CLK_SRC] = &gp2_clk_src.clkr,
+ [GP3_CLK_SRC] = &gp3_clk_src.clkr,
+ [GPLL0] = &gpll0.clkr,
+ [GPLL0_EARLY] = &gpll0_early.clkr,
+ [GPLL1] = &gpll1.clkr,
+ [GPLL1_EARLY] = &gpll1_early.clkr,
+ [GPLL1] = &gpll1.clkr,
+ [GPLL4_EARLY] = &gpll4_early.clkr,
+ [GPLL4] = &gpll4.clkr,
+ [HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
+ [HMSS_GPLL4_CLK_SRC] = &hmss_gpll4_clk_src.clkr,
+ [HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
+ [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
+ [QSPI_SER_CLK_SRC] = &qspi_ser_clk_src.clkr,
+ [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
+ [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
+ [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
+ [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
+ [UFS_ICE_CORE_CLK_SRC] = &ufs_ice_core_clk_src.clkr,
+ [UFS_PHY_AUX_CLK_SRC] = &ufs_phy_aux_clk_src.clkr,
+ [UFS_UNIPRO_CORE_CLK_SRC] = &ufs_unipro_core_clk_src.clkr,
+ [USB20_MASTER_CLK_SRC] = &usb20_master_clk_src.clkr,
+ [USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
+ [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
+ [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
+ [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
+};
+
+static struct gdsc *gcc_660_gdscs[] = {
+ [UFS_GDSC] = &ufs_gdsc,
+ [USB_30_GDSC] = &usb_30_gdsc,
+ [PCIE_0_GDSC] = &pcie_0_gdsc,
+};
+
+static const struct qcom_reset_map gcc_660_resets[] = {
+ [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
+ [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
+ [GCC_UFS_BCR] = { 0x75000 },
+ [GCC_USB3_DP_PHY_BCR] = { 0x50028 },
+ [GCC_USB3_PHY_BCR] = { 0x50020 },
+ [GCC_USB3PHY_PHY_BCR] = { 0x50024 },
+ [GCC_USB_20_BCR] = { 0x2f000 },
+ [GCC_USB_30_BCR] = { 0xf000 },
+ [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
+};
+
+static const struct regmap_config gcc_660_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x94000,
+ .fast_io = true,
+};
+
+static const struct qcom_cc_desc gcc_660_desc = {
+ .config = &gcc_660_regmap_config,
+ .clks = gcc_660_clocks,
+ .num_clks = ARRAY_SIZE(gcc_660_clocks),
+ .resets = gcc_660_resets,
+ .num_resets = ARRAY_SIZE(gcc_660_resets),
+ .gdscs = gcc_660_gdscs,
+ .num_gdscs = ARRAY_SIZE(gcc_660_gdscs),
+};
+
+static const struct of_device_id gcc_660_match_table[] = {
+ { .compatible = "qcom,gcc-sdm630" },
+ { .compatible = "qcom,gcc-sdm660" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, gcc_660_match_table);
+
+static int gcc_660_probe(struct platform_device *pdev)
+{
+ int i, ret = 0;
+ struct regmap *regmap;
+
+ regmap = qcom_cc_map(pdev, &gcc_660_desc);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ /*
+ * Set the HMSS_AHB_CLK_SLEEP_ENA bit to allow the hmss_ahb_clk to be
+ * turned off by hardware during certain apps low power modes.
+ */
+ ret = regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
+ if (ret)
+ return ret;
+
+ /* Register the hws */
+ for (i = 0; i < ARRAY_SIZE(gcc_sdm660_hws); i++) {
+ ret = devm_clk_hw_register(&pdev->dev, gcc_sdm660_hws[i]);
+ if (ret)
+ return ret;
+ }
+
+ return qcom_cc_really_probe(pdev, &gcc_660_desc, regmap);
+}
+
+static struct platform_driver gcc_660_driver = {
+ .probe = gcc_660_probe,
+ .driver = {
+ .name = "gcc-sdm660",
+ .of_match_table = gcc_660_match_table,
+ },
+};
+
+static int __init gcc_660_init(void)
+{
+ return platform_driver_register(&gcc_660_driver);
+}
+core_initcall_sync(gcc_660_init);
+
+static void __exit gcc_660_exit(void)
+{
+ platform_driver_unregister(&gcc_660_driver);
+}
+module_exit(gcc_660_exit);
+
+MODULE_DESCRIPTION("QCOM GCC sdm660 Driver");
diff --git a/include/dt-bindings/clock/qcom,gcc-sdm660.h b/include/dt-bindings/clock/qcom,gcc-sdm660.h
new file mode 100644
index 000000000000..76aabcc5e7e3
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sdm660.h
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018, Craig Tatlor.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H
+#define _DT_BINDINGS_CLK_MSM_GCC_660_H
+
+#define GCC_XO 0
+#define GCC_GPLL0_EARLY_DIV 1
+#define GCC_GPLL1_EARLY_DIV 2
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 3
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 4
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 5
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 6
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 7
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 8
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC 9
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC 10
+#define BLSP1_UART1_APPS_CLK_SRC 11
+#define BLSP1_UART2_APPS_CLK_SRC 12
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC 13
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC 14
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC 15
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC 16
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC 17
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC 18
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC 19
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC 20
+#define BLSP2_UART1_APPS_CLK_SRC 21
+#define BLSP2_UART2_APPS_CLK_SRC 22
+#define GCC_AGGRE2_UFS_AXI_CLK 23
+#define GCC_AGGRE2_USB3_AXI_CLK 24
+#define GCC_BIMC_GFX_CLK 25
+#define GCC_BIMC_HMSS_AXI_CLK 26
+#define GCC_BIMC_MSS_Q6_AXI_CLK 27
+#define GCC_BLSP1_AHB_CLK 28
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 29
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 30
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 31
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 32
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 33
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 34
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 35
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 36
+#define GCC_BLSP1_UART1_APPS_CLK 37
+#define GCC_BLSP1_UART2_APPS_CLK 38
+#define GCC_BLSP2_AHB_CLK 39
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK 40
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK 41
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK 42
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK 43
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK 44
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK 46
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK 45
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK 46
+#define GCC_BLSP2_UART1_APPS_CLK 47
+#define GCC_BLSP2_UART2_APPS_CLK 48
+#define GCC_BOOT_ROM_AHB_CLK 49
+#define GCC_CFG_NOC_USB2_AXI_CLK 50
+#define GCC_CFG_NOC_USB3_AXI_CLK 51
+#define GCC_DCC_AHB_CLK 52
+#define GCC_GP1_CLK 53
+#define GCC_GP2_CLK 54
+#define GCC_GP3_CLK 55
+#define GCC_GPU_BIMC_GFX_CLK 56
+#define GCC_GPU_CFG_AHB_CLK 57
+#define GCC_GPU_GPLL0_CLK 58
+#define GCC_GPU_GPLL0_DIV_CLK 59
+#define GCC_HMSS_DVM_BUS_CLK 60
+#define GCC_HMSS_RBCPR_CLK 61
+#define GCC_MMSS_GPLL0_CLK 62
+#define GCC_MMSS_GPLL0_DIV_CLK 63
+#define GCC_MMSS_NOC_CFG_AHB_CLK 64
+#define GCC_MMSS_SYS_NOC_AXI_CLK 65
+#define GCC_MSS_CFG_AHB_CLK 66
+#define GCC_MSS_GPLL0_DIV_CLK 67
+#define GCC_MSS_MNOC_BIMC_AXI_CLK 68
+#define GCC_MSS_Q6_BIMC_AXI_CLK 69
+#define GCC_MSS_SNOC_AXI_CLK 70
+#define GCC_PDM2_CLK 71
+#define GCC_PDM_AHB_CLK 72
+#define GCC_PRNG_AHB_CLK 73
+#define GCC_QSPI_AHB_CLK 74
+#define GCC_QSPI_SER_CLK 75
+#define GCC_SDCC1_AHB_CLK 76
+#define GCC_SDCC1_APPS_CLK 77
+#define GCC_SDCC1_ICE_CORE_CLK 78
+#define GCC_SDCC2_AHB_CLK 79
+#define GCC_SDCC2_APPS_CLK 80
+#define GCC_UFS_AHB_CLK 81
+#define GCC_UFS_AXI_CLK 82
+#define GCC_UFS_CLKREF_CLK 83
+#define GCC_UFS_ICE_CORE_CLK 84
+#define GCC_UFS_PHY_AUX_CLK 85
+#define GCC_UFS_RX_SYMBOL_0_CLK 86
+#define GCC_UFS_RX_SYMBOL_1_CLK 87
+#define GCC_UFS_TX_SYMBOL_0_CLK 88
+#define GCC_UFS_UNIPRO_CORE_CLK 89
+#define GCC_USB20_MASTER_CLK 90
+#define GCC_USB20_MOCK_UTMI_CLK 91
+#define GCC_USB20_SLEEP_CLK 92
+#define GCC_USB30_MASTER_CLK 93
+#define GCC_USB30_MOCK_UTMI_CLK 94
+#define GCC_USB30_SLEEP_CLK 95
+#define GCC_USB3_CLKREF_CLK 96
+#define GCC_USB3_PHY_AUX_CLK 97
+#define GCC_USB3_PHY_PIPE_CLK 98
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK 99
+#define GP1_CLK_SRC 100
+#define GP2_CLK_SRC 101
+#define GP3_CLK_SRC 102
+#define GPLL0 103
+#define GPLL0_EARLY 104
+#define GPLL1 105
+#define GPLL1_EARLY 106
+#define GPLL4 107
+#define GPLL4_EARLY 108
+#define HMSS_GPLL0_CLK_SRC 109
+#define HMSS_GPLL4_CLK_SRC 110
+#define HMSS_RBCPR_CLK_SRC 111
+#define PDM2_CLK_SRC 112
+#define QSPI_SER_CLK_SRC 113
+#define SDCC1_APPS_CLK_SRC 114
+#define SDCC1_ICE_CORE_CLK_SRC 115
+#define SDCC2_APPS_CLK_SRC 116
+#define UFS_AXI_CLK_SRC 117
+#define UFS_ICE_CORE_CLK_SRC 118
+#define UFS_PHY_AUX_CLK_SRC 119
+#define UFS_UNIPRO_CORE_CLK_SRC 120
+#define USB20_MASTER_CLK_SRC 121
+#define USB20_MOCK_UTMI_CLK_SRC 122
+#define USB30_MASTER_CLK_SRC 123
+#define USB30_MOCK_UTMI_CLK_SRC 124
+#define USB3_PHY_AUX_CLK_SRC 125
+#define GPLL0_OUT_MSSCC 126
+#define GCC_UFS_AXI_HW_CTL_CLK 127
+#define GCC_UFS_ICE_CORE_HW_CTL_CLK 128
+#define GCC_UFS_PHY_AUX_HW_CTL_CLK 129
+#define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 130
+#define GCC_RX0_USB2_CLKREF_CLK 131
+#define GCC_RX1_USB2_CLKREF_CLK 132
+
+#define PCIE_0_GDSC 0
+#define UFS_GDSC 1
+#define USB_30_GDSC 2
+
+#define GCC_QUSB2PHY_PRIM_BCR 0
+#define GCC_QUSB2PHY_SEC_BCR 1
+#define GCC_UFS_BCR 2
+#define GCC_USB3_DP_PHY_BCR 3
+#define GCC_USB3_PHY_BCR 4
+#define GCC_USB3PHY_PHY_BCR 5
+#define GCC_USB_20_BCR 6
+#define GCC_USB_30_BCR 7
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR 8
+
+#endif
--
2.18.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v3] clk: qcom: Add Global Clock controller (GCC) driver for SDM660
2018-09-25 17:35 ` [PATCH v3] " Craig Tatlor
2018-09-25 17:35 ` Craig Tatlor
@ 2018-09-27 19:51 ` Rob Herring
2018-09-27 19:51 ` Rob Herring
2018-10-08 6:51 ` Craig
2018-10-16 22:05 ` Stephen Boyd
3 siblings, 1 reply; 18+ messages in thread
From: Rob Herring @ 2018-09-27 19:51 UTC (permalink / raw)
To: Craig Tatlor
Cc: linux-arm-msm, Taniya Das, Michael Turquette, Stephen Boyd,
Mark Rutland, Andy Gross, David Brown, linux-clk, devicetree,
linux-kernel, linux-soc
On Tue, Sep 25, 2018 at 06:35:58PM +0100, Craig Tatlor wrote:
> From: Taniya Das <tdas@codeaurora.org>
>
> Add support for the global clock controller found on SDM660
> based devices. This should allow most non-multimedia device
> drivers to probe and control their clocks.
> Based on CAF implementation.
>
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> [craig: rename parents to fit upstream, and other cleanups]
> Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
> ---
> Changes from V1:
> Change authorship
> Add sdm630 compatible
> .../devicetree/bindings/clock/qcom,gcc.txt | 1 +
Acked-by: Rob Herring <robh@kernel.org>
> drivers/clk/qcom/Kconfig | 9 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/gcc-sdm660.c | 2480 +++++++++++++++++
> include/dt-bindings/clock/qcom,gcc-sdm660.h | 159 ++
> 5 files changed, 2650 insertions(+)
> create mode 100644 drivers/clk/qcom/gcc-sdm660.c
> create mode 100644 include/dt-bindings/clock/qcom,gcc-sdm660.h
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3] clk: qcom: Add Global Clock controller (GCC) driver for SDM660
2018-09-27 19:51 ` Rob Herring
@ 2018-09-27 19:51 ` Rob Herring
0 siblings, 0 replies; 18+ messages in thread
From: Rob Herring @ 2018-09-27 19:51 UTC (permalink / raw)
To: Craig Tatlor
Cc: linux-arm-msm, Taniya Das, Michael Turquette, Stephen Boyd,
Mark Rutland, Andy Gross, David Brown, linux-clk, devicetree,
linux-kernel, linux-soc
On Tue, Sep 25, 2018 at 06:35:58PM +0100, Craig Tatlor wrote:
> From: Taniya Das <tdas@codeaurora.org>
>
> Add support for the global clock controller found on SDM660
> based devices. This should allow most non-multimedia device
> drivers to probe and control their clocks.
> Based on CAF implementation.
>
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> [craig: rename parents to fit upstream, and other cleanups]
> Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
> ---
> Changes from V1:
> Change authorship
> Add sdm630 compatible
> .../devicetree/bindings/clock/qcom,gcc.txt | 1 +
Acked-by: Rob Herring <robh@kernel.org>
> drivers/clk/qcom/Kconfig | 9 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/gcc-sdm660.c | 2480 +++++++++++++++++
> include/dt-bindings/clock/qcom,gcc-sdm660.h | 159 ++
> 5 files changed, 2650 insertions(+)
> create mode 100644 drivers/clk/qcom/gcc-sdm660.c
> create mode 100644 include/dt-bindings/clock/qcom,gcc-sdm660.h
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3] clk: qcom: Add Global Clock controller (GCC) driver for SDM660
2018-09-25 17:35 ` [PATCH v3] " Craig Tatlor
2018-09-25 17:35 ` Craig Tatlor
2018-09-27 19:51 ` Rob Herring
@ 2018-10-08 6:51 ` Craig
2018-10-16 22:05 ` Stephen Boyd
3 siblings, 0 replies; 18+ messages in thread
From: Craig @ 2018-10-08 6:51 UTC (permalink / raw)
Cc: linux-arm-msm, Taniya Das, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Andy Gross, David Brown, linux-clk,
devicetree, linux-kernel, linux-soc
(Resend due to broken email client) any reviews for this?
On 25 September 2018 18:35:58 BST, Craig Tatlor <ctatlor97@gmail.com> wrote:
>From: Taniya Das <tdas@codeaurora.org>
>
>Add support for the global clock controller found on SDM660
>based devices. This should allow most non-multimedia device
>drivers to probe and control their clocks.
>Based on CAF implementation.
>
>Signed-off-by: Taniya Das <tdas@codeaurora.org>
>[craig: rename parents to fit upstream, and other cleanups]
>Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
>---
>Changes from V1:
> Change authorship
> Add sdm630 compatible
> .../devicetree/bindings/clock/qcom,gcc.txt | 1 +
> drivers/clk/qcom/Kconfig | 9 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/gcc-sdm660.c | 2480 +++++++++++++++++
> include/dt-bindings/clock/qcom,gcc-sdm660.h | 159 ++
> 5 files changed, 2650 insertions(+)
> create mode 100644 drivers/clk/qcom/gcc-sdm660.c
> create mode 100644 include/dt-bindings/clock/qcom,gcc-sdm660.h
>
>diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
>b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
>index 664ea1fd6c76..e498ad2e8db8 100644
>--- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt
>+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt
>@@ -38,6 +38,8 @@ Required properties :
> "qcom,gcc-msm8996"
> "qcom,gcc-msm8998"
> "qcom,gcc-mdm9615"
>+ "qcom,gcc-sdm630"
>+ "qcom,gcc-sdm660"
> "qcom,gcc-sdm845"
>
> - reg : shall contain base register location and length
>diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>index 5b181b182f40..4d478b261dfe 100644
>--- a/drivers/clk/qcom/Kconfig
>+++ b/drivers/clk/qcom/Kconfig
>@@ -243,6 +243,15 @@ config SDM_CAMCC_845
> Support for the camera clock controller on SDM845 devices.
> Say Y if you want to support camera devices and camera
>functionality.
>
>+config SDM_GCC_660
>+ tristate "SDM660 Global Clock Controller"
>+ select QCOM_GDSC
>+ depends on COMMON_CLK_QCOM
>+ help
>+ Support for the global clock controller on SDM660 devices.
>+ Say Y if you want to use peripheral devices such as UART, SPI,
>+ i2C, USB, UFS, SDDC, PCIe, etc.
>+
> config SDM_GCC_845
> tristate "SDM845 Global Clock Controller"
> select QCOM_GDSC
>diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>index 935f142bc155..ab892f6d847c 100644
>--- a/drivers/clk/qcom/Makefile
>+++ b/drivers/clk/qcom/Makefile
>@@ -41,6 +41,7 @@ obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o
> obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
> obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o
> obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
>+obj-$(CONFIG_SDM_GCC_660) += gcc-sdm660.o
> obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
> obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
> obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
>diff --git a/drivers/clk/qcom/gcc-sdm660.c
>b/drivers/clk/qcom/gcc-sdm660.c
>new file mode 100644
>index 000000000000..641bba611b5f
>--- /dev/null
>+++ b/drivers/clk/qcom/gcc-sdm660.c
>@@ -0,0 +1,2480 @@
>+// SPDX-License-Identifier: GPL-2.0
>+/*
>+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
>+ * Copyright (c) 2018, Craig Tatlor.
>+ */
>+
>+#include <linux/kernel.h>
>+#include <linux/bitops.h>
>+#include <linux/err.h>
>+#include <linux/platform_device.h>
>+#include <linux/module.h>
>+#include <linux/of.h>
>+#include <linux/of_device.h>
>+#include <linux/clk-provider.h>
>+#include <linux/regmap.h>
>+#include <linux/reset-controller.h>
>+
>+#include <dt-bindings/clock/qcom,gcc-sdm660.h>
>+
>+#include "common.h"
>+#include "clk-regmap.h"
>+#include "clk-alpha-pll.h"
>+#include "clk-rcg.h"
>+#include "clk-branch.h"
>+#include "reset.h"
>+#include "gdsc.h"
>+
>+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
>+
>+enum {
>+ P_XO,
>+ P_SLEEP_CLK,
>+ P_GPLL0,
>+ P_GPLL1,
>+ P_GPLL4,
>+ P_GPLL0_EARLY_DIV,
>+ P_GPLL1_EARLY_DIV,
>+};
>+
>+static const struct parent_map
>gcc_parent_map_xo_gpll0_gpll0_early_div[] = {
>+ { P_XO, 0 },
>+ { P_GPLL0, 1 },
>+ { P_GPLL0_EARLY_DIV, 6 },
>+};
>+
>+static const char * const gcc_parent_names_xo_gpll0_gpll0_early_div[]
>= {
>+ "xo",
>+ "gpll0",
>+ "gpll0_early_div",
>+};
>+
>+static const struct parent_map gcc_parent_map_xo_gpll0[] = {
>+ { P_XO, 0 },
>+ { P_GPLL0, 1 },
>+};
>+
>+static const char * const gcc_parent_names_xo_gpll0[] = {
>+ "xo",
>+ "gpll0",
>+};
>+
>+static const struct parent_map
>gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div[] = {
>+ { P_XO, 0 },
>+ { P_GPLL0, 1 },
>+ { P_SLEEP_CLK, 5 },
>+ { P_GPLL0_EARLY_DIV, 6 },
>+};
>+
>+static const char * const
>gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div[] = {
>+ "xo",
>+ "gpll0",
>+ "sleep_clk",
>+ "gpll0_early_div",
>+};
>+
>+static const struct parent_map gcc_parent_map_xo_sleep_clk[] = {
>+ { P_XO, 0 },
>+ { P_SLEEP_CLK, 5 },
>+};
>+
>+static const char * const gcc_parent_names_xo_sleep_clk[] = {
>+ "xo",
>+ "sleep_clk",
>+};
>+
>+static const struct parent_map gcc_parent_map_xo_gpll4[] = {
>+ { P_XO, 0 },
>+ { P_GPLL4, 5 },
>+};
>+
>+static const char * const gcc_parent_names_xo_gpll4[] = {
>+ "xo",
>+ "gpll4",
>+};
>+
>+static const struct parent_map
>gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[] =
>{
>+ { P_XO, 0 },
>+ { P_GPLL0, 1 },
>+ { P_GPLL0_EARLY_DIV, 3 },
>+ { P_GPLL1, 4 },
>+ { P_GPLL4, 5 },
>+ { P_GPLL1_EARLY_DIV, 6 },
>+};
>+
>+static const char * const
>gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div[]
>= {
>+ "xo",
>+ "gpll0",
>+ "gpll0_early_div",
>+ "gpll1",
>+ "gpll4",
>+ "gpll1_early_div",
>+};
>+
>+static const struct parent_map
>gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div[] = {
>+ { P_XO, 0 },
>+ { P_GPLL0, 1 },
>+ { P_GPLL4, 5 },
>+ { P_GPLL0_EARLY_DIV, 6 },
>+};
>+
>+static const char * const
>gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div[] = {
>+ "xo",
>+ "gpll0",
>+ "gpll4",
>+ "gpll0_early_div",
>+};
>+
>+static const struct parent_map
>gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4[] = {
>+ { P_XO, 0 },
>+ { P_GPLL0, 1 },
>+ { P_GPLL0_EARLY_DIV, 2 },
>+ { P_GPLL4, 5 },
>+};
>+
>+static const char * const
>gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4[] = {
>+ "xo",
>+ "gpll0",
>+ "gpll0_early_div",
>+ "gpll4",
>+};
>+
>+static struct clk_fixed_factor xo = {
>+ .mult = 1,
>+ .div = 1,
>+ .hw.init = &(struct clk_init_data){
>+ .name = "xo",
>+ .parent_names = (const char *[]){ "xo_board" },
>+ .num_parents = 1,
>+ .ops = &clk_fixed_factor_ops,
>+ },
>+};
>+
>+static struct clk_alpha_pll gpll0_early = {
>+ .offset = 0x0,
>+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>+ .clkr = {
>+ .enable_reg = 0x52000,
>+ .enable_mask = BIT(0),
>+ .hw.init = &(struct clk_init_data){
>+ .name = "gpll0_early",
>+ .parent_names = (const char *[]){ "xo" },
>+ .num_parents = 1,
>+ .ops = &clk_alpha_pll_ops,
>+ },
>+ },
>+};
>+
>+static struct clk_fixed_factor gpll0_early_div = {
>+ .mult = 1,
>+ .div = 2,
>+ .hw.init = &(struct clk_init_data){
>+ .name = "gpll0_early_div",
>+ .parent_names = (const char *[]){ "gpll0_early" },
>+ .num_parents = 1,
>+ .ops = &clk_fixed_factor_ops,
>+ },
>+};
>+
>+static struct clk_alpha_pll_postdiv gpll0 = {
>+ .offset = 0x00000,
>+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "gpll0",
>+ .parent_names = (const char *[]){ "gpll0_early" },
>+ .num_parents = 1,
>+ .ops = &clk_alpha_pll_postdiv_ops,
>+ },
>+};
>+
>+static struct clk_alpha_pll gpll1_early = {
>+ .offset = 0x1000,
>+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>+ .clkr = {
>+ .enable_reg = 0x52000,
>+ .enable_mask = BIT(1),
>+ .hw.init = &(struct clk_init_data){
>+ .name = "gpll1_early",
>+ .parent_names = (const char *[]){ "xo" },
>+ .num_parents = 1,
>+ .ops = &clk_alpha_pll_ops,
>+ },
>+ },
>+};
>+
>+static struct clk_fixed_factor gpll1_early_div = {
>+ .mult = 1,
>+ .div = 2,
>+ .hw.init = &(struct clk_init_data){
>+ .name = "gpll1_early_div",
>+ .parent_names = (const char *[]){ "gpll1_early" },
>+ .num_parents = 1,
>+ .ops = &clk_fixed_factor_ops,
>+ },
>+};
>+
>+static struct clk_alpha_pll_postdiv gpll1 = {
>+ .offset = 0x1000,
>+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "gpll1",
>+ .parent_names = (const char *[]){ "gpll1_early" },
>+ .num_parents = 1,
>+ .ops = &clk_alpha_pll_postdiv_ops,
>+ },
>+};
>+
>+static struct clk_alpha_pll gpll4_early = {
>+ .offset = 0x77000,
>+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>+ .clkr = {
>+ .enable_reg = 0x52000,
>+ .enable_mask = BIT(4),
>+ .hw.init = &(struct clk_init_data){
>+ .name = "gpll4_early",
>+ .parent_names = (const char *[]){ "xo" },
>+ .num_parents = 1,
>+ .ops = &clk_alpha_pll_ops,
>+ },
>+ },
>+};
>+
>+static struct clk_alpha_pll_postdiv gpll4 = {
>+ .offset = 0x77000,
>+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>+ .clkr.hw.init = &(struct clk_init_data)
>+ {
>+ .name = "gpll4",
>+ .parent_names = (const char *[]) { "gpll4_early" },
>+ .num_parents = 1,
>+ .ops = &clk_alpha_pll_postdiv_ops,
>+ },
>+};
>+
>+static const struct freq_tbl ftbl_blsp1_qup1_i2c_apps_clk_src[] = {
>+ F(19200000, P_XO, 1, 0, 0),
>+ F(50000000, P_GPLL0, 12, 0, 0),
>+ { }
>+};
>+
>+static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
>+ .cmd_rcgr = 0x19020,
>+ .mnd_width = 0,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "blsp1_qup1_i2c_apps_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
>+ F(960000, P_XO, 10, 1, 2),
>+ F(4800000, P_XO, 4, 0, 0),
>+ F(9600000, P_XO, 2, 0, 0),
>+ F(15000000, P_GPLL0, 10, 1, 4),
>+ F(19200000, P_XO, 1, 0, 0),
>+ F(25000000, P_GPLL0, 12, 1, 2),
>+ F(50000000, P_GPLL0, 12, 0, 0),
>+ { }
>+};
>+
>+static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
>+ .cmd_rcgr = 0x1900c,
>+ .mnd_width = 8,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "blsp1_qup1_spi_apps_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
>+ .cmd_rcgr = 0x1b020,
>+ .mnd_width = 0,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "blsp1_qup2_i2c_apps_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
>+ .cmd_rcgr = 0x1b00c,
>+ .mnd_width = 8,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "blsp1_qup2_spi_apps_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
>+ .cmd_rcgr = 0x1d020,
>+ .mnd_width = 0,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "blsp1_qup3_i2c_apps_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
>+ .cmd_rcgr = 0x1d00c,
>+ .mnd_width = 8,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "blsp1_qup3_spi_apps_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
>+ .cmd_rcgr = 0x1f020,
>+ .mnd_width = 0,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "blsp1_qup4_i2c_apps_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
>+ .cmd_rcgr = 0x1f00c,
>+ .mnd_width = 8,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "blsp1_qup4_spi_apps_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static const struct freq_tbl ftbl_blsp1_uart1_apps_clk_src[] = {
>+ F(3686400, P_GPLL0, 1, 96, 15625),
>+ F(7372800, P_GPLL0, 1, 192, 15625),
>+ F(14745600, P_GPLL0, 1, 384, 15625),
>+ F(16000000, P_GPLL0, 5, 2, 15),
>+ F(19200000, P_XO, 1, 0, 0),
>+ F(24000000, P_GPLL0, 5, 1, 5),
>+ F(32000000, P_GPLL0, 1, 4, 75),
>+ F(40000000, P_GPLL0, 15, 0, 0),
>+ F(46400000, P_GPLL0, 1, 29, 375),
>+ F(48000000, P_GPLL0, 12.5, 0, 0),
>+ F(51200000, P_GPLL0, 1, 32, 375),
>+ F(56000000, P_GPLL0, 1, 7, 75),
>+ F(58982400, P_GPLL0, 1, 1536, 15625),
>+ F(60000000, P_GPLL0, 10, 0, 0),
>+ F(63157895, P_GPLL0, 9.5, 0, 0),
>+ { }
>+};
>+
>+static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
>+ .cmd_rcgr = 0x1a00c,
>+ .mnd_width = 16,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "blsp1_uart1_apps_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
>+ .cmd_rcgr = 0x1c00c,
>+ .mnd_width = 16,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "blsp1_uart2_apps_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
>+ .cmd_rcgr = 0x26020,
>+ .mnd_width = 0,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "blsp2_qup1_i2c_apps_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
>+ .cmd_rcgr = 0x2600c,
>+ .mnd_width = 8,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "blsp2_qup1_spi_apps_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
>+ .cmd_rcgr = 0x28020,
>+ .mnd_width = 0,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "blsp2_qup2_i2c_apps_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
>+ .cmd_rcgr = 0x2800c,
>+ .mnd_width = 8,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "blsp2_qup2_spi_apps_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
>+ .cmd_rcgr = 0x2a020,
>+ .mnd_width = 0,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "blsp2_qup3_i2c_apps_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
>+ .cmd_rcgr = 0x2a00c,
>+ .mnd_width = 8,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "blsp2_qup3_spi_apps_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
>+ .cmd_rcgr = 0x2c020,
>+ .mnd_width = 0,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_blsp1_qup1_i2c_apps_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "blsp2_qup4_i2c_apps_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
>+ .cmd_rcgr = 0x2c00c,
>+ .mnd_width = 8,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "blsp2_qup4_spi_apps_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
>+ .cmd_rcgr = 0x2700c,
>+ .mnd_width = 16,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "blsp2_uart1_apps_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
>+ .cmd_rcgr = 0x2900c,
>+ .mnd_width = 16,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_blsp1_uart1_apps_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "blsp2_uart2_apps_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static const struct freq_tbl ftbl_gp1_clk_src[] = {
>+ F(19200000, P_XO, 1, 0, 0),
>+ F(100000000, P_GPLL0, 6, 0, 0),
>+ F(200000000, P_GPLL0, 3, 0, 0),
>+ { }
>+};
>+
>+static struct clk_rcg2 gp1_clk_src = {
>+ .cmd_rcgr = 0x64004,
>+ .mnd_width = 8,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
>+ .freq_tbl = ftbl_gp1_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "gp1_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
>+ .num_parents = 4,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static struct clk_rcg2 gp2_clk_src = {
>+ .cmd_rcgr = 0x65004,
>+ .mnd_width = 8,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
>+ .freq_tbl = ftbl_gp1_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "gp2_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
>+ .num_parents = 4,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static struct clk_rcg2 gp3_clk_src = {
>+ .cmd_rcgr = 0x66004,
>+ .mnd_width = 8,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_sleep_clk_gpll0_early_div,
>+ .freq_tbl = ftbl_gp1_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "gp3_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_sleep_clk_gpll0_early_div,
>+ .num_parents = 4,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static const struct freq_tbl ftbl_hmss_gpll0_clk_src[] = {
>+ F(300000000, P_GPLL0, 2, 0, 0),
>+ F(600000000, P_GPLL0, 1, 0, 0),
>+ { }
>+};
>+
>+static struct clk_rcg2 hmss_gpll0_clk_src = {
>+ .cmd_rcgr = 0x4805c,
>+ .mnd_width = 0,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_hmss_gpll0_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "hmss_gpll0_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static const struct freq_tbl ftbl_hmss_gpll4_clk_src[] = {
>+ F(384000000, P_GPLL4, 4, 0, 0),
>+ F(768000000, P_GPLL4, 2, 0, 0),
>+ F(1536000000, P_GPLL4, 1, 0, 0),
>+ { }
>+};
>+
>+static struct clk_rcg2 hmss_gpll4_clk_src = {
>+ .cmd_rcgr = 0x48074,
>+ .mnd_width = 0,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll4,
>+ .freq_tbl = ftbl_hmss_gpll4_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "hmss_gpll4_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll4,
>+ .num_parents = 2,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static const struct freq_tbl ftbl_hmss_rbcpr_clk_src[] = {
>+ F(19200000, P_XO, 1, 0, 0),
>+ { }
>+};
>+
>+static struct clk_rcg2 hmss_rbcpr_clk_src = {
>+ .cmd_rcgr = 0x48044,
>+ .mnd_width = 0,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_hmss_rbcpr_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "hmss_rbcpr_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0,
>+ .num_parents = 2,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static const struct freq_tbl ftbl_pdm2_clk_src[] = {
>+ F(60000000, P_GPLL0, 10, 0, 0),
>+ { }
>+};
>+
>+static struct clk_rcg2 pdm2_clk_src = {
>+ .cmd_rcgr = 0x33010,
>+ .mnd_width = 0,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_pdm2_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "pdm2_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
>+ F(19200000, P_XO, 1, 0, 0),
>+ F(80200000, P_GPLL1_EARLY_DIV, 5, 0, 0),
>+ F(160400000, P_GPLL1, 5, 0, 0),
>+ F(267333333, P_GPLL1, 3, 0, 0),
>+ { }
>+};
>+
>+static struct clk_rcg2 qspi_ser_clk_src = {
>+ .cmd_rcgr = 0x4d00c,
>+ .mnd_width = 0,
>+ .hid_width = 5,
>+ .parent_map =
>gcc_parent_map_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
>+ .freq_tbl = ftbl_qspi_ser_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "qspi_ser_clk_src",
>+ .parent_names =
>gcc_parent_names_xo_gpll0_gpll0_early_div_gpll1_gpll4_gpll1_early_div,
>+ .num_parents = 6,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
>+ F(144000, P_XO, 16, 3, 25),
>+ F(400000, P_XO, 12, 1, 4),
>+ F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
>+ F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
>+ F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
>+ F(100000000, P_GPLL0, 6, 0, 0),
>+ F(192000000, P_GPLL4, 8, 0, 0),
>+ F(384000000, P_GPLL4, 4, 0, 0),
>+ { }
>+};
>+
>+static struct clk_rcg2 sdcc1_apps_clk_src = {
>+ .cmd_rcgr = 0x1602c,
>+ .mnd_width = 8,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll4_gpll0_early_div,
>+ .freq_tbl = ftbl_sdcc1_apps_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "sdcc1_apps_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll4_gpll0_early_div,
>+ .num_parents = 4,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
>+ F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
>+ F(150000000, P_GPLL0, 4, 0, 0),
>+ F(200000000, P_GPLL0, 3, 0, 0),
>+ F(300000000, P_GPLL0, 2, 0, 0),
>+ { }
>+};
>+
>+static struct clk_rcg2 sdcc1_ice_core_clk_src = {
>+ .cmd_rcgr = 0x16010,
>+ .mnd_width = 0,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "sdcc1_ice_core_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
>+ F(144000, P_XO, 16, 3, 25),
>+ F(400000, P_XO, 12, 1, 4),
>+ F(20000000, P_GPLL0_EARLY_DIV, 5, 1, 3),
>+ F(25000000, P_GPLL0_EARLY_DIV, 6, 1, 2),
>+ F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
>+ F(100000000, P_GPLL0, 6, 0, 0),
>+ F(192000000, P_GPLL4, 8, 0, 0),
>+ F(200000000, P_GPLL0, 3, 0, 0),
>+ { }
>+};
>+
>+static struct clk_rcg2 sdcc2_apps_clk_src = {
>+ .cmd_rcgr = 0x14010,
>+ .mnd_width = 8,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div_gpll4,
>+ .freq_tbl = ftbl_sdcc2_apps_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "sdcc2_apps_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div_gpll4,
>+ .num_parents = 4,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static const struct freq_tbl ftbl_ufs_axi_clk_src[] = {
>+ F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),
>+ F(100000000, P_GPLL0, 6, 0, 0),
>+ F(150000000, P_GPLL0, 4, 0, 0),
>+ F(200000000, P_GPLL0, 3, 0, 0),
>+ F(240000000, P_GPLL0, 2.5, 0, 0),
>+ { }
>+};
>+
>+static struct clk_rcg2 ufs_axi_clk_src = {
>+ .cmd_rcgr = 0x75018,
>+ .mnd_width = 8,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_ufs_axi_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "ufs_axi_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
>+ F(75000000, P_GPLL0_EARLY_DIV, 4, 0, 0),
>+ F(150000000, P_GPLL0, 4, 0, 0),
>+ F(300000000, P_GPLL0, 2, 0, 0),
>+ { }
>+};
>+
>+static struct clk_rcg2 ufs_ice_core_clk_src = {
>+ .cmd_rcgr = 0x76010,
>+ .mnd_width = 0,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_ufs_ice_core_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "ufs_ice_core_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static struct clk_rcg2 ufs_phy_aux_clk_src = {
>+ .cmd_rcgr = 0x76044,
>+ .mnd_width = 0,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_sleep_clk,
>+ .freq_tbl = ftbl_hmss_rbcpr_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "ufs_phy_aux_clk_src",
>+ .parent_names = gcc_parent_names_xo_sleep_clk,
>+ .num_parents = 2,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static const struct freq_tbl ftbl_ufs_unipro_core_clk_src[] = {
>+ F(37500000, P_GPLL0_EARLY_DIV, 8, 0, 0),
>+ F(75000000, P_GPLL0, 8, 0, 0),
>+ F(150000000, P_GPLL0, 4, 0, 0),
>+ { }
>+};
>+
>+static struct clk_rcg2 ufs_unipro_core_clk_src = {
>+ .cmd_rcgr = 0x76028,
>+ .mnd_width = 0,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_ufs_unipro_core_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "ufs_unipro_core_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static const struct freq_tbl ftbl_usb20_master_clk_src[] = {
>+ F(19200000, P_XO, 1, 0, 0),
>+ F(60000000, P_GPLL0, 10, 0, 0),
>+ F(120000000, P_GPLL0, 5, 0, 0),
>+ { }
>+};
>+
>+static struct clk_rcg2 usb20_master_clk_src = {
>+ .cmd_rcgr = 0x2f010,
>+ .mnd_width = 8,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_usb20_master_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "usb20_master_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static const struct freq_tbl ftbl_usb20_mock_utmi_clk_src[] = {
>+ F(19200000, P_XO, 1, 0, 0),
>+ F(60000000, P_GPLL0, 10, 0, 0),
>+ { }
>+};
>+
>+static struct clk_rcg2 usb20_mock_utmi_clk_src = {
>+ .cmd_rcgr = 0x2f024,
>+ .mnd_width = 0,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_usb20_mock_utmi_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "usb20_mock_utmi_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
>+ F(19200000, P_XO, 1, 0, 0),
>+ F(66666667, P_GPLL0_EARLY_DIV, 4.5, 0, 0),
>+ F(120000000, P_GPLL0, 5, 0, 0),
>+ F(133333333, P_GPLL0, 4.5, 0, 0),
>+ F(150000000, P_GPLL0, 4, 0, 0),
>+ F(200000000, P_GPLL0, 3, 0, 0),
>+ F(240000000, P_GPLL0, 2.5, 0, 0),
>+ { }
>+};
>+
>+static struct clk_rcg2 usb30_master_clk_src = {
>+ .cmd_rcgr = 0xf014,
>+ .mnd_width = 8,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_usb30_master_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "usb30_master_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static const struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
>+ F(19200000, P_XO, 1, 0, 0),
>+ F(40000000, P_GPLL0_EARLY_DIV, 7.5, 0, 0),
>+ F(60000000, P_GPLL0, 10, 0, 0),
>+ { }
>+};
>+
>+static struct clk_rcg2 usb30_mock_utmi_clk_src = {
>+ .cmd_rcgr = 0xf028,
>+ .mnd_width = 0,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_gpll0_gpll0_early_div,
>+ .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "usb30_mock_utmi_clk_src",
>+ .parent_names = gcc_parent_names_xo_gpll0_gpll0_early_div,
>+ .num_parents = 3,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static const struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
>+ F(1200000, P_XO, 16, 0, 0),
>+ F(19200000, P_XO, 1, 0, 0),
>+ { }
>+};
>+
>+static struct clk_rcg2 usb3_phy_aux_clk_src = {
>+ .cmd_rcgr = 0x5000c,
>+ .mnd_width = 0,
>+ .hid_width = 5,
>+ .parent_map = gcc_parent_map_xo_sleep_clk,
>+ .freq_tbl = ftbl_usb3_phy_aux_clk_src,
>+ .clkr.hw.init = &(struct clk_init_data){
>+ .name = "usb3_phy_aux_clk_src",
>+ .parent_names = gcc_parent_names_xo_sleep_clk,
>+ .num_parents = 2,
>+ .ops = &clk_rcg2_ops,
>+ },
>+};
>+
>+static struct clk_branch gcc_aggre2_ufs_axi_clk = {
>+ .halt_reg = 0x75034,
>+ .halt_check = BRANCH_HALT,
>+ .clkr = {
>+ .enable_reg = 0x75034,
>+ .enable_mask = BIT(0),
>+ .hw.init = &(struct clk_init_data){
>+ .name = "gcc_aggre2_ufs_axi_clk",
>+ .parent_names = (const char *[]){
>+ "ufs_axi_clk_src",
>+ },
>+ .num_parents = 1,
>+ .ops = &clk_branch2_ops,
>+ },
>+ },
>+};
>+
>+static struct clk_branch gcc_aggre2_usb3_axi_clk = {
>+ .halt_reg = 0xf03c,
>+ .halt_check = BRANCH_HALT,
>+ .clkr = {
>+ .enable_reg = 0xf03c,
>+ .enable_mask = BIT(0),
>+ .hw.init = &(struct clk_init_data){
>+ .name = "gcc_aggre2_usb3_axi_clk",
>+ .parent_names = (const char *[]){
>+ "usb30_master_clk_src",
>+ },
>+ .num_parents = 1,
>+ .ops = &clk_branch2_ops,
>+ },
>+ },
>+};
>+
>+static struct clk_branch gcc_bimc_gfx_clk = {
>+ .halt_reg = 0x7106c,
>+ .halt_check = BRANCH_VOTED,
>+ .clkr = {
>+ .enable_reg = 0x7106c,
>+ .enable_mask = BIT(0),
>+ .hw.init = &(struct clk_init_data){
>+ .name = "gcc_bimc_gfx_clk",
>+ .ops = &clk_branch2_ops,
>+ },
>+ },
>+};
>+
>+static struct clk_branch gcc_bimc_hmss_axi_clk = {
>+ .halt_reg = 0x48004,
>+ .halt_check = BRANCH_HALT_VOTED,
>+ .clkr = {
>+ .enable_reg = 0x52004,
>+ .enable_mask = BIT(22),
>+ .hw.init = &(struct clk_init_data){
>+ .name = "gcc_bimc_hmss_axi_clk",
>+ .ops = &clk_branch2_ops,
>+ },
>+ },
>+};
>+
>+static struct clk_branch gcc_bimc_mss_q6_axi_clk = {
>+ .halt_reg = 0x4401c,
>+ .halt_check = BRANCH_HALT,
>+ .clkr = {
>+ .enable_reg = 0x4401c,
>+ .enable_mask = BIT(0),
>+ .hw.init = &(struct clk_init_data){
>+ .name = "gcc_bimc_mss_q6_axi_clk",
>+ .ops = &clk_branch2_ops,
>+ },
>+ },
>+};
>+
>+static struct clk_branch gcc_blsp1_ahb_clk = {
>+ .halt_reg = 0x17004,
>+ .halt_check = BRANCH_HALT_VOTED,
>+ .clkr = {
>+ .enable_reg = 0x52004,
>+ .enable_mask = BIT(17),
>+ .hw.init = &(struct clk_init_data){
>+ .name = "gcc_blsp1_ahb_clk",
>+ .ops = &clk_branch2_ops,
>+ },
>+ },
>+};
>+
>+static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3] clk: qcom: Add Global Clock controller (GCC) driver for SDM660
2018-09-25 17:35 ` [PATCH v3] " Craig Tatlor
` (2 preceding siblings ...)
2018-10-08 6:51 ` Craig
@ 2018-10-16 22:05 ` Stephen Boyd
3 siblings, 0 replies; 18+ messages in thread
From: Stephen Boyd @ 2018-10-16 22:05 UTC (permalink / raw)
To: Craig Tatlor
Cc: ctatlor97, linux-arm-msm, Taniya Das, Michael Turquette,
Rob Herring, Mark Rutland, Andy Gross, David Brown, linux-clk,
devicetree, linux-kernel, linux-soc
Quoting Craig Tatlor (2018-09-25 10:35:58)
> From: Taniya Das <tdas@codeaurora.org>
>
> Add support for the global clock controller found on SDM660
> based devices. This should allow most non-multimedia device
> drivers to probe and control their clocks.
> Based on CAF implementation.
>
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> [craig: rename parents to fit upstream, and other cleanups]
> Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
> ---
Applied to clk-next
But there was some noise:
drivers/clk/qcom/gcc-sdm660.c:2304:10: warning: Initializer entry defined twice
drivers/clk/qcom/gcc-sdm660.c:2306:10: also defined here
and I didn't like seeing gcc_660, so I applied this fixup on top:
diff --git a/drivers/clk/qcom/gcc-sdm660.c b/drivers/clk/qcom/gcc-sdm660.c
index 1722a9b181e2..9efb55092ebf 100644
--- a/drivers/clk/qcom/gcc-sdm660.c
+++ b/drivers/clk/qcom/gcc-sdm660.c
@@ -2253,12 +2253,12 @@ static struct gdsc pcie_0_gdsc = {
};
static struct clk_hw *gcc_sdm660_hws[] = {
- [GCC_XO] = &xo.hw,
- [GCC_GPLL0_EARLY_DIV] = &gpll0_early_div.hw,
- [GCC_GPLL1_EARLY_DIV] = &gpll1_early_div.hw,
+ &xo.hw,
+ &gpll0_early_div.hw,
+ &gpll1_early_div.hw,
};
-static struct clk_regmap *gcc_660_clocks[] = {
+static struct clk_regmap *gcc_sdm660_clocks[] = {
[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
@@ -2365,9 +2365,8 @@ static struct clk_regmap *gcc_660_clocks[] = {
[GPLL0_EARLY] = &gpll0_early.clkr,
[GPLL1] = &gpll1.clkr,
[GPLL1_EARLY] = &gpll1_early.clkr,
- [GPLL1] = &gpll1.clkr,
- [GPLL4_EARLY] = &gpll4_early.clkr,
[GPLL4] = &gpll4.clkr,
+ [GPLL4_EARLY] = &gpll4_early.clkr,
[HMSS_GPLL0_CLK_SRC] = &hmss_gpll0_clk_src.clkr,
[HMSS_GPLL4_CLK_SRC] = &hmss_gpll4_clk_src.clkr,
[HMSS_RBCPR_CLK_SRC] = &hmss_rbcpr_clk_src.clkr,
@@ -2387,13 +2386,13 @@ static struct clk_regmap *gcc_660_clocks[] = {
[USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
};
-static struct gdsc *gcc_660_gdscs[] = {
+static struct gdsc *gcc_sdm660_gdscs[] = {
[UFS_GDSC] = &ufs_gdsc,
[USB_30_GDSC] = &usb_30_gdsc,
[PCIE_0_GDSC] = &pcie_0_gdsc,
};
-static const struct qcom_reset_map gcc_660_resets[] = {
+static const struct qcom_reset_map gcc_sdm660_resets[] = {
[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
[GCC_UFS_BCR] = { 0x75000 },
@@ -2405,7 +2404,7 @@ static const struct qcom_reset_map gcc_660_resets[] = {
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
};
-static const struct regmap_config gcc_660_regmap_config = {
+static const struct regmap_config gcc_sdm660_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
@@ -2413,29 +2412,29 @@ static const struct regmap_config gcc_660_regmap_config = {
.fast_io = true,
};
-static const struct qcom_cc_desc gcc_660_desc = {
- .config = &gcc_660_regmap_config,
- .clks = gcc_660_clocks,
- .num_clks = ARRAY_SIZE(gcc_660_clocks),
- .resets = gcc_660_resets,
- .num_resets = ARRAY_SIZE(gcc_660_resets),
- .gdscs = gcc_660_gdscs,
- .num_gdscs = ARRAY_SIZE(gcc_660_gdscs),
+static const struct qcom_cc_desc gcc_sdm660_desc = {
+ .config = &gcc_sdm660_regmap_config,
+ .clks = gcc_sdm660_clocks,
+ .num_clks = ARRAY_SIZE(gcc_sdm660_clocks),
+ .resets = gcc_sdm660_resets,
+ .num_resets = ARRAY_SIZE(gcc_sdm660_resets),
+ .gdscs = gcc_sdm660_gdscs,
+ .num_gdscs = ARRAY_SIZE(gcc_sdm660_gdscs),
};
-static const struct of_device_id gcc_660_match_table[] = {
+static const struct of_device_id gcc_sdm660_match_table[] = {
{ .compatible = "qcom,gcc-sdm630" },
{ .compatible = "qcom,gcc-sdm660" },
{ }
};
-MODULE_DEVICE_TABLE(of, gcc_660_match_table);
+MODULE_DEVICE_TABLE(of, gcc_sdm660_match_table);
-static int gcc_660_probe(struct platform_device *pdev)
+static int gcc_sdm660_probe(struct platform_device *pdev)
{
int i, ret = 0;
struct regmap *regmap;
- regmap = qcom_cc_map(pdev, &gcc_660_desc);
+ regmap = qcom_cc_map(pdev, &gcc_sdm660_desc);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
@@ -2454,27 +2453,27 @@ static int gcc_660_probe(struct platform_device *pdev)
return ret;
}
- return qcom_cc_really_probe(pdev, &gcc_660_desc, regmap);
+ return qcom_cc_really_probe(pdev, &gcc_sdm660_desc, regmap);
}
-static struct platform_driver gcc_660_driver = {
- .probe = gcc_660_probe,
+static struct platform_driver gcc_sdm660_driver = {
+ .probe = gcc_sdm660_probe,
.driver = {
.name = "gcc-sdm660",
- .of_match_table = gcc_660_match_table,
+ .of_match_table = gcc_sdm660_match_table,
},
};
-static int __init gcc_660_init(void)
+static int __init gcc_sdm660_init(void)
{
- return platform_driver_register(&gcc_660_driver);
+ return platform_driver_register(&gcc_sdm660_driver);
}
-core_initcall_sync(gcc_660_init);
+core_initcall_sync(gcc_sdm660_init);
-static void __exit gcc_660_exit(void)
+static void __exit gcc_sdm660_exit(void)
{
- platform_driver_unregister(&gcc_660_driver);
+ platform_driver_unregister(&gcc_sdm660_driver);
}
-module_exit(gcc_660_exit);
+module_exit(gcc_sdm660_exit);
MODULE_DESCRIPTION("QCOM GCC sdm660 Driver");
diff --git a/include/dt-bindings/clock/qcom,gcc-sdm660.h b/include/dt-bindings/clock/qcom,gcc-sdm660.h
index 76aabcc5e7e3..468302282913 100644
--- a/include/dt-bindings/clock/qcom,gcc-sdm660.h
+++ b/include/dt-bindings/clock/qcom,gcc-sdm660.h
@@ -7,140 +7,137 @@
#ifndef _DT_BINDINGS_CLK_MSM_GCC_660_H
#define _DT_BINDINGS_CLK_MSM_GCC_660_H
-#define GCC_XO 0
-#define GCC_GPLL0_EARLY_DIV 1
-#define GCC_GPLL1_EARLY_DIV 2
-#define BLSP1_QUP1_I2C_APPS_CLK_SRC 3
-#define BLSP1_QUP1_SPI_APPS_CLK_SRC 4
-#define BLSP1_QUP2_I2C_APPS_CLK_SRC 5
-#define BLSP1_QUP2_SPI_APPS_CLK_SRC 6
-#define BLSP1_QUP3_I2C_APPS_CLK_SRC 7
-#define BLSP1_QUP3_SPI_APPS_CLK_SRC 8
-#define BLSP1_QUP4_I2C_APPS_CLK_SRC 9
-#define BLSP1_QUP4_SPI_APPS_CLK_SRC 10
-#define BLSP1_UART1_APPS_CLK_SRC 11
-#define BLSP1_UART2_APPS_CLK_SRC 12
-#define BLSP2_QUP1_I2C_APPS_CLK_SRC 13
-#define BLSP2_QUP1_SPI_APPS_CLK_SRC 14
-#define BLSP2_QUP2_I2C_APPS_CLK_SRC 15
-#define BLSP2_QUP2_SPI_APPS_CLK_SRC 16
-#define BLSP2_QUP3_I2C_APPS_CLK_SRC 17
-#define BLSP2_QUP3_SPI_APPS_CLK_SRC 18
-#define BLSP2_QUP4_I2C_APPS_CLK_SRC 19
-#define BLSP2_QUP4_SPI_APPS_CLK_SRC 20
-#define BLSP2_UART1_APPS_CLK_SRC 21
-#define BLSP2_UART2_APPS_CLK_SRC 22
-#define GCC_AGGRE2_UFS_AXI_CLK 23
-#define GCC_AGGRE2_USB3_AXI_CLK 24
-#define GCC_BIMC_GFX_CLK 25
-#define GCC_BIMC_HMSS_AXI_CLK 26
-#define GCC_BIMC_MSS_Q6_AXI_CLK 27
-#define GCC_BLSP1_AHB_CLK 28
-#define GCC_BLSP1_QUP1_I2C_APPS_CLK 29
-#define GCC_BLSP1_QUP1_SPI_APPS_CLK 30
-#define GCC_BLSP1_QUP2_I2C_APPS_CLK 31
-#define GCC_BLSP1_QUP2_SPI_APPS_CLK 32
-#define GCC_BLSP1_QUP3_I2C_APPS_CLK 33
-#define GCC_BLSP1_QUP3_SPI_APPS_CLK 34
-#define GCC_BLSP1_QUP4_I2C_APPS_CLK 35
-#define GCC_BLSP1_QUP4_SPI_APPS_CLK 36
-#define GCC_BLSP1_UART1_APPS_CLK 37
-#define GCC_BLSP1_UART2_APPS_CLK 38
-#define GCC_BLSP2_AHB_CLK 39
-#define GCC_BLSP2_QUP1_I2C_APPS_CLK 40
-#define GCC_BLSP2_QUP1_SPI_APPS_CLK 41
-#define GCC_BLSP2_QUP2_I2C_APPS_CLK 42
-#define GCC_BLSP2_QUP2_SPI_APPS_CLK 43
-#define GCC_BLSP2_QUP3_I2C_APPS_CLK 44
-#define GCC_BLSP2_QUP3_SPI_APPS_CLK 46
-#define GCC_BLSP2_QUP4_I2C_APPS_CLK 45
-#define GCC_BLSP2_QUP4_SPI_APPS_CLK 46
-#define GCC_BLSP2_UART1_APPS_CLK 47
-#define GCC_BLSP2_UART2_APPS_CLK 48
-#define GCC_BOOT_ROM_AHB_CLK 49
-#define GCC_CFG_NOC_USB2_AXI_CLK 50
-#define GCC_CFG_NOC_USB3_AXI_CLK 51
-#define GCC_DCC_AHB_CLK 52
-#define GCC_GP1_CLK 53
-#define GCC_GP2_CLK 54
-#define GCC_GP3_CLK 55
-#define GCC_GPU_BIMC_GFX_CLK 56
-#define GCC_GPU_CFG_AHB_CLK 57
-#define GCC_GPU_GPLL0_CLK 58
-#define GCC_GPU_GPLL0_DIV_CLK 59
-#define GCC_HMSS_DVM_BUS_CLK 60
-#define GCC_HMSS_RBCPR_CLK 61
-#define GCC_MMSS_GPLL0_CLK 62
-#define GCC_MMSS_GPLL0_DIV_CLK 63
-#define GCC_MMSS_NOC_CFG_AHB_CLK 64
-#define GCC_MMSS_SYS_NOC_AXI_CLK 65
-#define GCC_MSS_CFG_AHB_CLK 66
-#define GCC_MSS_GPLL0_DIV_CLK 67
-#define GCC_MSS_MNOC_BIMC_AXI_CLK 68
-#define GCC_MSS_Q6_BIMC_AXI_CLK 69
-#define GCC_MSS_SNOC_AXI_CLK 70
-#define GCC_PDM2_CLK 71
-#define GCC_PDM_AHB_CLK 72
-#define GCC_PRNG_AHB_CLK 73
-#define GCC_QSPI_AHB_CLK 74
-#define GCC_QSPI_SER_CLK 75
-#define GCC_SDCC1_AHB_CLK 76
-#define GCC_SDCC1_APPS_CLK 77
-#define GCC_SDCC1_ICE_CORE_CLK 78
-#define GCC_SDCC2_AHB_CLK 79
-#define GCC_SDCC2_APPS_CLK 80
-#define GCC_UFS_AHB_CLK 81
-#define GCC_UFS_AXI_CLK 82
-#define GCC_UFS_CLKREF_CLK 83
-#define GCC_UFS_ICE_CORE_CLK 84
-#define GCC_UFS_PHY_AUX_CLK 85
-#define GCC_UFS_RX_SYMBOL_0_CLK 86
-#define GCC_UFS_RX_SYMBOL_1_CLK 87
-#define GCC_UFS_TX_SYMBOL_0_CLK 88
-#define GCC_UFS_UNIPRO_CORE_CLK 89
-#define GCC_USB20_MASTER_CLK 90
-#define GCC_USB20_MOCK_UTMI_CLK 91
-#define GCC_USB20_SLEEP_CLK 92
-#define GCC_USB30_MASTER_CLK 93
-#define GCC_USB30_MOCK_UTMI_CLK 94
-#define GCC_USB30_SLEEP_CLK 95
-#define GCC_USB3_CLKREF_CLK 96
-#define GCC_USB3_PHY_AUX_CLK 97
-#define GCC_USB3_PHY_PIPE_CLK 98
-#define GCC_USB_PHY_CFG_AHB2PHY_CLK 99
-#define GP1_CLK_SRC 100
-#define GP2_CLK_SRC 101
-#define GP3_CLK_SRC 102
-#define GPLL0 103
-#define GPLL0_EARLY 104
-#define GPLL1 105
-#define GPLL1_EARLY 106
-#define GPLL4 107
-#define GPLL4_EARLY 108
-#define HMSS_GPLL0_CLK_SRC 109
-#define HMSS_GPLL4_CLK_SRC 110
-#define HMSS_RBCPR_CLK_SRC 111
-#define PDM2_CLK_SRC 112
-#define QSPI_SER_CLK_SRC 113
-#define SDCC1_APPS_CLK_SRC 114
-#define SDCC1_ICE_CORE_CLK_SRC 115
-#define SDCC2_APPS_CLK_SRC 116
-#define UFS_AXI_CLK_SRC 117
-#define UFS_ICE_CORE_CLK_SRC 118
-#define UFS_PHY_AUX_CLK_SRC 119
-#define UFS_UNIPRO_CORE_CLK_SRC 120
-#define USB20_MASTER_CLK_SRC 121
-#define USB20_MOCK_UTMI_CLK_SRC 122
-#define USB30_MASTER_CLK_SRC 123
-#define USB30_MOCK_UTMI_CLK_SRC 124
-#define USB3_PHY_AUX_CLK_SRC 125
-#define GPLL0_OUT_MSSCC 126
-#define GCC_UFS_AXI_HW_CTL_CLK 127
-#define GCC_UFS_ICE_CORE_HW_CTL_CLK 128
-#define GCC_UFS_PHY_AUX_HW_CTL_CLK 129
-#define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 130
-#define GCC_RX0_USB2_CLKREF_CLK 131
-#define GCC_RX1_USB2_CLKREF_CLK 132
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 0
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 1
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 2
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 3
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 4
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 5
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC 6
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC 7
+#define BLSP1_UART1_APPS_CLK_SRC 8
+#define BLSP1_UART2_APPS_CLK_SRC 9
+#define BLSP2_QUP1_I2C_APPS_CLK_SRC 10
+#define BLSP2_QUP1_SPI_APPS_CLK_SRC 11
+#define BLSP2_QUP2_I2C_APPS_CLK_SRC 12
+#define BLSP2_QUP2_SPI_APPS_CLK_SRC 13
+#define BLSP2_QUP3_I2C_APPS_CLK_SRC 14
+#define BLSP2_QUP3_SPI_APPS_CLK_SRC 15
+#define BLSP2_QUP4_I2C_APPS_CLK_SRC 16
+#define BLSP2_QUP4_SPI_APPS_CLK_SRC 17
+#define BLSP2_UART1_APPS_CLK_SRC 18
+#define BLSP2_UART2_APPS_CLK_SRC 19
+#define GCC_AGGRE2_UFS_AXI_CLK 20
+#define GCC_AGGRE2_USB3_AXI_CLK 21
+#define GCC_BIMC_GFX_CLK 22
+#define GCC_BIMC_HMSS_AXI_CLK 23
+#define GCC_BIMC_MSS_Q6_AXI_CLK 24
+#define GCC_BLSP1_AHB_CLK 25
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 26
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 27
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 28
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 29
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 30
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 31
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 32
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 33
+#define GCC_BLSP1_UART1_APPS_CLK 34
+#define GCC_BLSP1_UART2_APPS_CLK 35
+#define GCC_BLSP2_AHB_CLK 36
+#define GCC_BLSP2_QUP1_I2C_APPS_CLK 37
+#define GCC_BLSP2_QUP1_SPI_APPS_CLK 38
+#define GCC_BLSP2_QUP2_I2C_APPS_CLK 39
+#define GCC_BLSP2_QUP2_SPI_APPS_CLK 40
+#define GCC_BLSP2_QUP3_I2C_APPS_CLK 41
+#define GCC_BLSP2_QUP3_SPI_APPS_CLK 42
+#define GCC_BLSP2_QUP4_I2C_APPS_CLK 43
+#define GCC_BLSP2_QUP4_SPI_APPS_CLK 44
+#define GCC_BLSP2_UART1_APPS_CLK 45
+#define GCC_BLSP2_UART2_APPS_CLK 46
+#define GCC_BOOT_ROM_AHB_CLK 47
+#define GCC_CFG_NOC_USB2_AXI_CLK 48
+#define GCC_CFG_NOC_USB3_AXI_CLK 49
+#define GCC_DCC_AHB_CLK 50
+#define GCC_GP1_CLK 51
+#define GCC_GP2_CLK 52
+#define GCC_GP3_CLK 53
+#define GCC_GPU_BIMC_GFX_CLK 54
+#define GCC_GPU_CFG_AHB_CLK 55
+#define GCC_GPU_GPLL0_CLK 56
+#define GCC_GPU_GPLL0_DIV_CLK 57
+#define GCC_HMSS_DVM_BUS_CLK 58
+#define GCC_HMSS_RBCPR_CLK 59
+#define GCC_MMSS_GPLL0_CLK 60
+#define GCC_MMSS_GPLL0_DIV_CLK 61
+#define GCC_MMSS_NOC_CFG_AHB_CLK 62
+#define GCC_MMSS_SYS_NOC_AXI_CLK 63
+#define GCC_MSS_CFG_AHB_CLK 64
+#define GCC_MSS_GPLL0_DIV_CLK 65
+#define GCC_MSS_MNOC_BIMC_AXI_CLK 66
+#define GCC_MSS_Q6_BIMC_AXI_CLK 67
+#define GCC_MSS_SNOC_AXI_CLK 68
+#define GCC_PDM2_CLK 69
+#define GCC_PDM_AHB_CLK 70
+#define GCC_PRNG_AHB_CLK 71
+#define GCC_QSPI_AHB_CLK 72
+#define GCC_QSPI_SER_CLK 73
+#define GCC_SDCC1_AHB_CLK 74
+#define GCC_SDCC1_APPS_CLK 75
+#define GCC_SDCC1_ICE_CORE_CLK 76
+#define GCC_SDCC2_AHB_CLK 77
+#define GCC_SDCC2_APPS_CLK 78
+#define GCC_UFS_AHB_CLK 79
+#define GCC_UFS_AXI_CLK 80
+#define GCC_UFS_CLKREF_CLK 81
+#define GCC_UFS_ICE_CORE_CLK 82
+#define GCC_UFS_PHY_AUX_CLK 83
+#define GCC_UFS_RX_SYMBOL_0_CLK 84
+#define GCC_UFS_RX_SYMBOL_1_CLK 85
+#define GCC_UFS_TX_SYMBOL_0_CLK 86
+#define GCC_UFS_UNIPRO_CORE_CLK 87
+#define GCC_USB20_MASTER_CLK 88
+#define GCC_USB20_MOCK_UTMI_CLK 89
+#define GCC_USB20_SLEEP_CLK 90
+#define GCC_USB30_MASTER_CLK 91
+#define GCC_USB30_MOCK_UTMI_CLK 92
+#define GCC_USB30_SLEEP_CLK 93
+#define GCC_USB3_CLKREF_CLK 94
+#define GCC_USB3_PHY_AUX_CLK 95
+#define GCC_USB3_PHY_PIPE_CLK 96
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK 97
+#define GP1_CLK_SRC 98
+#define GP2_CLK_SRC 99
+#define GP3_CLK_SRC 100
+#define GPLL0 101
+#define GPLL0_EARLY 102
+#define GPLL1 103
+#define GPLL1_EARLY 104
+#define GPLL4 105
+#define GPLL4_EARLY 106
+#define HMSS_GPLL0_CLK_SRC 107
+#define HMSS_GPLL4_CLK_SRC 108
+#define HMSS_RBCPR_CLK_SRC 109
+#define PDM2_CLK_SRC 110
+#define QSPI_SER_CLK_SRC 111
+#define SDCC1_APPS_CLK_SRC 112
+#define SDCC1_ICE_CORE_CLK_SRC 113
+#define SDCC2_APPS_CLK_SRC 114
+#define UFS_AXI_CLK_SRC 115
+#define UFS_ICE_CORE_CLK_SRC 116
+#define UFS_PHY_AUX_CLK_SRC 117
+#define UFS_UNIPRO_CORE_CLK_SRC 118
+#define USB20_MASTER_CLK_SRC 119
+#define USB20_MOCK_UTMI_CLK_SRC 120
+#define USB30_MASTER_CLK_SRC 121
+#define USB30_MOCK_UTMI_CLK_SRC 122
+#define USB3_PHY_AUX_CLK_SRC 123
+#define GPLL0_OUT_MSSCC 124
+#define GCC_UFS_AXI_HW_CTL_CLK 125
+#define GCC_UFS_ICE_CORE_HW_CTL_CLK 126
+#define GCC_UFS_PHY_AUX_HW_CTL_CLK 127
+#define GCC_UFS_UNIPRO_CORE_HW_CTL_CLK 128
+#define GCC_RX0_USB2_CLKREF_CLK 129
+#define GCC_RX1_USB2_CLKREF_CLK 130
#define PCIE_0_GDSC 0
#define UFS_GDSC 1
^ permalink raw reply related [flat|nested] 18+ messages in thread
end of thread, other threads:[~2018-10-16 22:06 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
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[not found] <20180407135934.26122-1-ctatlor97@gmail.com>
2018-08-10 20:21 ` [PATCH] clk: qcom: Add Global Clock controller (GCC) driver for SDM660 Craig Tatlor
2018-08-11 21:30 ` kbuild test robot
2018-08-11 21:30 ` [RFC PATCH] clk: qcom: gcc_sdm660_hws[] can be static kbuild test robot
2018-08-13 6:55 ` [PATCH] clk: qcom: Add Global Clock controller (GCC) driver for SDM660 Taniya Das
2018-08-13 7:45 ` Craig Tatlor
2018-09-24 12:44 ` Heiko Stuebner
2018-09-24 12:44 ` Heiko Stuebner
2018-09-24 14:33 ` Craig
2018-09-24 14:33 ` Craig
2018-08-13 9:44 ` Craig Tatlor
2018-09-25 16:35 ` [PATCH v2] " Craig Tatlor
2018-09-25 16:35 ` Craig Tatlor
2018-09-25 17:35 ` [PATCH v3] " Craig Tatlor
2018-09-25 17:35 ` Craig Tatlor
2018-09-27 19:51 ` Rob Herring
2018-09-27 19:51 ` Rob Herring
2018-10-08 6:51 ` Craig
2018-10-16 22:05 ` Stephen Boyd
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