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From: Stephen Boyd <sboyd@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>,
	Paul Cercueil <paul@crapouillou.net>
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	Paul Cercueil <paul@crapouillou.net>,
	stable@vger.kernel.org
Subject: Re: [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock
Date: Wed, 17 Apr 2019 16:48:54 -0700	[thread overview]
Message-ID: <155554493444.15276.2577888773542833089@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20190417112420.3034-1-paul@crapouillou.net>

Quoting Paul Cercueil (2019-04-17 04:24:20)
> The pixel clock is directly connected to the output of the PLL, and not
> to the /2 divider.
> 
> Cc: stable@vger.kernel.org
> Fixes: 226dfa4726eb ("clk: Add Ingenic jz4725b CGU driver")
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---

Is this breaking something in 5.1-rc series? Or just found by
inspection? I'm trying to understand the priority of this patch.


  reply	other threads:[~2019-04-17 23:49 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-17 11:24 [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock Paul Cercueil
2019-04-17 23:48 ` Stephen Boyd [this message]
2019-04-17 23:53   ` Paul Cercueil
2019-04-18 20:32     ` Stephen Boyd
2019-04-18 21:58 ` Stephen Boyd
2019-04-29 20:53   ` Paul Cercueil
2019-04-29 22:59     ` Stephen Boyd

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