From: Paul Cercueil <paul@crapouillou.net>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
Paul Cercueil <paul@crapouillou.net>,
stable@vger.kernel.org
Subject: [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock
Date: Wed, 17 Apr 2019 13:24:20 +0200 [thread overview]
Message-ID: <20190417112420.3034-1-paul@crapouillou.net> (raw)
The pixel clock is directly connected to the output of the PLL, and not
to the /2 divider.
Cc: stable@vger.kernel.org
Fixes: 226dfa4726eb ("clk: Add Ingenic jz4725b CGU driver")
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
drivers/clk/ingenic/jz4725b-cgu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c
index 8901ea0295b7..76793b3d2ef8 100644
--- a/drivers/clk/ingenic/jz4725b-cgu.c
+++ b/drivers/clk/ingenic/jz4725b-cgu.c
@@ -102,7 +102,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
[JZ4725B_CLK_LCD] = {
"lcd", CGU_CLK_DIV | CGU_CLK_GATE,
- .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
+ .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
.div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
.gate = { CGU_REG_CLKGR, 9 },
},
--
2.21.0.593.g511ec345e18
next reply other threads:[~2019-04-17 11:24 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-17 11:24 Paul Cercueil [this message]
2019-04-17 23:48 ` [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock Stephen Boyd
2019-04-17 23:53 ` Paul Cercueil
2019-04-18 20:32 ` Stephen Boyd
2019-04-18 21:58 ` Stephen Boyd
2019-04-29 20:53 ` Paul Cercueil
2019-04-29 22:59 ` Stephen Boyd
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