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From: Stephen Boyd <sboyd@kernel.org>
To: Paul Cercueil <paul@crapouillou.net>
Cc: Michael Turquette <mturquette@baylibre.com>,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	stable@vger.kernel.org
Subject: Re: [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock
Date: Mon, 29 Apr 2019 15:59:19 -0700	[thread overview]
Message-ID: <155657875909.168659.9064792203031956186@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <1556571191.1721.0@crapouillou.net>

Quoting Paul Cercueil (2019-04-29 13:53:11)
> Hi Stephen,
> 
> Le jeu. 18 avril 2019 à 23:58, Stephen Boyd <sboyd@kernel.org> a 
> écrit :
> > Quoting Paul Cercueil (2019-04-17 04:24:20)
> >>  The pixel clock is directly connected to the output of the PLL, and 
> >> not
> >>  to the /2 divider.
> >> 
> >>  Cc: stable@vger.kernel.org
> >>  Fixes: 226dfa4726eb ("clk: Add Ingenic jz4725b CGU driver")
> >>  Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> >>  ---
> > 
> > Applied to clk-next
> 
> Could you drop this patch?
> 
> It turns out it is wrong and the pixel clock is really connected to the 
> "pll half"
> clock. The real bug was elsewhere: the "pll half" clock does not report 
> the correct
> rate. I will send a patch for this one later.
> 

Ok. No problem.


      reply	other threads:[~2019-04-29 22:59 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-17 11:24 [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock Paul Cercueil
2019-04-17 23:48 ` Stephen Boyd
2019-04-17 23:53   ` Paul Cercueil
2019-04-18 20:32     ` Stephen Boyd
2019-04-18 21:58 ` Stephen Boyd
2019-04-29 20:53   ` Paul Cercueil
2019-04-29 22:59     ` Stephen Boyd [this message]

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