From: Sowjanya Komatineni <skomatineni@nvidia.com> To: <skomatineni@nvidia.com>, <thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <broonie@kernel.org>, <lgirdwood@gmail.com>, <perex@perex.cz>, <tiwai@suse.com>, <digetx@gmail.com>, <mperttunen@nvidia.com>, <gregkh@linuxfoundation.org>, <sboyd@kernel.org>, <robh+dt@kernel.org>, <mark.rutland@arm.com> Cc: <pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>, <spujar@nvidia.com>, <josephl@nvidia.com>, <daniel.lezcano@linaro.org>, <mmaddireddy@nvidia.com>, <markz@nvidia.com>, <devicetree@vger.kernel.org>, <linux-clk@vger.kernel.org>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org> Subject: [PATCH v8 02/22] clk: tegra: Add support for OSC_DIV fixed clocks Date: Mon, 13 Jan 2020 23:24:07 -0800 Message-ID: <1578986667-16041-3-git-send-email-skomatineni@nvidia.com> (raw) In-Reply-To: <1578986667-16041-1-git-send-email-skomatineni@nvidia.com> Tegra30 through Tegra210 has OSC_DIV2 and OSC_DIV4 fixed clocks from the OSC pads. This patch adds support for these clocks. Tested-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- drivers/clk/tegra/clk-id.h | 2 ++ drivers/clk/tegra/clk-tegra-fixed.c | 16 ++++++++++++++++ drivers/clk/tegra/clk-tegra114.c | 4 ++++ drivers/clk/tegra/clk-tegra124.c | 4 ++++ drivers/clk/tegra/clk-tegra210.c | 4 ++++ drivers/clk/tegra/clk-tegra30.c | 4 ++++ 6 files changed, 34 insertions(+) diff --git a/drivers/clk/tegra/clk-id.h b/drivers/clk/tegra/clk-id.h index c4faebd32760..17d8b252cd0a 100644 --- a/drivers/clk/tegra/clk-id.h +++ b/drivers/clk/tegra/clk-id.h @@ -46,6 +46,8 @@ enum clk_id { tegra_clk_clk_m, tegra_clk_clk_m_div2, tegra_clk_clk_m_div4, + tegra_clk_osc_div2, + tegra_clk_osc_div4, tegra_clk_clk_out_1, tegra_clk_clk_out_1_mux, tegra_clk_clk_out_2, diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c index 7c6c8abfcde6..990106391334 100644 --- a/drivers/clk/tegra/clk-tegra-fixed.c +++ b/drivers/clk/tegra/clk-tegra-fixed.c @@ -48,6 +48,22 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, osc = clk_register_fixed_rate(NULL, "osc", NULL, 0, *osc_freq); + /* osc_div2 */ + dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div2, clks); + if (dt_clk) { + clk = clk_register_fixed_factor(NULL, "osc_div2", "osc", + 0, 1, 2); + *dt_clk = clk; + } + + /* osc_div4 */ + dt_clk = tegra_lookup_dt_id(tegra_clk_osc_div4, clks); + if (dt_clk) { + clk = clk_register_fixed_factor(NULL, "osc_div4", "osc", + 0, 1, 4); + *dt_clk = clk; + } + dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks); if (!dt_clk) return 0; diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index 4efcaaf51b3a..d44cb8db0ef6 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -737,6 +737,8 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = { [tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true }, [tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true }, [tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true }, + [tegra_clk_osc_div2] = { .dt_id = TEGRA114_CLK_OSC_DIV2, .present = true }, + [tegra_clk_osc_div4] = { .dt_id = TEGRA114_CLK_OSC_DIV4, .present = true }, [tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true }, [tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true }, [tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true }, @@ -817,6 +819,8 @@ static struct tegra_devclk devclks[] __initdata = { { .con_id = "clk_32k", .dt_id = TEGRA114_CLK_CLK_32K }, { .con_id = "clk_m_div2", .dt_id = TEGRA114_CLK_CLK_M_DIV2 }, { .con_id = "clk_m_div4", .dt_id = TEGRA114_CLK_CLK_M_DIV4 }, + { .con_id = "osc_div2", .dt_id = TEGRA114_CLK_OSC_DIV2 }, + { .con_id = "osc_div4", .dt_id = TEGRA114_CLK_OSC_DIV4 }, { .con_id = "pll_c", .dt_id = TEGRA114_CLK_PLL_C }, { .con_id = "pll_c_out1", .dt_id = TEGRA114_CLK_PLL_C_OUT1 }, { .con_id = "pll_c2", .dt_id = TEGRA114_CLK_PLL_C2 }, diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index b3110d5b5a6c..32f3dd1ccbad 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -862,6 +862,8 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = { [tegra_clk_clk_m] = { .dt_id = TEGRA124_CLK_CLK_M, .present = true }, [tegra_clk_clk_m_div2] = { .dt_id = TEGRA124_CLK_CLK_M_DIV2, .present = true }, [tegra_clk_clk_m_div4] = { .dt_id = TEGRA124_CLK_CLK_M_DIV4, .present = true }, + [tegra_clk_osc_div2] = { .dt_id = TEGRA124_CLK_OSC_DIV2, .present = true }, + [tegra_clk_osc_div4] = { .dt_id = TEGRA124_CLK_OSC_DIV4, .present = true }, [tegra_clk_pll_ref] = { .dt_id = TEGRA124_CLK_PLL_REF, .present = true }, [tegra_clk_pll_c] = { .dt_id = TEGRA124_CLK_PLL_C, .present = true }, [tegra_clk_pll_c_out1] = { .dt_id = TEGRA124_CLK_PLL_C_OUT1, .present = true }, @@ -943,6 +945,8 @@ static struct tegra_devclk devclks[] __initdata = { { .con_id = "clk_32k", .dt_id = TEGRA124_CLK_CLK_32K }, { .con_id = "clk_m_div2", .dt_id = TEGRA124_CLK_CLK_M_DIV2 }, { .con_id = "clk_m_div4", .dt_id = TEGRA124_CLK_CLK_M_DIV4 }, + { .con_id = "osc_div2", .dt_id = TEGRA124_CLK_OSC_DIV2 }, + { .con_id = "osc_div4", .dt_id = TEGRA124_CLK_OSC_DIV4 }, { .con_id = "pll_c", .dt_id = TEGRA124_CLK_PLL_C }, { .con_id = "pll_c_out1", .dt_id = TEGRA124_CLK_PLL_C_OUT1 }, { .con_id = "pll_c2", .dt_id = TEGRA124_CLK_PLL_C2 }, diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index 762cd186f714..899d8ca68c4f 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -2373,6 +2373,8 @@ static struct tegra_clk tegra210_clks[tegra_clk_max] __initdata = { [tegra_clk_clk_m] = { .dt_id = TEGRA210_CLK_CLK_M, .present = true }, [tegra_clk_clk_m_div2] = { .dt_id = TEGRA210_CLK_CLK_M_DIV2, .present = true }, [tegra_clk_clk_m_div4] = { .dt_id = TEGRA210_CLK_CLK_M_DIV4, .present = true }, + [tegra_clk_osc_div2] = { .dt_id = TEGRA210_CLK_OSC_DIV2, .present = true }, + [tegra_clk_osc_div4] = { .dt_id = TEGRA210_CLK_OSC_DIV4, .present = true }, [tegra_clk_pll_ref] = { .dt_id = TEGRA210_CLK_PLL_REF, .present = true }, [tegra_clk_pll_c] = { .dt_id = TEGRA210_CLK_PLL_C, .present = true }, [tegra_clk_pll_c_out1] = { .dt_id = TEGRA210_CLK_PLL_C_OUT1, .present = true }, @@ -2499,6 +2501,8 @@ static struct tegra_devclk devclks[] __initdata = { { .con_id = "clk_32k", .dt_id = TEGRA210_CLK_CLK_32K }, { .con_id = "clk_m_div2", .dt_id = TEGRA210_CLK_CLK_M_DIV2 }, { .con_id = "clk_m_div4", .dt_id = TEGRA210_CLK_CLK_M_DIV4 }, + { .con_id = "osc_div2", .dt_id = TEGRA210_CLK_OSC_DIV2 }, + { .con_id = "osc_div4", .dt_id = TEGRA210_CLK_OSC_DIV4 }, { .con_id = "pll_c", .dt_id = TEGRA210_CLK_PLL_C }, { .con_id = "pll_c_out1", .dt_id = TEGRA210_CLK_PLL_C_OUT1 }, { .con_id = "pll_c2", .dt_id = TEGRA210_CLK_PLL_C2 }, diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index c8bc18e4d7e5..c2da1f1d2b58 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -583,6 +583,8 @@ static struct tegra_devclk devclks[] __initdata = { { .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K }, { .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 }, { .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 }, + { .con_id = "osc_div2", .dt_id = TEGRA30_CLK_OSC_DIV2 }, + { .con_id = "osc_div4", .dt_id = TEGRA30_CLK_OSC_DIV4 }, { .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 }, { .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 }, { .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M }, @@ -685,6 +687,8 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = { [tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true }, [tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true }, [tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true }, + [tegra_clk_osc_div2] = { .dt_id = TEGRA30_CLK_OSC_DIV2, .present = true }, + [tegra_clk_osc_div4] = { .dt_id = TEGRA30_CLK_OSC_DIV4, .present = true }, [tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true }, [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true }, [tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true }, -- 2.7.4
next prev parent reply index Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-01-14 7:24 [PATCH v8 00/22] Move PMC clocks into Tegra PMC driver Sowjanya Komatineni 2020-01-14 7:24 ` [PATCH v8 01/22] dt-bindings: clock: tegra: Add IDs for OSC clocks Sowjanya Komatineni 2020-01-14 7:24 ` Sowjanya Komatineni [this message] 2020-01-14 7:24 ` [PATCH v8 03/22] clk: tegra: Add Tegra OSC to clock lookup Sowjanya Komatineni 2020-01-14 7:24 ` [PATCH v8 04/22] clk: tegra: Fix Tegra PMC clock out parents Sowjanya Komatineni 2020-01-14 7:24 ` [PATCH v8 05/22] clk: tegra: Remove CLK_M_DIV fixed clocks Sowjanya Komatineni 2020-01-14 7:24 ` [PATCH v8 06/22] dt-bindings: tegra: Convert Tegra PMC bindings to YAML Sowjanya Komatineni 2020-01-14 7:24 ` [PATCH v8 07/22] dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings Sowjanya Komatineni 2020-01-14 7:24 ` [PATCH v8 08/22] soc: tegra: Add Tegra PMC clocks registration into PMC driver Sowjanya Komatineni 2020-01-14 7:24 ` [PATCH v8 09/22] dt-bindings: soc: tegra-pmc: Add id for Tegra PMC 32KHz blink clock Sowjanya Komatineni 2020-01-14 7:24 ` [PATCH v8 10/22] soc: tegra: Add support for " Sowjanya Komatineni 2020-01-14 7:24 ` [PATCH v8 11/22] ASoC: tegra: Add fallback implementation for audio mclk Sowjanya Komatineni 2020-01-19 15:08 ` Dmitry Osipenko 2020-01-23 23:56 ` Dmitry Osipenko 2020-02-17 9:29 ` Thierry Reding 2020-02-17 9:40 ` Thierry Reding 2020-02-17 14:51 ` Dmitry Osipenko 2020-01-14 7:24 ` [PATCH v8 12/22] ASoC: tegra: Use device managed resource APIs to get the clock Sowjanya Komatineni 2020-02-17 9:48 ` Thierry Reding 2020-01-14 7:24 ` [PATCH v8 13/22] ARM: dts: tegra: Add clock-cells property to pmc Sowjanya Komatineni 2020-01-14 7:24 ` [PATCH v8 14/22] arm64: tegra: Add clock-cells property to Tegra PMC node Sowjanya Komatineni 2020-01-14 7:24 ` [PATCH v8 15/22] ARM: tegra: Update sound node clocks in device tree Sowjanya Komatineni 2020-01-14 7:24 ` [PATCH v8 16/22] arm64: tegra: smaug: Change clk_out_2 provider to pmc Sowjanya Komatineni 2020-01-14 7:24 ` [PATCH v8 17/22] ASoC: nau8825: change Tegra clk_out_2 provider to tegra_pmc Sowjanya Komatineni 2020-02-17 9:52 ` Thierry Reding 2020-01-14 7:24 ` [PATCH v8 18/22] ASoC: tegra: Add audio mclk parent configuration Sowjanya Komatineni 2020-02-17 9:53 ` Thierry Reding 2020-01-14 7:24 ` [PATCH v8 19/22] ASoC: tegra: Enable audio mclk during tegra_asoc_utils_init Sowjanya Komatineni 2020-01-19 15:14 ` Dmitry Osipenko 2020-01-20 4:10 ` Sameer Pujar 2020-01-20 15:32 ` Dmitry Osipenko 2020-02-17 9:53 ` Thierry Reding 2020-01-14 7:24 ` [PATCH v8 20/22] clk: tegra: Remove tegra_pmc_clk_init along with clk ids Sowjanya Komatineni 2020-02-17 9:55 ` Thierry Reding 2020-01-14 7:24 ` [PATCH v8 21/22] dt-bindings: clock: tegra: Remove pmc clock ids from clock dt-bindings Sowjanya Komatineni 2020-01-14 7:24 ` [PATCH v8 22/22] clk: tegra: Remove audio clocks configuration from clock driver Sowjanya Komatineni 2020-01-19 15:04 ` Dmitry Osipenko 2020-01-21 16:19 ` Sowjanya Komatineni 2020-01-21 16:57 ` Dmitry Osipenko 2020-01-24 4:34 ` Dmitry Osipenko 2020-01-24 8:50 ` Ben Dooks 2020-02-17 9:59 ` [PATCH v8 00/22] Move PMC clocks into Tegra PMC driver Thierry Reding 2020-03-04 19:26 ` Dmitry Osipenko 2020-03-04 21:22 ` Dmitry Osipenko 2020-03-25 21:27 ` Thierry Reding 2020-03-27 15:45 ` Mark Brown 2020-04-21 13:52 ` Jon Hunter
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