[GIT PULL]: Amlogic clock updates for v5.6

[GIT PULL]: Amlogic clock updates for v5.6

[Jerome Brunet]

Hi Stephen

Here are the updates for the amlogic clocks for this cycle.
The bulk of it is a clean up of the 32bits SoC clock controllers by
Martin.

Cheers
Jerome

The following changes since commit e42617b825f8073569da76dc4510bfa019b1c35a:

  Linux 5.5-rc1 (2019-12-08 14:57:55 -0800)

are available in the Git repository at:

  git://github.com/BayLibre/clk-meson.git tags/clk-meson-v5.6-1

for you to fetch changes up to 64c76b31774db5a0c0ce8df13aef618912136e32:

  clk: clarify that clk_set_rate() does updates from top to bottom (2020-01-07 11:31:47 +0100)

----------------------------------------------------------------
Amlogic clock updates for v5.6:
* Add meson8b DDR clock controller
* Add input clocks to meson8b controllers
* Fix meson8b mali clock update using the glitch free mux
* Fix pll driver division by zero init

----------------------------------------------------------------
Jerome Brunet (2):
      clk: meson: g12a: fix missing uart2 in regmap table
      Merge branch 'v5.5/fixes' into v5.6/drivers

Martin Blumenstingl (9):
      dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding
      dt-bindings: clock: meson8b: add the clock inputs
      clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller
      clk: meson: meson8b: use clk_hw_set_parent in the CPU clock notifier
      clk: meson: meson8b: change references to the XTAL clock to use [fw_]name
      clk: meson: meson8b: don't register the XTAL clock when provided via OF
      clk: meson: meson8b: use of_clk_hw_register to register the clocks
      clk: meson: meson8b: make the CCF use the glitch-free mali mux
      clk: clarify that clk_set_rate() does updates from top to bottom

Remi Pommarel (1):
      clk: meson: pll: Fix by 0 division in __pll_params_to_rate()

 .../bindings/clock/amlogic,meson8-ddr-clkc.yaml    |  50 +++++++
 .../bindings/clock/amlogic,meson8b-clkc.txt        |   5 +
 drivers/clk/meson/Makefile                         |   2 +-
 drivers/clk/meson/clk-pll.c                        |   9 ++
 drivers/clk/meson/g12a.c                           |   1 +
 drivers/clk/meson/meson8-ddr.c                     | 149 +++++++++++++++++++++
 drivers/clk/meson/meson8b.c                        | 124 +++++++++--------
 include/dt-bindings/clock/meson8-ddr-clkc.h        |   4 +
 include/linux/clk.h                                |   3 +
 9 files changed, 291 insertions(+), 56 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/amlogic,meson8-ddr-clkc.yaml
 create mode 100644 drivers/clk/meson/meson8-ddr.c
 create mode 100644 include/dt-bindings/clock/meson8-ddr-clkc.h

Re: [GIT PULL]: Amlogic clock updates for v5.6

[Stephen Boyd]

Quoting Jerome Brunet (2020-01-10 08:11:42)
> Hi Stephen
> 
> Here are the updates for the amlogic clocks for this cycle.
> The bulk of it is a clean up of the 32bits SoC clock controllers by
> Martin.
> 
> Cheers
> Jerome
> 
> The following changes since commit e42617b825f8073569da76dc4510bfa019b1c35a:
> 
>   Linux 5.5-rc1 (2019-12-08 14:57:55 -0800)
> 
> are available in the Git repository at:
> 
>   git://github.com/BayLibre/clk-meson.git tags/clk-meson-v5.6-1
> 
> for you to fetch changes up to 64c76b31774db5a0c0ce8df13aef618912136e32:
> 
>   clk: clarify that clk_set_rate() does updates from top to bottom (2020-01-07 11:31:47 +0100)
> 
> ----------------------------------------------------------------

Thanks. Pulled into clk-next