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* [PATCH 1/1] clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate
@ 2019-09-21 15:04 Martin Blumenstingl
  2019-09-23  8:38 ` Jerome Brunet
  2019-10-01 13:15 ` Jerome Brunet
  0 siblings, 2 replies; 3+ messages in thread
From: Martin Blumenstingl @ 2019-09-21 15:04 UTC (permalink / raw)
  To: narmstrong, jbrunet, linux-amlogic
  Cc: linux-kernel, linux-arm-kernel, linux-clk, Martin Blumenstingl

The meson-saradc driver manually sets the input clock for
sar_adc_clk_sel. Update the GXBB clock driver (which is used on GXBB,
GXL and GXM) so the rate settings on sar_adc_clk_div are propagated up
to sar_adc_clk_sel which will let the common clock framework select the
best matching parent clock if we want that.

This makes sar_adc_clk_div consistent with the axg-aoclk and g12a-aoclk
drivers, which both also specify CLK_SET_RATE_PARENT.

Fixes: 33d0fcdfe0e870 ("clk: gxbb: add the SAR ADC clocks and expose them")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
This is a small consistency fix which I found while debugging an
unrelated problem.

 drivers/clk/meson/gxbb.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 7cfb998eeb3e..1f9c056e684c 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -935,6 +935,7 @@ static struct clk_regmap gxbb_sar_adc_clk_div = {
 			&gxbb_sar_adc_clk_sel.hw
 		},
 		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
-- 
2.23.0


^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH 1/1] clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate
  2019-09-21 15:04 [PATCH 1/1] clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate Martin Blumenstingl
@ 2019-09-23  8:38 ` Jerome Brunet
  2019-10-01 13:15 ` Jerome Brunet
  1 sibling, 0 replies; 3+ messages in thread
From: Jerome Brunet @ 2019-09-23  8:38 UTC (permalink / raw)
  To: Martin Blumenstingl, narmstrong, linux-amlogic
  Cc: linux-kernel, linux-arm-kernel, linux-clk, Martin Blumenstingl

On Sat 21 Sep 2019 at 17:04, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:

> The meson-saradc driver manually sets the input clock for
> sar_adc_clk_sel. Update the GXBB clock driver (which is used on GXBB,
> GXL and GXM) so the rate settings on sar_adc_clk_div are propagated up
> to sar_adc_clk_sel which will let the common clock framework select the
> best matching parent clock if we want that.
>
> This makes sar_adc_clk_div consistent with the axg-aoclk and g12a-aoclk
> drivers, which both also specify CLK_SET_RATE_PARENT.
>
> Fixes: 33d0fcdfe0e870 ("clk: gxbb: add the SAR ADC clocks and expose them")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

Looks good. I'll apply it once rc1 is tagged
Thanks

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [PATCH 1/1] clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate
  2019-09-21 15:04 [PATCH 1/1] clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate Martin Blumenstingl
  2019-09-23  8:38 ` Jerome Brunet
@ 2019-10-01 13:15 ` Jerome Brunet
  1 sibling, 0 replies; 3+ messages in thread
From: Jerome Brunet @ 2019-10-01 13:15 UTC (permalink / raw)
  To: Martin Blumenstingl
  Cc: narmstrong, linux-amlogic, linux-kernel, linux-arm-kernel, linux-clk


On Sat 21 Sep 2019 at 17:04, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:

> The meson-saradc driver manually sets the input clock for
> sar_adc_clk_sel. Update the GXBB clock driver (which is used on GXBB,
> GXL and GXM) so the rate settings on sar_adc_clk_div are propagated up
> to sar_adc_clk_sel which will let the common clock framework select the
> best matching parent clock if we want that.
>
> This makes sar_adc_clk_div consistent with the axg-aoclk and g12a-aoclk
> drivers, which both also specify CLK_SET_RATE_PARENT.
>
> Fixes: 33d0fcdfe0e870 ("clk: gxbb: add the SAR ADC clocks and expose them")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

Applied, Thx

^ permalink raw reply	[flat|nested] 3+ messages in thread

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2019-09-21 15:04 [PATCH 1/1] clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate Martin Blumenstingl
2019-09-23  8:38 ` Jerome Brunet
2019-10-01 13:15 ` Jerome Brunet

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