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From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Nicolas Boichat <drinkcat@chromium.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Stephen Boyd <sboyd@codeaurora.org>,
	Rob Herring <robh@kernel.org>
Cc: James Liao <jamesjj.liao@mediatek.com>,
	Fan Chen <fan.chen@mediatek.com>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>,
	<srv_heupstream@mediatek.com>, <stable@vger.kernel.org>,
	Weiyi Lu <weiyi.lu@mediatek.com>
Subject: [PATCH v3 10/12] dt-bindings: soc: Add MT8183 power dt-bindings
Date: Mon, 10 Dec 2018 15:32:38 +0800
Message-ID: <20181210073240.32278-12-weiyi.lu@mediatek.com> (raw)
In-Reply-To: <20181210073240.32278-1-weiyi.lu@mediatek.com>

Add power dt-bindings for MT8183.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
 .../bindings/soc/mediatek/scpsys.txt          | 14 ++++++++++
 include/dt-bindings/power/mt8183-power.h      | 26 +++++++++++++++++++
 2 files changed, 40 insertions(+)
 create mode 100644 include/dt-bindings/power/mt8183-power.h

diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index d6fe16f094af..b4728ce81c43 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -14,6 +14,7 @@ power/power_domain.txt. It provides the power domains defined in
 - include/dt-bindings/power/mt2701-power.h
 - include/dt-bindings/power/mt2712-power.h
 - include/dt-bindings/power/mt7622-power.h
+- include/dt-bindings/power/mt8183-power.h
 
 Required properties:
 - compatible: Should be one of:
@@ -24,18 +25,31 @@ Required properties:
 	- "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys": For MT7623 SoC
 	- "mediatek,mt7623a-scpsys": For MT7623A SoC
 	- "mediatek,mt8173-scpsys"
+	- "mediatek,mt8183-scpsys"
 - #power-domain-cells: Must be 1
 - reg: Address range of the SCPSYS unit
 - infracfg: must contain a phandle to the infracfg controller
 - clock, clock-names: clocks according to the common clock binding.
                       These are clocks which hardware needs to be
                       enabled before enabling certain power domains.
+                      The new clock type "BASIC" belongs to the type above.
+                      As to the new clock type "SUBSYS" needs to be
+                      enabled before releasing bus protection.
 	Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif"
 	Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
 	Required clocks for MT6797: "mm", "mfg", "vdec"
 	Required clocks for MT7622: "hif_sel"
 	Required clocks for MT7622A: "ethif"
 	Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
+	Required clocks for MT8183: BASIC: "audio", "mfg", "mm", "cam", "isp",
+					   "vpu", "vpu1", "vpu2", "vpu3"
+				    SUBSYS: "mm-0", "mm-1", "mm-2", "mm-3",
+					    "mm-4", "mm-5", "mm-6", "mm-7",
+					    "mm-8", "mm-9", "isp-0", "isp-1",
+					    "cam-0", "cam-1", "cam-2", "cam-3",
+					    "cam-4", "cam-5", "cam-6", "vpu-0",
+					    "vpu-1", "vpu-2", "vpu-3", "vpu-4",
+					    "vpu-5"
 
 Optional properties:
 - vdec-supply: Power supply for the vdec power domain
diff --git a/include/dt-bindings/power/mt8183-power.h b/include/dt-bindings/power/mt8183-power.h
new file mode 100644
index 000000000000..5c0c8c7e3cd0
--- /dev/null
+++ b/include/dt-bindings/power/mt8183-power.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Weiyi Lu <weiyi.lu@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H
+#define _DT_BINDINGS_POWER_MT8183_POWER_H
+
+#define MT8183_POWER_DOMAIN_AUDIO	0
+#define MT8183_POWER_DOMAIN_CONN	1
+#define MT8183_POWER_DOMAIN_MFG_ASYNC	2
+#define MT8183_POWER_DOMAIN_MFG		3
+#define MT8183_POWER_DOMAIN_MFG_CORE0	4
+#define MT8183_POWER_DOMAIN_MFG_CORE1	5
+#define MT8183_POWER_DOMAIN_MFG_2D	6
+#define MT8183_POWER_DOMAIN_DISP	7
+#define MT8183_POWER_DOMAIN_CAM		8
+#define MT8183_POWER_DOMAIN_ISP		9
+#define MT8183_POWER_DOMAIN_VDEC	10
+#define MT8183_POWER_DOMAIN_VENC	11
+#define MT8183_POWER_DOMAIN_VPU_TOP	12
+#define MT8183_POWER_DOMAIN_VPU_CORE0	13
+#define MT8183_POWER_DOMAIN_VPU_CORE1	14
+
+#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */
-- 
2.18.0


  parent reply index

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-10  7:32 [PATCH v3 00/11] Mediatek MT8183 clock and scpsys support Weiyi Lu
2018-12-10  7:32 ` [PATCH v3 00/12] " Weiyi Lu
2018-12-10  7:32 ` [PATCH v3 01/12] clk: mediatek: fixup: Disable tuner_en before change PLL rate Weiyi Lu
2018-12-14 21:57   ` Stephen Boyd
2019-02-01  8:21     ` Weiyi Lu
2018-12-10  7:32 ` [PATCH v3 02/12] clk: mediatek: add new clkmux register API Weiyi Lu
2018-12-10 12:30   ` Nicolas Boichat
2019-02-01  8:22     ` Weiyi Lu
2018-12-10  7:32 ` [PATCH v3 03/12] clk: mediatek: add configurable pcwibits and fmin to mtk_pll_data Weiyi Lu
2018-12-14 22:02   ` Stephen Boyd
2019-02-01  8:22     ` Weiyi Lu
2018-12-10  7:32 ` [PATCH v3 04/12] soc: mediatek: add new flow for mtcmos power Weiyi Lu
2018-12-10 12:52   ` Nicolas Boichat
2018-12-10  7:32 ` [PATCH v3 05/12] dt-bindings: ARM: Mediatek: Document bindings for MT8183 Weiyi Lu
2018-12-14 21:57   ` Stephen Boyd
2018-12-10  7:32 ` [PATCH v3 06/12] clk: mediatek: Add dt-bindings for MT8183 clocks Weiyi Lu
2018-12-10  7:32 ` [PATCH v3 07/12] clk: mediatek: Add flags support for mtk_gate data Weiyi Lu
2018-12-10  7:32 ` [PATCH v3 08/12] clk: mediatek: Add MT8183 clock support Weiyi Lu
2018-12-11  1:00   ` Nicolas Boichat
2019-02-01  8:22     ` Weiyi Lu
2018-12-14 21:59   ` Stephen Boyd
2019-02-01  8:22     ` Weiyi Lu
2018-12-10  7:32 ` [PATCH v3 09/12] dt-bindings: soc: fix typo of MT8173 power dt-bindings Weiyi Lu
2018-12-10  7:32 ` Weiyi Lu [this message]
2018-12-10  7:32 ` [PATCH v3 11/12] soc: mediatek: Add MT8183 scpsys support Weiyi Lu
2018-12-10  7:32 ` [PATCH v3 12/12] clk: mediatek: Allow changing PLL rate when it is off Weiyi Lu
2018-12-14 22:01   ` Stephen Boyd
2019-02-01  8:22     ` Weiyi Lu

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