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* [PATCH v3 0/7] Add non PAS wcss Q6 support for QCS404
@ 2018-12-15 10:35 Govind Singh
  2018-12-15 10:35 ` [PATCH v3 1/7] dt-bindings: clock: qcom: Introduce QCOM WCSS Q6DSP clock bindings Govind Singh
                   ` (6 more replies)
  0 siblings, 7 replies; 20+ messages in thread
From: Govind Singh @ 2018-12-15 10:35 UTC (permalink / raw)
  To: bjorn.andersson, linux-remoteproc, sboyd
  Cc: linux-clk, sricharan, sibis, linux-arm-msm, andy.gross,
	david.brown, linux-soc, devicetree, Govind Singh

Add non PAS(Peripheral Authentication System) WCSS remoteproc
driver support and wcss clock/reset controls for QCS404 SOC.
Add WCSS q6 bootup and shutdown sequence handled from
Application Processor SubSystem(APSS).

Changes since v2:
 Removed unused properties.
 Refactored code to have common logic b/w ipq8074 and QCS404, wherever possible.
 Added compatible example.
 Removed wcss-protected bool.

Changes since v1:
  Corrected clock names as per comments in v1 patch.


Govind Singh (7):
  dt-bindings: clock: qcom: Introduce QCOM WCSS Q6DSP clock bindings
  clk: qcom: Add WCSS Q6DSP clock controller for QCS404
  dt-bindings: clock: qcom: Add QCOM WCSS GCC clock bindings
  clk: qcom: Add WCSS gcc clock control for QCS404
  remoteproc: qcom: wcss: populate hardcoded param using driver data
  remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404
  remoteproc: qcom: wcss: explicitly request exclusive reset control

 .../devicetree/bindings/clock/qcom,wcsscc.txt |  26 +
 .../bindings/remoteproc/qcom,q6v5.txt         |  61 ++
 drivers/clk/qcom/Kconfig                      |   9 +
 drivers/clk/qcom/Makefile                     |   1 +
 drivers/clk/qcom/gcc-qcs404.c                 |  51 +-
 drivers/clk/qcom/wcsscc-qcs404.c              | 297 +++++++++
 drivers/remoteproc/qcom_q6v5_wcss.c           | 574 +++++++++++++++++-
 include/dt-bindings/clock/qcom,gcc-qcs404.h   |   3 +
 include/dt-bindings/clock/qcom,wcss-qcs404.h  |  24 +
 9 files changed, 1016 insertions(+), 30 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,wcsscc.txt
 create mode 100644 drivers/clk/qcom/wcsscc-qcs404.c
 create mode 100644 include/dt-bindings/clock/qcom,wcss-qcs404.h

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH v3 1/7] dt-bindings: clock: qcom: Introduce QCOM WCSS Q6DSP clock bindings
  2018-12-15 10:35 [PATCH v3 0/7] Add non PAS wcss Q6 support for QCS404 Govind Singh
@ 2018-12-15 10:35 ` Govind Singh
  2018-12-17 19:33   ` Stephen Boyd
  2018-12-15 10:35 ` [PATCH v3 2/7] clk: qcom: Add WCSS Q6DSP clock controller for QCS404 Govind Singh
                   ` (5 subsequent siblings)
  6 siblings, 1 reply; 20+ messages in thread
From: Govind Singh @ 2018-12-15 10:35 UTC (permalink / raw)
  To: bjorn.andersson, linux-remoteproc, sboyd
  Cc: linux-clk, sricharan, sibis, linux-arm-msm, andy.gross,
	david.brown, linux-soc, devicetree, Govind Singh

Add device tree bindings for WiFi QDSP subsystem clock controls
found in OCS405 soc.

Signed-off-by: Govind Singh <govinds@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 .../devicetree/bindings/clock/qcom,wcsscc.txt | 26 +++++++++++++++++++
 include/dt-bindings/clock/qcom,wcss-qcs404.h  | 24 +++++++++++++++++
 2 files changed, 50 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,wcsscc.txt
 create mode 100644 include/dt-bindings/clock/qcom,wcss-qcs404.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,wcsscc.txt b/Documentation/devicetree/bindings/clock/qcom,wcsscc.txt
new file mode 100644
index 000000000000..2b19ef0b5689
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,wcsscc.txt
@@ -0,0 +1,26 @@
+Qualcomm WCSS Clock Controller Binding
+-----------------------------------------------
+
+Required properties :
+- compatible		: shall contain "qcom,qcs404-wcsscc"
+- #clock-cells		: from common clock binding, shall contain 1.
+- reg			: shall contain base register address and size,
+			  in the order
+			Index-0 maps to WCSS_Q6SSTOP clocks register region
+			Index-1 maps to WCSS_TCSR register region
+			Index-2 maps to WCSS_QDSP6SS register region
+
+Optional properties :
+- reg-names	: register names of WCSS domain
+		 "wcss_q6sstop", "wcnss_tcsr", "wcss_qdsp6ss".
+
+Example:
+The below node has to be defined in the cases where the WCSS peripheral loader
+would bring the subsystem out of reset.
+
+	clock_wcsscc: qcom,wcsscc@7000000 {
+		compatible = "qcom,qcs404-wcsscc";
+		reg = <0x07500000 0x4e000>, <0x07550000 0x8012>, <0x07400000 0x104>;
+		reg-names = "wcss_q6sstop", "wcnss_tcsr", "wcss_qdsp6ss";
+		#clock-cells = <1>;
+	};
diff --git a/include/dt-bindings/clock/qcom,wcss-qcs404.h b/include/dt-bindings/clock/qcom,wcss-qcs404.h
new file mode 100644
index 000000000000..45dd6599db81
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,wcss-qcs404.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_WCSS_QCS404_H
+#define _DT_BINDINGS_CLK_WCSS_QCS404_H
+
+#define WCSS_AHBFABRIC_CBCR_CLK			0
+#define WCSS_AHBS_CBCR_CLK			1
+#define WCSS_TCM_CBCR_CLK			2
+#define WCSS_AHBM_CBCR_CLK			3
+#define WCSS_AXIM_CBCR_CLK			4
+#define WCSS_BCR_CBCR_CLK			5
+#define WCSS_LCC_CBCR_CLK			6
+#define WCSS_QDSP6SS_XO_CBCR_CLK		7
+#define WCSS_QDSP6SS_SLEEP_CBCR_CLK		8
+#define WCSS_QDSP6SS_GFMMUX_CLK			9
+
+#define Q6SSTOP_QDSP6SS_RESET			0
+#define Q6SSTOP_QDSP6SS_CORE_RESET		1
+#define Q6SSTOP_QDSP6SS_BUS_RESET		2
+#define Q6SSTOP_BCR_RESET			3
+#endif
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH v3 2/7] clk: qcom: Add WCSS Q6DSP clock controller for QCS404
  2018-12-15 10:35 [PATCH v3 0/7] Add non PAS wcss Q6 support for QCS404 Govind Singh
  2018-12-15 10:35 ` [PATCH v3 1/7] dt-bindings: clock: qcom: Introduce QCOM WCSS Q6DSP clock bindings Govind Singh
@ 2018-12-15 10:35 ` Govind Singh
  2018-12-17 18:52   ` Stephen Boyd
  2018-12-15 10:35 ` [PATCH v3 3/7] dt-bindings: clock: qcom: Add QCOM WCSS GCC clock bindings Govind Singh
                   ` (4 subsequent siblings)
  6 siblings, 1 reply; 20+ messages in thread
From: Govind Singh @ 2018-12-15 10:35 UTC (permalink / raw)
  To: bjorn.andersson, linux-remoteproc, sboyd
  Cc: linux-clk, sricharan, sibis, linux-arm-msm, andy.gross,
	david.brown, linux-soc, devicetree, Govind Singh

Add support for the WCSS QDSP clock control used on qcs404
based devices. This would allow wcss remoteproc driver to
control the required WCSS QDSP clock/reset controls to
bring the subsystem out of reset and shutdown the WCSS QDSP.

Signed-off-by: Govind Singh <govinds@codeaurora.org>
---
 drivers/clk/qcom/Kconfig         |   9 +
 drivers/clk/qcom/Makefile        |   1 +
 drivers/clk/qcom/wcsscc-qcs404.c | 297 +++++++++++++++++++++++++++++++
 3 files changed, 307 insertions(+)
 create mode 100644 drivers/clk/qcom/wcsscc-qcs404.c

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 9fe28b9ceba8..84acc7718691 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -222,6 +222,15 @@ config QCS_GCC_404
 	  Say Y if you want to use multimedia devices or peripheral
 	  devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc.
 
+config QCS_WCSSCC_404
+	tristate "QCS404 WCSS Clock Controller"
+	depends on COMMON_CLK_QCOM
+	select QCS_GCC_404
+	help
+	  Support for the WCSS clock controller on QCS404 devices.
+	  Say Y if you want to use the WCSS branch clocks of the WCSS clock
+	  controller to reset the WCSS subsystem.
+
 config SDM_GCC_845
 	tristate "SDM845 Global Clock Controller"
 	select QCOM_GDSC
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 108c27d648a2..44563cb10cd5 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o
 obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
 obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o
 obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o
+obj-$(CONFIG_QCS_WCSSCC_404) += wcsscc-qcs404.o
 obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
 obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
 obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
diff --git a/drivers/clk/qcom/wcsscc-qcs404.c b/drivers/clk/qcom/wcsscc-qcs404.c
new file mode 100644
index 000000000000..bd694ef1b6ac
--- /dev/null
+++ b/drivers/clk/qcom/wcsscc-qcs404.c
@@ -0,0 +1,297 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
+
+#include <dt-bindings/clock/qcom,wcss-qcs404.h>
+#include <linux/reset-controller.h>
+
+#include "clk-regmap.h"
+#include "clk-branch.h"
+#include "common.h"
+#include "reset.h"
+
+/* Q6SSTOP clocks. These clocks are voted
+ * during by remoteproc client when loaded from
+ * user space, soc hang is seen when CCF turns
+ * off unused clocks. As a temp solution use
+ * CLK_IGNORE_UNUSED flags which prevent these
+ * clocks from being gated during bootup.
+ */
+static struct clk_branch lcc_ahbfabric_cbc_clk = {
+	.halt_reg = 0x1b004,
+	.halt_check = BRANCH_VOTED,
+	.clkr = {
+		.enable_reg = 0x1b004,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "lcc_ahbfabric_cbc_clk",
+			.ops = &clk_branch2_ops,
+			.flags = CLK_IGNORE_UNUSED,
+		},
+	},
+};
+
+static struct clk_branch lcc_q6ss_ahbs_cbc_clk = {
+	.halt_reg = 0x22000,
+	.halt_check = BRANCH_VOTED,
+	.clkr = {
+		.enable_reg = 0x22000,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "lcc_q6ss_ahbs_cbc_clk",
+			.ops = &clk_branch2_ops,
+			.flags = CLK_IGNORE_UNUSED,
+		},
+	},
+};
+
+static struct clk_branch lcc_q6ss_tcm_slave_cbc_clk = {
+	.halt_reg = 0x1c000,
+	.halt_check = BRANCH_VOTED,
+	.clkr = {
+		.enable_reg = 0x1c000,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "lcc_q6ss_tcm_slave_cbc_clk",
+			.ops = &clk_branch2_ops,
+			.flags = CLK_IGNORE_UNUSED,
+		},
+	},
+};
+
+static struct clk_branch lcc_q6ss_ahbm_cbc_clk = {
+	.halt_reg = 0x22004,
+	.halt_check = BRANCH_VOTED,
+	.clkr = {
+		.enable_reg = 0x22004,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "lcc_q6ss_ahbm_cbc_clk",
+			.ops = &clk_branch2_ops,
+			.flags = CLK_IGNORE_UNUSED,
+		},
+	},
+};
+
+static struct clk_branch lcc_q6ss_axim_cbc_clk = {
+	.halt_reg = 0x1c004,
+	.halt_check = BRANCH_VOTED,
+	.clkr = {
+		.enable_reg = 0x1c004,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "lcc_q6ss_axim_cbc_clk",
+			.ops = &clk_branch2_ops,
+			.flags = CLK_IGNORE_UNUSED,
+		},
+	},
+};
+
+static struct clk_branch lcc_q6ss_bcr_sleep_clk = {
+	.halt_reg = 0x6004,
+	.halt_check = BRANCH_VOTED,
+	.clkr = {
+		.enable_reg = 0x6004,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "lcc_q6ss_bcr_sleep_clk",
+			.ops = &clk_branch2_ops,
+			.flags = CLK_IGNORE_UNUSED,
+		},
+	},
+};
+
+/* TCSR clock */
+static struct clk_branch wcss_lcc_csr_cbcr_clk = {
+	.halt_reg = 0x8008,
+	.halt_check = BRANCH_VOTED,
+	.clkr = {
+		.enable_reg = 0x8008,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "wcss_lcc_csr_cbcr_clk",
+			.ops = &clk_branch2_ops,
+			.flags = CLK_IGNORE_UNUSED,
+		},
+	},
+};
+
+/* Q6SSTOP_QDSP6SS clock */
+static struct clk_branch q6ss_xo_clk = {
+	.halt_reg = 0x38,
+	/* CLK_OFF would not toggle until WCSS is out of reset */
+	.halt_check = BRANCH_HALT_SKIP,
+	.clkr = {
+		.enable_reg = 0x38,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "q6ss_xo_clk",
+			.ops = &clk_branch2_ops,
+			.flags = CLK_IGNORE_UNUSED,
+		},
+	},
+};
+
+static struct clk_branch q6ss_slp_clk = {
+	.halt_reg = 0x3c,
+	/* CLK_OFF would not toggle until WCSS is out of reset */
+	.halt_check = BRANCH_HALT_SKIP,
+	.clkr = {
+		.enable_reg = 0x3c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "q6ss_slp_clk",
+			.ops = &clk_branch2_ops,
+			.flags = CLK_IGNORE_UNUSED,
+		},
+	},
+};
+
+static struct clk_branch q6sstop_q6ss_gfmux_clk_src = {
+	.halt_reg = 0x20,
+	.halt_check = BRANCH_VOTED,
+	.clkr = {
+		.enable_reg = 0x20,
+		.enable_mask = BIT(1) | BIT(3) | BIT(8),
+		.hw.init = &(struct clk_init_data){
+			.name = "q6sstop_q6ss_gfmux_clk_src",
+			.ops = &clk_branch2_ops,
+			.flags = CLK_IGNORE_UNUSED,
+		},
+	},
+};
+
+static struct regmap_config wcss_regmap_config = {
+	.reg_bits	= 32,
+	.reg_stride	= 4,
+	.val_bits	= 32,
+	.fast_io	= true,
+};
+
+static struct clk_regmap *wcss_q6sstop_qcs404_clocks[] = {
+	[WCSS_AHBFABRIC_CBCR_CLK] = &lcc_ahbfabric_cbc_clk.clkr,
+	[WCSS_AHBS_CBCR_CLK] = &lcc_q6ss_ahbs_cbc_clk.clkr,
+	[WCSS_TCM_CBCR_CLK] = &lcc_q6ss_tcm_slave_cbc_clk.clkr,
+	[WCSS_AHBM_CBCR_CLK] = &lcc_q6ss_ahbm_cbc_clk.clkr,
+	[WCSS_AXIM_CBCR_CLK] = &lcc_q6ss_axim_cbc_clk.clkr,
+	[WCSS_BCR_CBCR_CLK] = &lcc_q6ss_bcr_sleep_clk.clkr,
+};
+
+static const struct qcom_reset_map qdsp6ss_qcs404_resets[] = {
+	[Q6SSTOP_QDSP6SS_RESET] = {0x14, 0},
+	[Q6SSTOP_QDSP6SS_CORE_RESET] = {0x14, 1},
+	[Q6SSTOP_QDSP6SS_BUS_RESET] = {0x14, 2},
+};
+
+static const struct qcom_reset_map q6sstop_qcs404_resets[] = {
+	[Q6SSTOP_BCR_RESET] = {0x6000},
+};
+
+static const struct qcom_cc_desc wcss_q6sstop_qcs404_desc = {
+	.config = &wcss_regmap_config,
+	.clks = wcss_q6sstop_qcs404_clocks,
+	.num_clks = ARRAY_SIZE(wcss_q6sstop_qcs404_clocks),
+	.resets = q6sstop_qcs404_resets,
+	.num_resets = ARRAY_SIZE(q6sstop_qcs404_resets),
+};
+
+static struct clk_regmap *wcnss_tcsr_qcs404_clocks[] = {
+	[WCSS_LCC_CBCR_CLK] = &wcss_lcc_csr_cbcr_clk.clkr,
+};
+
+static const struct qcom_cc_desc wcnss_tcsr_qcs404_desc = {
+	.config = &wcss_regmap_config,
+	.clks = wcnss_tcsr_qcs404_clocks,
+	.num_clks = ARRAY_SIZE(wcnss_tcsr_qcs404_clocks),
+};
+
+static struct clk_regmap *wcnss_qdsp6ss_qcs404_clocks[] = {
+	[WCSS_QDSP6SS_XO_CBCR_CLK] = &q6ss_xo_clk.clkr,
+	[WCSS_QDSP6SS_SLEEP_CBCR_CLK] = &q6ss_slp_clk.clkr,
+	[WCSS_QDSP6SS_GFMMUX_CLK] = &q6sstop_q6ss_gfmux_clk_src.clkr,
+};
+
+static const struct qcom_cc_desc wcnss_qdsp6ss_qcs404_desc = {
+	.config = &wcss_regmap_config,
+	.clks = wcnss_qdsp6ss_qcs404_clocks,
+	.num_clks = ARRAY_SIZE(wcnss_qdsp6ss_qcs404_clocks),
+	.resets = qdsp6ss_qcs404_resets,
+	.num_resets = ARRAY_SIZE(qdsp6ss_qcs404_resets),
+};
+
+static int wcss_clocks_qcs404_probe(struct platform_device *pdev, int index,
+				    const struct qcom_cc_desc *desc)
+{
+	struct regmap *regmap;
+	struct resource *res;
+	void __iomem *base;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, index);
+	base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(base))
+		return -ENOMEM;
+
+	regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config);
+	if (IS_ERR(regmap))
+		return PTR_ERR(regmap);
+
+	return qcom_cc_really_probe(pdev, desc, regmap);
+}
+
+static const struct of_device_id wcss_cc_qcs404_match_table[] = {
+	{ .compatible = "qcom,qcs404-wcsscc" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, wcss_cc_qcs404_match_table);
+
+static int wcss_cc_qcs404_probe(struct platform_device *pdev)
+{
+	const struct qcom_cc_desc *desc;
+	int ret;
+
+	wcss_regmap_config.name = "wcss_q6sstop";
+	desc = &wcss_q6sstop_qcs404_desc;
+
+	ret = wcss_clocks_qcs404_probe(pdev, 0, desc);
+	if (ret)
+		return ret;
+
+	wcss_regmap_config.name = "wcnss_tcsr";
+	desc = &wcnss_tcsr_qcs404_desc;
+
+	ret = wcss_clocks_qcs404_probe(pdev, 1, desc);
+	if (ret)
+		return ret;
+
+	wcss_regmap_config.name = "wcss_qdsp6ss";
+	desc = &wcnss_qdsp6ss_qcs404_desc;
+
+	return wcss_clocks_qcs404_probe(pdev, 2, desc);
+}
+
+static struct platform_driver wcss_cc_qcs404_driver = {
+	.probe		= wcss_cc_qcs404_probe,
+	.driver		= {
+		.name	= "qcs404-wcsscc",
+		.of_match_table = wcss_cc_qcs404_match_table,
+	},
+};
+
+static int __init wcss_cc_qcs404_init(void)
+{
+	return platform_driver_register(&wcss_cc_qcs404_driver);
+}
+subsys_initcall(wcss_cc_qcs404_init);
+
+MODULE_LICENSE("GPL v2");
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH v3 3/7] dt-bindings: clock: qcom: Add QCOM WCSS GCC clock bindings
  2018-12-15 10:35 [PATCH v3 0/7] Add non PAS wcss Q6 support for QCS404 Govind Singh
  2018-12-15 10:35 ` [PATCH v3 1/7] dt-bindings: clock: qcom: Introduce QCOM WCSS Q6DSP clock bindings Govind Singh
  2018-12-15 10:35 ` [PATCH v3 2/7] clk: qcom: Add WCSS Q6DSP clock controller for QCS404 Govind Singh
@ 2018-12-15 10:35 ` Govind Singh
  2018-12-17 19:34   ` Stephen Boyd
  2018-12-15 10:35 ` [PATCH v3 4/7] clk: qcom: Add WCSS gcc clock control for QCS404 Govind Singh
                   ` (3 subsequent siblings)
  6 siblings, 1 reply; 20+ messages in thread
From: Govind Singh @ 2018-12-15 10:35 UTC (permalink / raw)
  To: bjorn.andersson, linux-remoteproc, sboyd
  Cc: linux-clk, sricharan, sibis, linux-arm-msm, andy.gross,
	david.brown, linux-soc, devicetree, Govind Singh

Add device tree bindings for WiFi QDSP gcc clock controls found in
QCS404 soc.

Signed-off-by: Govind Singh <govinds@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
 include/dt-bindings/clock/qcom,gcc-qcs404.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h
index 00ab0d77b38a..8f800adda225 100644
--- a/include/dt-bindings/clock/qcom,gcc-qcs404.h
+++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
@@ -146,6 +146,8 @@
 #define GCC_MDP_TBU_CLK					138
 #define GCC_QDSS_DAP_CLK				139
 #define GCC_DCC_XO_CLK					140
+#define GCC_WCSS_Q6_AHB_CBCR_CLK			141
+#define GCC_WCSS_Q6_AXIM_CBCR_CLK			142
 
 #define GCC_GENI_IR_BCR					0
 #define GCC_USB_HS_BCR					1
@@ -168,5 +170,6 @@
 #define GCC_PCIE_0_CORE_STICKY_ARES			18
 #define GCC_PCIE_0_SLEEP_ARES				19
 #define GCC_PCIE_0_PIPE_ARES				20
+#define GCC_WDSP_RESTART				21
 
 #endif
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH v3 4/7] clk: qcom: Add WCSS gcc clock control for QCS404
  2018-12-15 10:35 [PATCH v3 0/7] Add non PAS wcss Q6 support for QCS404 Govind Singh
                   ` (2 preceding siblings ...)
  2018-12-15 10:35 ` [PATCH v3 3/7] dt-bindings: clock: qcom: Add QCOM WCSS GCC clock bindings Govind Singh
@ 2018-12-15 10:35 ` Govind Singh
  2018-12-15 17:56   ` Bjorn Andersson
  2018-12-17 18:53   ` Stephen Boyd
  2018-12-15 10:35 ` [PATCH v3 5/7] remoteproc: qcom: wcss: populate hardcoded param using driver data Govind Singh
                   ` (2 subsequent siblings)
  6 siblings, 2 replies; 20+ messages in thread
From: Govind Singh @ 2018-12-15 10:35 UTC (permalink / raw)
  To: bjorn.andersson, linux-remoteproc, sboyd
  Cc: linux-clk, sricharan, sibis, linux-arm-msm, andy.gross,
	david.brown, linux-soc, devicetree, Govind Singh

Add support for the WCSS QDSP gcc clock control used on qcs404 based devices.
This would allow wcss remoteproc driver to control the required gcc clocks to
bring the subsystem out of reset.

Signed-off-by: Govind Singh <govinds@codeaurora.org>
---
 drivers/clk/qcom/gcc-qcs404.c | 51 ++++++++++++++++++++++++++++++++++-
 1 file changed, 50 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index f5235cc2d3f1..efb28cff1102 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -2520,6 +2520,32 @@ static struct clk_branch gcc_usb_hs_system_clk = {
 	},
 };
 
+static struct clk_branch gcc_wdsp_q6ss_ahbs_clk = {
+	.halt_reg = 0x1e004,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x1e004,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_wdsp_q6ss_ahbs_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_wdsp_q6ss_axim_clk = {
+	.halt_reg = 0x1e008,
+	.halt_check = BRANCH_HALT,
+	.clkr = {
+		.enable_reg = 0x1e008,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_wdsp_q6ss_axim_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
 static struct clk_hw *gcc_qcs404_hws[] = {
 	&cxo.hw,
 };
@@ -2661,6 +2687,9 @@ static struct clk_regmap *gcc_qcs404_clocks[] = {
 	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
 	[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
 	[GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr,
+	[GCC_WCSS_Q6_AHB_CBCR_CLK] = NULL,
+	[GCC_WCSS_Q6_AXIM_CBCR_CLK] =  NULL,
+
 };
 
 static const struct qcom_reset_map gcc_qcs404_resets[] = {
@@ -2685,6 +2714,21 @@ static const struct qcom_reset_map gcc_qcs404_resets[] = {
 	[GCC_PCIE_0_SLEEP_ARES] = {0x3e040, 1},
 	[GCC_PCIE_0_PIPE_ARES] = {0x3e040, 0},
 	[GCC_EMAC_BCR] = { 0x4e000 },
+	[GCC_GENI_IR_BCR] = {0x0F000},
+	[GCC_USB_HS_BCR] = {0x41000},
+	[GCC_USB2_HS_PHY_ONLY_BCR] = {0x41034},
+	[GCC_QUSB2_PHY_BCR] = {0x4103C},
+	[GCC_USB_HS_PHY_CFG_AHB_BCR] = {0x0000C, 1},
+	[GCC_USB2A_PHY_BCR] = {0x0000C, 0},
+	[GCC_USB3_PHY_BCR] = {0x39004},
+	[GCC_USB_30_BCR] = {0x39000},
+	[GCC_USB3PHY_PHY_BCR] = {0x39008},
+	[GCC_PCIE_0_BCR] = {0x3E000},
+	[GCC_PCIE_0_PHY_BCR] = {0x3E004},
+	[GCC_PCIE_0_LINK_DOWN_BCR] = {0x3E038},
+	[GCC_PCIEPHY_0_PHY_BCR] = {0x3E03C},
+	[GCC_EMAC_BCR] = {0x4E000},
+	[GCC_WDSP_RESTART] = {0x19000},
 };
 
 static const struct regmap_config gcc_qcs404_regmap_config = {
@@ -2695,7 +2739,7 @@ static const struct regmap_config gcc_qcs404_regmap_config = {
 	.fast_io	= true,
 };
 
-static const struct qcom_cc_desc gcc_qcs404_desc = {
+static struct qcom_cc_desc gcc_qcs404_desc = {
 	.config = &gcc_qcs404_regmap_config,
 	.clks = gcc_qcs404_clocks,
 	.num_clks = ARRAY_SIZE(gcc_qcs404_clocks),
@@ -2726,6 +2770,11 @@ static int gcc_qcs404_probe(struct platform_device *pdev)
 			return ret;
 	}
 
+#ifdef CONFIG_QCS_WCSSCC_404
+		gcc_qcs404_clocks[GCC_WCSS_Q6_AHB_CBCR_CLK] = &gcc_wdsp_q6ss_ahbs_clk.clkr;
+		gcc_qcs404_clocks[GCC_WCSS_Q6_AXIM_CBCR_CLK] = &gcc_wdsp_q6ss_axim_clk.clkr;
+#endif
+
 	return qcom_cc_really_probe(pdev, &gcc_qcs404_desc, regmap);
 }
 
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH v3 5/7] remoteproc: qcom: wcss: populate hardcoded param using driver data
  2018-12-15 10:35 [PATCH v3 0/7] Add non PAS wcss Q6 support for QCS404 Govind Singh
                   ` (3 preceding siblings ...)
  2018-12-15 10:35 ` [PATCH v3 4/7] clk: qcom: Add WCSS gcc clock control for QCS404 Govind Singh
@ 2018-12-15 10:35 ` Govind Singh
  2018-12-17 18:55   ` Stephen Boyd
  2018-12-15 10:35 ` [PATCH v3 6/7] remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404 Govind Singh
  2018-12-15 10:35 ` [PATCH v3 7/7] remoteproc: qcom: wcss: explicitly request exclusive reset control Govind Singh
  6 siblings, 1 reply; 20+ messages in thread
From: Govind Singh @ 2018-12-15 10:35 UTC (permalink / raw)
  To: bjorn.andersson, linux-remoteproc, sboyd
  Cc: linux-clk, sricharan, sibis, linux-arm-msm, andy.gross,
	david.brown, linux-soc, devicetree, Govind Singh

Q6 based WiFi fw loading is supported across
different targets, ex: IPQ8074/QCS404. In order to
support different fw names/pas id etc, populate
hardcoded param using driver data.

Signed-off-by: Govind Singh <govinds@codeaurora.org>
---
 drivers/remoteproc/qcom_q6v5_wcss.c | 40 ++++++++++++++++++++++++-----
 1 file changed, 34 insertions(+), 6 deletions(-)

diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c
index f93e1e4a1cc0..129f82404656 100644
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -8,6 +8,7 @@
 #include <linux/kernel.h>
 #include <linux/mfd/syscon.h>
 #include <linux/module.h>
+#include <linux/of_device.h>
 #include <linux/of_reserved_mem.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
@@ -16,7 +17,6 @@
 #include "qcom_common.h"
 #include "qcom_q6v5.h"
 
-#define WCSS_CRASH_REASON		421
 
 /* Q6SS Register Offsets */
 #define Q6SS_RESET_REG		0x014
@@ -70,6 +70,14 @@
 #define TCSR_WCSS_CLK_MASK	0x1F
 #define TCSR_WCSS_CLK_ENABLE	0x14
 
+struct wcss_data {
+	void (*pas_handover)(struct qcom_q6v5 *q6v5);
+	const char *firmware_name;
+	int crash_reason_smem;
+	int version;
+	int pas_id;
+};
+
 struct q6v5_wcss {
 	struct device *dev;
 
@@ -91,6 +99,10 @@ struct q6v5_wcss {
 	phys_addr_t mem_reloc;
 	void *mem_region;
 	size_t mem_size;
+
+	int crash_reason_smem;
+	int pas_id;
+	int version;
 };
 
 static int q6v5_wcss_reset(struct q6v5_wcss *wcss)
@@ -427,7 +439,7 @@ static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw)
 				     wcss->mem_size, &wcss->mem_reloc);
 }
 
-static const struct rproc_ops q6v5_wcss_ops = {
+static const struct rproc_ops q6v5_wcss_ipq8074_ops = {
 	.start = q6v5_wcss_start,
 	.stop = q6v5_wcss_stop,
 	.da_to_va = q6v5_wcss_da_to_va,
@@ -527,12 +539,17 @@ static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss)
 
 static int q6v5_wcss_probe(struct platform_device *pdev)
 {
+	const struct wcss_data *desc;
 	struct q6v5_wcss *wcss;
 	struct rproc *rproc;
 	int ret;
 
-	rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_wcss_ops,
-			    "IPQ8074/q6_fw.mdt", sizeof(*wcss));
+	desc = of_device_get_match_data(&pdev->dev);
+	if (!desc)
+		return -EINVAL;
+
+	rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_wcss_ipq8074_ops,
+			    desc->firmware_name, sizeof(*wcss));
 	if (!rproc) {
 		dev_err(&pdev->dev, "failed to allocate rproc\n");
 		return -ENOMEM;
@@ -540,6 +557,9 @@ static int q6v5_wcss_probe(struct platform_device *pdev)
 
 	wcss = rproc->priv;
 	wcss->dev = &pdev->dev;
+	wcss->pas_id = desc->pas_id;
+	wcss->version = desc->version;
+	wcss->crash_reason_smem = desc->crash_reason_smem;
 
 	ret = q6v5_wcss_init_mmio(wcss, pdev);
 	if (ret)
@@ -553,7 +573,8 @@ static int q6v5_wcss_probe(struct platform_device *pdev)
 	if (ret)
 		goto free_rproc;
 
-	ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, WCSS_CRASH_REASON, NULL);
+	ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, desc->crash_reason_smem,
+			     desc->pas_handover);
 	if (ret)
 		goto free_rproc;
 
@@ -581,8 +602,15 @@ static int q6v5_wcss_remove(struct platform_device *pdev)
 	return 0;
 }
 
+static const struct wcss_data wcss_ipq8074_res_init = {
+	.firmware_name = "IPQ8074/q6_fw.mdt",
+	.crash_reason_smem = 421,
+	.pas_handover = NULL,
+};
+
 static const struct of_device_id q6v5_wcss_of_match[] = {
-	{ .compatible = "qcom,ipq8074-wcss-pil" },
+	{ .compatible = "qcom,ipq8074-wcss-pil", .data = &wcss_ipq8074_res_init },
+
 	{ },
 };
 MODULE_DEVICE_TABLE(of, q6v5_wcss_of_match);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH v3 6/7] remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404
  2018-12-15 10:35 [PATCH v3 0/7] Add non PAS wcss Q6 support for QCS404 Govind Singh
                   ` (4 preceding siblings ...)
  2018-12-15 10:35 ` [PATCH v3 5/7] remoteproc: qcom: wcss: populate hardcoded param using driver data Govind Singh
@ 2018-12-15 10:35 ` Govind Singh
  2018-12-17 19:00   ` Stephen Boyd
  2018-12-17 20:48   ` Rob Herring
  2018-12-15 10:35 ` [PATCH v3 7/7] remoteproc: qcom: wcss: explicitly request exclusive reset control Govind Singh
  6 siblings, 2 replies; 20+ messages in thread
From: Govind Singh @ 2018-12-15 10:35 UTC (permalink / raw)
  To: bjorn.andersson, linux-remoteproc, sboyd
  Cc: linux-clk, sricharan, sibis, linux-arm-msm, andy.gross,
	david.brown, linux-soc, devicetree, Govind Singh

Add non PAS WCSS remoteproc driver support for QCS404 SOC.
Add WCSS q6 bootup and shutdown sequence handled from
Application Processor SubSystem(APSS).

Signed-off-by: Govind Singh <govinds@codeaurora.org>
---
 .../bindings/remoteproc/qcom,q6v5.txt         |  61 ++
 drivers/remoteproc/qcom_q6v5_wcss.c           | 544 +++++++++++++++++-
 2 files changed, 577 insertions(+), 28 deletions(-)

diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
index 9ff5b0309417..9372dedcd7e2 100644
--- a/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt
@@ -13,6 +13,7 @@ on the Qualcomm Hexagon core.
 		    "qcom,msm8974-mss-pil"
 		    "qcom,msm8996-mss-pil"
 		    "qcom,sdm845-mss-pil"
+		    "qcom,qcs404-wcss-pil"
 
 - reg:
 	Usage: required
@@ -153,3 +154,63 @@ Hexagon, as it is found on MSM8974 boards.
 			memory-region = <&mpss_region>;
 		};
 	};
+
+	remoteproc-wcss {
+		compatible = "qcom,qcs404-wcss-pil";
+		reg = <0x07400000 0x00104>, <0x07500000 0x4e000>;
+		reg-names = "qdsp6", "q6stop";
+
+		interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
+				      <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+				      <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+				      <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+				      <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "wdog", "fatal", "ready",
+				  "handover", "stop-ack";
+
+		clocks = <&xo_board>,
+			 <&gcc GCC_WCSS_Q6_AHB_CBCR_CLK>,
+			 <&gcc GCC_WCSS_Q6_AXIM_CBCR_CLK>,
+
+			 <&clock_wcsscc WCSS_AHBFABRIC_CBCR_CLK>,
+			 <&clock_wcsscc WCSS_LCC_CBCR_CLK>,
+			 <&clock_wcsscc WCSS_AHBS_CBCR_CLK>,
+			 <&clock_wcsscc WCSS_TCM_CBCR_CLK>,
+			 <&clock_wcsscc WCSS_AHBM_CBCR_CLK>,
+			 <&clock_wcsscc WCSS_AXIM_CBCR_CLK>,
+			 <&clock_wcsscc WCSS_QDSP6SS_XO_CBCR_CLK>,
+			 <&clock_wcsscc WCSS_QDSP6SS_SLEEP_CBCR_CLK>,
+			 <&clock_wcsscc WCSS_QDSP6SS_GFMMUX_CLK>,
+			 <&clock_wcsscc WCSS_BCR_CBCR_CLK>;
+
+		clock-names = "xo", "gcc_abhs_cbcr", "gcc_axim_cbcr",
+			      "wcss_ahbfabric_cbcr", "wcnss_csr_cbcr",
+			      "wcnss_ahbs_cbcr", "wcnss_tcm_slave_cbcr",
+			      "wcnss_abhm_cbcr", "wcnss_axim_cbcr",
+			      "wcnss_qdsp6ss_xo_cbcr", "wcnss_sleep_cbcr",
+			      "wcnss_core_gfm", "wcss_bcr_cbcr";
+		resets = <&gcc GCC_WDSP_RESTART>,
+			 <&clock_wcsscc Q6SSTOP_QDSP6SS_RESET>,
+			 <&clock_wcsscc Q6SSTOP_QDSP6SS_CORE_RESET>,
+			 <&clock_wcsscc Q6SSTOP_QDSP6SS_BUS_RESET>,
+			 <&clock_wcsscc Q6SSTOP_BCR_RESET>;
+		reset-names = "wcss_reset", "wcss_q6_reset",
+			      "wcss_q6_core_reset", "wcss_q6_bus_reset",
+			      "wcss_q6_bcr_reset";
+
+		memory-region = <&wlan_fw_mem>;
+
+		qcom,smem-states = <&wcss_smp2p_out 0>;
+		qcom,smem-state-names = "stop";
+		qcom,halt-regs = <&tcsr_wlan_q6 0x18000>;
+		glink-edge {
+			interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			qcom,remote-pid = <1>;
+			mboxes = <&apcs_glb 16>;
+
+			label = "wcss";
+			};
+		};
+
diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c
index 129f82404656..3f66bd8fa407 100644
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -4,14 +4,19 @@
  * Copyright (C) 2014 Sony Mobile Communications AB
  * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
  */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
 #include <linux/iopoll.h>
 #include <linux/kernel.h>
 #include <linux/mfd/syscon.h>
 #include <linux/module.h>
+#include <linux/of_address.h>
 #include <linux/of_device.h>
 #include <linux/of_reserved_mem.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
 #include <linux/reset.h>
 #include <linux/soc/qcom/mdt_loader.h>
 #include "qcom_common.h"
@@ -23,6 +28,9 @@
 #define Q6SS_GFMUX_CTL_REG		0x020
 #define Q6SS_PWR_CTL_REG		0x030
 #define Q6SS_MEM_PWR_CTL		0x0B0
+#define Q6SS_STRAP_ACC			0x110
+#define Q6SS_CGC_OVERRIDE		0x034
+#define Q6SS_BCR_REG			0x6000
 
 /* AXI Halt Register Offsets */
 #define AXI_HALTREQ_REG			0x0
@@ -36,6 +44,9 @@
 #define Q6SS_CORE_ARES			BIT(1)
 #define Q6SS_BUS_ARES_ENABLE		BIT(2)
 
+/* Q6SS_BRC_RESET */
+#define Q6SS_BRC_BLK_ARES		BIT(0)
+
 /* Q6SS_GFMUX_CTL */
 #define Q6SS_CLK_ENABLE			BIT(1)
 
@@ -44,6 +55,7 @@
 #define Q6SS_SLP_RET_N			BIT(19)
 #define Q6SS_CLAMP_IO			BIT(20)
 #define QDSS_BHS_ON			BIT(21)
+#define QDSS_Q6_MEMORIES		GENMASK(15, 0)
 
 /* Q6SS parameters */
 #define Q6SS_LDO_BYP		BIT(25)
@@ -70,12 +82,22 @@
 #define TCSR_WCSS_CLK_MASK	0x1F
 #define TCSR_WCSS_CLK_ENABLE	0x14
 
+#define MAX_HALT_REG		3
+enum {
+	WCSS_IPQ8074,
+	WCSS_QCS404,
+};
+
 struct wcss_data {
-	void (*pas_handover)(struct qcom_q6v5 *q6v5);
 	const char *firmware_name;
 	int crash_reason_smem;
 	int version;
-	int pas_id;
+	bool aon_reset_required;
+	const char *ssr_name;
+	const char *sysmon_name;
+	int ssctl_id;
+	const struct rproc_ops *ops;
+	void (*pas_handover)(struct qcom_q6v5 *q6v5);
 };
 
 struct q6v5_wcss {
@@ -83,12 +105,32 @@ struct q6v5_wcss {
 
 	void __iomem *reg_base;
 	void __iomem *rmb_base;
+	void __iomem *q6stop_base;
 
 	struct regmap *halt_map;
 	u32 halt_q6;
 	u32 halt_wcss;
 	u32 halt_nc;
 
+	struct clk *xo;
+	struct clk *ahbfabric_cbcr_clk;
+	struct clk *gcc_abhs_cbcr;
+	struct clk *gcc_axim_cbcr;
+	struct clk *lcc_csr_cbcr;
+	struct clk *ahbs_cbcr;
+	struct clk *tcm_slave_cbcr;
+	struct clk *qdsp6ss_abhm_cbcr;
+	struct clk *qdsp6ss_sleep_cbcr;
+	struct clk *qdsp6ss_axim_cbcr;
+	struct clk *qdsp6ss_xo_cbcr;
+	struct clk *qdsp6ss_core_gfmux;
+	struct clk *wcss_bcr_cbcr;
+	struct regulator *cx_supply;
+
+	struct qcom_rproc_glink glink_subdev;
+	struct qcom_rproc_ssr ssr_subdev;
+	struct qcom_sysmon *sysmon;
+
 	struct reset_control *wcss_aon_reset;
 	struct reset_control *wcss_reset;
 	struct reset_control *wcss_q6_reset;
@@ -99,9 +141,7 @@ struct q6v5_wcss {
 	phys_addr_t mem_reloc;
 	void *mem_region;
 	size_t mem_size;
-
 	int crash_reason_smem;
-	int pas_id;
 	int version;
 };
 
@@ -245,6 +285,197 @@ static int q6v5_wcss_start(struct rproc *rproc)
 	return ret;
 }
 
+static int q6v5_wcss_qcs404_power_on(struct q6v5_wcss *wcss)
+{
+	unsigned long val;
+	int ret, idx;
+
+	/* Toggle the restart */
+	reset_control_assert(wcss->wcss_reset);
+	usleep_range(200, 300);
+	reset_control_deassert(wcss->wcss_reset);
+	usleep_range(200, 300);
+
+	/* Enable GCC_WDSP_Q6SS_AHBS_CBCR clock */
+	ret = clk_prepare_enable(wcss->gcc_abhs_cbcr);
+	if (ret)
+		return ret;
+
+	/* Remove reset to the WCNSS QDSP6SS */
+	val = readl(wcss->q6stop_base + Q6SS_BCR_REG);
+	val &= ~Q6SS_BRC_BLK_ARES;
+	writel(val, wcss->q6stop_base + Q6SS_BCR_REG);
+
+	/* Enable Q6SSTOP_AHBFABRIC_CBCR clock */
+	ret = clk_prepare_enable(wcss->ahbfabric_cbcr_clk);
+	if (ret)
+		goto disable_gcc_abhs_cbcr_clk;
+
+	/* Enable the LCCCSR CBC clock, Q6SSTOP_Q6SSTOP_LCC_CSR_CBCR clock */
+	ret = clk_prepare_enable(wcss->lcc_csr_cbcr);
+	if (ret)
+		goto disable_ahbfabric_cbcr_clk;
+
+	/* Enable the Q6AHBS CBC, Q6SSTOP_Q6SS_AHBS_CBCR clock */
+	ret = clk_prepare_enable(wcss->ahbs_cbcr);
+	if (ret)
+		goto disable_csr_cbcr_clk;
+
+	/* Enable the TCM slave CBC, Q6SSTOP_Q6SS_TCM_SLAVE_CBCR clock */
+	ret = clk_prepare_enable(wcss->tcm_slave_cbcr);
+	if (ret)
+		goto disable_ahbs_cbcr_clk;
+
+	/* Enable the Q6SS AHB master CBC, Q6SSTOP_Q6SS_AHBM_CBCR clock */
+	ret = clk_prepare_enable(wcss->qdsp6ss_abhm_cbcr);
+	if (ret)
+		goto disable_tcm_slave_cbcr_clk;
+
+	/* Enable the Q6SS AXI master CBC, Q6SSTOP_Q6SS_AXIM_CBCR clock */
+	ret = clk_prepare_enable(wcss->qdsp6ss_axim_cbcr);
+	if (ret)
+		goto disable_abhm_cbcr_clk;
+
+	/* Enable the Q6SS XO CBC */
+	ret = clk_prepare_enable(wcss->qdsp6ss_xo_cbcr);
+	if (ret)
+		goto disable_axim_cbcr_clk;
+
+	writel(0, wcss->reg_base + Q6SS_CGC_OVERRIDE);
+
+	/* Enable QDSP6 sleep clock clock */
+	ret = clk_prepare_enable(wcss->qdsp6ss_sleep_cbcr);
+	if (ret)
+		goto disable_xo_cbcr_clk;
+
+	/* Enable the Enable the Q6 AXI clock, GCC_WDSP_Q6SS_AXIM_CBCR*/
+	ret = clk_prepare_enable(wcss->gcc_axim_cbcr);
+	if (ret)
+		goto disable_sleep_cbcr_clk;
+
+	/* Assert resets, stop core */
+	val = readl(wcss->reg_base + Q6SS_RESET_REG);
+	val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
+	writel(val, wcss->reg_base + Q6SS_RESET_REG);
+
+	/* Program the QDSP6SS PWR_CTL register */
+	writel(0x01700000, wcss->reg_base + Q6SS_PWR_CTL_REG);
+
+	writel(0x03700000, wcss->reg_base + Q6SS_PWR_CTL_REG);
+
+	writel(0x03300000, wcss->reg_base + Q6SS_PWR_CTL_REG);
+
+	writel(0x033C0000, wcss->reg_base + Q6SS_PWR_CTL_REG);
+
+	/*
+	 * Enable memories by turning on the QDSP6 memory foot/head switch, one
+	 * bank at a time to avoid in-rush current
+	 */
+	for (idx = 28; idx >= 0; idx--) {
+		writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) |
+			(1 << idx)), wcss->reg_base + Q6SS_MEM_PWR_CTL);
+	}
+
+	writel(0x031C0000, wcss->reg_base + Q6SS_PWR_CTL_REG);
+	writel(0x030C0000, wcss->reg_base + Q6SS_PWR_CTL_REG);
+
+	val = readl(wcss->reg_base + Q6SS_RESET_REG);
+	val &= ~Q6SS_CORE_ARES;
+	writel(val, wcss->reg_base + Q6SS_RESET_REG);
+
+	/* Enable the Q6 core clock at the GFM, Q6SSTOP_QDSP6SS_GFMUX_CTL */
+	ret = clk_prepare_enable(wcss->qdsp6ss_core_gfmux);
+	if (ret)
+		goto disable_gcc_axim_cbcr_clk;
+
+	/* Enable sleep clock branch needed for BCR circuit */
+	ret = clk_prepare_enable(wcss->wcss_bcr_cbcr);
+	if (ret)
+		goto disable_core_gfmux_clk;
+
+	return 0;
+
+disable_core_gfmux_clk:
+	clk_disable_unprepare(wcss->qdsp6ss_core_gfmux);
+disable_gcc_axim_cbcr_clk:
+	clk_disable_unprepare(wcss->gcc_axim_cbcr);
+disable_sleep_cbcr_clk:
+	clk_disable_unprepare(wcss->qdsp6ss_sleep_cbcr);
+disable_xo_cbcr_clk:
+	clk_disable_unprepare(wcss->qdsp6ss_xo_cbcr);
+disable_axim_cbcr_clk:
+	clk_disable_unprepare(wcss->qdsp6ss_axim_cbcr);
+disable_abhm_cbcr_clk:
+	clk_disable_unprepare(wcss->qdsp6ss_abhm_cbcr);
+disable_tcm_slave_cbcr_clk:
+	clk_disable_unprepare(wcss->tcm_slave_cbcr);
+disable_ahbs_cbcr_clk:
+	clk_disable_unprepare(wcss->ahbs_cbcr);
+disable_csr_cbcr_clk:
+	clk_disable_unprepare(wcss->lcc_csr_cbcr);
+disable_ahbfabric_cbcr_clk:
+	clk_disable_unprepare(wcss->ahbfabric_cbcr_clk);
+disable_gcc_abhs_cbcr_clk:
+	clk_disable_unprepare(wcss->gcc_abhs_cbcr);
+
+	return ret;
+}
+
+static inline int q6v5_wcss_qcs404_reset(struct q6v5_wcss *wcss)
+{
+	unsigned long val;
+
+	writel(0x80800000, wcss->reg_base + Q6SS_STRAP_ACC);
+
+	/* Start core execution */
+	val = readl(wcss->reg_base + Q6SS_RESET_REG);
+	val &= ~Q6SS_STOP_CORE;
+	writel(val, wcss->reg_base + Q6SS_RESET_REG);
+
+	return 0;
+}
+
+static int q6v5_qcs404_wcss_start(struct rproc *rproc)
+{
+	struct q6v5_wcss *wcss = rproc->priv;
+	int ret;
+
+	ret = clk_prepare_enable(wcss->xo);
+	if (ret)
+		return ret;
+
+	ret = regulator_enable(wcss->cx_supply);
+	if (ret)
+		goto disable_xo_clk;
+
+	qcom_q6v5_prepare(&wcss->q6v5);
+
+	ret = q6v5_wcss_qcs404_power_on(wcss);
+	if (ret) {
+		dev_err(wcss->dev, "wcss clk_enable failed\n");
+		goto disable_cx_supply;
+	}
+
+	writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB);
+
+	q6v5_wcss_qcs404_reset(wcss);
+
+	ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ);
+	if (ret == -ETIMEDOUT) {
+		dev_err(wcss->dev, "start timed out\n");
+		goto disable_cx_supply;
+	}
+
+	return 0;
+
+disable_cx_supply:
+	regulator_disable(wcss->cx_supply);
+disable_xo_clk:
+	clk_disable_unprepare(wcss->xo);
+
+	return ret;
+}
+
 static void q6v5_wcss_halt_axi_port(struct q6v5_wcss *wcss,
 				    struct regmap *halt_map,
 				    u32 offset)
@@ -279,6 +510,58 @@ static void q6v5_wcss_halt_axi_port(struct q6v5_wcss *wcss,
 	regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
 }
 
+static int q6v5_qcs404_wcss_shutdown(struct q6v5_wcss *wcss)
+{
+	unsigned long val;
+	int ret;
+
+	q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_wcss);
+
+	/* assert clamps to avoid MX current inrush */
+	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
+	val |= (Q6SS_CLAMP_IO | Q6SS_CLAMP_WL | Q6SS_CLAMP_QMC_MEM);
+	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
+
+	/* Disable memories by turning off memory foot/headswitch */
+	writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) &
+		~QDSS_Q6_MEMORIES),
+		wcss->reg_base + Q6SS_MEM_PWR_CTL);
+
+	/* Clear the BHS_ON bit */
+	val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG);
+	val &= ~Q6SS_BHS_ON;
+	writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG);
+
+	clk_disable_unprepare(wcss->ahbfabric_cbcr_clk);
+	clk_disable_unprepare(wcss->lcc_csr_cbcr);
+	clk_disable_unprepare(wcss->tcm_slave_cbcr);
+	clk_disable_unprepare(wcss->qdsp6ss_abhm_cbcr);
+	clk_disable_unprepare(wcss->qdsp6ss_axim_cbcr);
+	clk_disable_unprepare(wcss->qdsp6ss_xo_cbcr);
+	clk_disable_unprepare(wcss->ahbs_cbcr);
+	clk_disable_unprepare(wcss->wcss_bcr_cbcr);
+	clk_disable_unprepare(wcss->qdsp6ss_core_gfmux);
+	clk_disable_unprepare(wcss->gcc_abhs_cbcr);
+
+	ret = reset_control_assert(wcss->wcss_reset);
+	if (ret) {
+		dev_err(wcss->dev, "wcss_reset failed\n");
+		return ret;
+	}
+	usleep_range(200, 300);
+
+	ret = reset_control_deassert(wcss->wcss_reset);
+	if (ret) {
+		dev_err(wcss->dev, "wcss_reset failed\n");
+		return ret;
+	}
+	usleep_range(200, 300);
+
+	clk_disable_unprepare(wcss->gcc_axim_cbcr);
+
+	return 0;
+}
+
 static int q6v5_wcss_powerdown(struct q6v5_wcss *wcss)
 {
 	int ret;
@@ -392,6 +675,14 @@ static int q6v5_q6_powerdown(struct q6v5_wcss *wcss)
 	return 0;
 }
 
+static void q6v5_wcss_handover(struct qcom_q6v5 *q6v5)
+{
+	struct q6v5_wcss *wcss = container_of(q6v5, struct q6v5_wcss, q6v5);
+
+	regulator_disable(wcss->cx_supply);
+	clk_disable_unprepare(wcss->xo);
+}
+
 static int q6v5_wcss_stop(struct rproc *rproc)
 {
 	struct q6v5_wcss *wcss = rproc->priv;
@@ -404,7 +695,11 @@ static int q6v5_wcss_stop(struct rproc *rproc)
 		return ret;
 	}
 
-	ret = q6v5_wcss_powerdown(wcss);
+	if (wcss->version == WCSS_QCS404)
+		ret = q6v5_qcs404_wcss_shutdown(wcss);
+	else
+		ret = q6v5_wcss_powerdown(wcss);
+
 	if (ret)
 		return ret;
 
@@ -447,14 +742,25 @@ static const struct rproc_ops q6v5_wcss_ipq8074_ops = {
 	.get_boot_addr = rproc_elf_get_boot_addr,
 };
 
-static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss)
+static const struct rproc_ops q6v5_wcss_qcs404_ops = {
+	.start = q6v5_qcs404_wcss_start,
+	.stop = q6v5_wcss_stop,
+	.da_to_va = q6v5_wcss_da_to_va,
+	.load = q6v5_wcss_load,
+	.get_boot_addr = rproc_elf_get_boot_addr,
+};
+
+static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss,
+				bool aon_reset_required)
 {
 	struct device *dev = wcss->dev;
 
-	wcss->wcss_aon_reset = devm_reset_control_get(dev, "wcss_aon_reset");
-	if (IS_ERR(wcss->wcss_aon_reset)) {
-		dev_err(wcss->dev, "unable to acquire wcss_aon_reset\n");
-		return PTR_ERR(wcss->wcss_aon_reset);
+	if (aon_reset_required) {
+		wcss->wcss_aon_reset = devm_reset_control_get(dev, "wcss_aon_reset");
+		if (IS_ERR(wcss->wcss_aon_reset)) {
+			dev_err(wcss->dev, "fail to acquire wcss_aon_reset\n");
+			return PTR_ERR(wcss->wcss_aon_reset);
+		}
 	}
 
 	wcss->wcss_reset = devm_reset_control_get(dev, "wcss_reset");
@@ -475,35 +781,60 @@ static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss)
 static int q6v5_wcss_init_mmio(struct q6v5_wcss *wcss,
 			       struct platform_device *pdev)
 {
-	struct of_phandle_args args;
+	unsigned int halt_reg[MAX_HALT_REG] = {0};
+	struct device_node *syscon;
 	struct resource *res;
 	int ret;
 
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
-	wcss->reg_base = devm_ioremap_resource(&pdev->dev, res);
+	wcss->reg_base = devm_ioremap(&pdev->dev, res->start,
+				      resource_size(res));
 	if (IS_ERR(wcss->reg_base))
 		return PTR_ERR(wcss->reg_base);
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
-	wcss->rmb_base = devm_ioremap_resource(&pdev->dev, res);
-	if (IS_ERR(wcss->rmb_base))
-		return PTR_ERR(wcss->rmb_base);
+	if (wcss->version == WCSS_QCS404) {
+		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+						   "q6stop");
+		if (!res) {
+			dev_err(&pdev->dev, "invalid q6stop_base resource\n");
+			return -EINVAL;
+		}
+
+		wcss->q6stop_base = devm_ioremap(&pdev->dev, res->start,
+						 resource_size(res));
+		if (IS_ERR(wcss->q6stop_base))
+			return PTR_ERR(wcss->q6stop_base);
+	} else {
+		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
+		wcss->rmb_base = devm_ioremap_resource(&pdev->dev, res);
+		if (IS_ERR(wcss->rmb_base))
+			return PTR_ERR(wcss->rmb_base);
+	}
 
-	ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
-					       "qcom,halt-regs", 3, 0, &args);
-	if (ret < 0) {
+	syscon = of_parse_phandle(pdev->dev.of_node,
+				  "qcom,halt-regs", 0);
+	if (!syscon) {
 		dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
 		return -EINVAL;
 	}
 
-	wcss->halt_map = syscon_node_to_regmap(args.np);
-	of_node_put(args.np);
+	wcss->halt_map = syscon_node_to_regmap(syscon);
+	of_node_put(syscon);
 	if (IS_ERR(wcss->halt_map))
 		return PTR_ERR(wcss->halt_map);
 
-	wcss->halt_q6 = args.args[0];
-	wcss->halt_wcss = args.args[1];
-	wcss->halt_nc = args.args[2];
+	ret = of_property_read_variable_u32_array(pdev->dev.of_node,
+						  "qcom,halt-regs",
+						  halt_reg, 0,
+						  MAX_HALT_REG);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
+		return -EINVAL;
+	}
+
+	wcss->halt_q6 = halt_reg[0];
+	wcss->halt_wcss = halt_reg[1];
+	wcss->halt_nc = halt_reg[2];
 
 	return 0;
 }
@@ -537,6 +868,132 @@ static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss)
 	return 0;
 }
 
+static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss)
+{
+	int ret;
+
+	wcss->xo = devm_clk_get(wcss->dev, "xo");
+	if (IS_ERR(wcss->xo)) {
+		ret = PTR_ERR(wcss->xo);
+		if (ret != -EPROBE_DEFER)
+			dev_err(wcss->dev, "failed to get xo clock");
+		return ret;
+	}
+
+	wcss->gcc_abhs_cbcr = devm_clk_get(wcss->dev, "gcc_abhs_cbcr");
+	if (IS_ERR(wcss->gcc_abhs_cbcr)) {
+		ret = PTR_ERR(wcss->gcc_abhs_cbcr);
+		if (ret != -EPROBE_DEFER)
+			dev_err(wcss->dev, "failed to get gcc_sway clock\n");
+		return PTR_ERR(wcss->gcc_abhs_cbcr);
+	}
+
+	wcss->gcc_axim_cbcr = devm_clk_get(wcss->dev, "gcc_axim_cbcr");
+	if (IS_ERR(wcss->gcc_axim_cbcr)) {
+		ret = PTR_ERR(wcss->gcc_axim_cbcr);
+		if (ret != -EPROBE_DEFER)
+			dev_err(wcss->dev, "failed to get csr cbcr clk\n");
+		return PTR_ERR(wcss->gcc_axim_cbcr);
+	}
+
+	wcss->ahbfabric_cbcr_clk = devm_clk_get(wcss->dev,
+						"wcss_ahbfabric_cbcr");
+	if (IS_ERR(wcss->ahbfabric_cbcr_clk)) {
+		ret = PTR_ERR(wcss->ahbfabric_cbcr_clk);
+		if (ret != -EPROBE_DEFER)
+			dev_err(wcss->dev, "failed to get gcc_sway clock\n");
+		return PTR_ERR(wcss->ahbfabric_cbcr_clk);
+	}
+
+	wcss->lcc_csr_cbcr = devm_clk_get(wcss->dev, "wcnss_csr_cbcr");
+	if (IS_ERR(wcss->lcc_csr_cbcr)) {
+		ret = PTR_ERR(wcss->lcc_csr_cbcr);
+		if (ret != -EPROBE_DEFER)
+			dev_err(wcss->dev, "failed to get csr cbcr clk\n");
+		return PTR_ERR(wcss->lcc_csr_cbcr);
+	}
+
+	wcss->ahbs_cbcr = devm_clk_get(wcss->dev,
+				       "wcnss_ahbs_cbcr");
+	if (IS_ERR(wcss->ahbs_cbcr)) {
+		ret = PTR_ERR(wcss->ahbs_cbcr);
+		if (ret != -EPROBE_DEFER)
+			dev_err(wcss->dev, "failed to get ahbs_cbcr clk\n");
+		return PTR_ERR(wcss->ahbs_cbcr);
+	}
+
+	wcss->tcm_slave_cbcr = devm_clk_get(wcss->dev,
+					    "wcnss_tcm_slave_cbcr");
+	if (IS_ERR(wcss->tcm_slave_cbcr)) {
+		ret = PTR_ERR(wcss->tcm_slave_cbcr);
+		if (ret != -EPROBE_DEFER)
+			dev_err(wcss->dev, "failed to get tcm cbcr clk\n");
+		return PTR_ERR(wcss->tcm_slave_cbcr);
+	}
+
+	wcss->qdsp6ss_abhm_cbcr = devm_clk_get(wcss->dev, "wcnss_abhm_cbcr");
+	if (IS_ERR(wcss->qdsp6ss_abhm_cbcr)) {
+		ret = PTR_ERR(wcss->qdsp6ss_abhm_cbcr);
+		if (ret != -EPROBE_DEFER)
+			dev_err(wcss->dev, "failed to get abhm cbcr clk\n");
+		return PTR_ERR(wcss->qdsp6ss_abhm_cbcr);
+	}
+
+	wcss->qdsp6ss_axim_cbcr = devm_clk_get(wcss->dev, "wcnss_axim_cbcr");
+	if (IS_ERR(wcss->qdsp6ss_axim_cbcr)) {
+		ret = PTR_ERR(wcss->qdsp6ss_axim_cbcr);
+		if (ret != -EPROBE_DEFER)
+			dev_err(wcss->dev, "failed to get abhm cbcr clk\n");
+		return PTR_ERR(wcss->qdsp6ss_abhm_cbcr);
+	}
+
+	wcss->qdsp6ss_sleep_cbcr = devm_clk_get(wcss->dev, "wcnss_sleep_cbcr");
+	if (IS_ERR(wcss->qdsp6ss_sleep_cbcr)) {
+		ret = PTR_ERR(wcss->qdsp6ss_sleep_cbcr);
+		if (ret != -EPROBE_DEFER)
+			dev_err(wcss->dev, "failed to get qdsp6ss_sleep clk\n");
+		return PTR_ERR(wcss->qdsp6ss_sleep_cbcr);
+	}
+
+	wcss->qdsp6ss_xo_cbcr = devm_clk_get(wcss->dev,
+					     "wcnss_qdsp6ss_xo_cbcr");
+	if (IS_ERR(wcss->qdsp6ss_xo_cbcr)) {
+		ret = PTR_ERR(wcss->qdsp6ss_xo_cbcr);
+		if (ret != -EPROBE_DEFER)
+			dev_err(wcss->dev, "failed to get qdsp6ss_xo_cbcr clk\n");
+		return PTR_ERR(wcss->qdsp6ss_xo_cbcr);
+	}
+
+	wcss->qdsp6ss_core_gfmux = devm_clk_get(wcss->dev, "wcnss_core_gfm");
+	if (IS_ERR(wcss->qdsp6ss_core_gfmux)) {
+		ret = PTR_ERR(wcss->qdsp6ss_core_gfmux);
+		if (ret != -EPROBE_DEFER)
+			dev_err(wcss->dev, "failed to get core gfm clk\n");
+		return PTR_ERR(wcss->qdsp6ss_core_gfmux);
+	}
+
+	wcss->wcss_bcr_cbcr = devm_clk_get(wcss->dev, "wcss_bcr_cbcr");
+	if (IS_ERR(wcss->wcss_bcr_cbcr)) {
+		ret = PTR_ERR(wcss->wcss_bcr_cbcr);
+		if (ret != -EPROBE_DEFER)
+			dev_err(wcss->dev, "failed to get bcr cbcr clk\n");
+		return PTR_ERR(wcss->wcss_bcr_cbcr);
+	}
+
+	return 0;
+}
+
+static int q6v5_wcss_init_regulator(struct q6v5_wcss *wcss)
+{
+	wcss->cx_supply = devm_regulator_get(wcss->dev, "cx");
+	if (IS_ERR(wcss->cx_supply))
+		return PTR_ERR(wcss->cx_supply);
+
+	regulator_set_load(wcss->cx_supply, 100000);
+
+	return 0;
+}
+
 static int q6v5_wcss_probe(struct platform_device *pdev)
 {
 	const struct wcss_data *desc;
@@ -548,7 +1005,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev)
 	if (!desc)
 		return -EINVAL;
 
-	rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_wcss_ipq8074_ops,
+	rproc = rproc_alloc(&pdev->dev, pdev->name, desc->ops,
 			    desc->firmware_name, sizeof(*wcss));
 	if (!rproc) {
 		dev_err(&pdev->dev, "failed to allocate rproc\n");
@@ -557,9 +1014,9 @@ static int q6v5_wcss_probe(struct platform_device *pdev)
 
 	wcss = rproc->priv;
 	wcss->dev = &pdev->dev;
-	wcss->pas_id = desc->pas_id;
 	wcss->version = desc->version;
-	wcss->crash_reason_smem = desc->crash_reason_smem;
+
+	wcss->version = desc->version;
 
 	ret = q6v5_wcss_init_mmio(wcss, pdev);
 	if (ret)
@@ -569,7 +1026,17 @@ static int q6v5_wcss_probe(struct platform_device *pdev)
 	if (ret)
 		goto free_rproc;
 
-	ret = q6v5_wcss_init_reset(wcss);
+	if (wcss->version == WCSS_QCS404) {
+		ret = q6v5_wcss_init_clock(wcss);
+		if (ret)
+			goto free_rproc;
+
+		ret = q6v5_wcss_init_regulator(wcss);
+		if (ret)
+			goto free_rproc;
+	}
+
+	ret = q6v5_wcss_init_reset(wcss, desc->aon_reset_required);
 	if (ret)
 		goto free_rproc;
 
@@ -578,6 +1045,12 @@ static int q6v5_wcss_probe(struct platform_device *pdev)
 	if (ret)
 		goto free_rproc;
 
+	qcom_add_glink_subdev(rproc, &wcss->glink_subdev);
+	qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, desc->ssr_name);
+	wcss->sysmon = qcom_add_sysmon_subdev(rproc,
+					      desc->sysmon_name,
+					      desc->ssctl_id);
+
 	ret = rproc_add(rproc);
 	if (ret)
 		goto free_rproc;
@@ -605,11 +1078,26 @@ static int q6v5_wcss_remove(struct platform_device *pdev)
 static const struct wcss_data wcss_ipq8074_res_init = {
 	.firmware_name = "IPQ8074/q6_fw.mdt",
 	.crash_reason_smem = 421,
+	.aon_reset_required = true,
 	.pas_handover = NULL,
+	.ops = &q6v5_wcss_ipq8074_ops,
+};
+
+static const struct wcss_data wcss_qcs404_res_init = {
+	.crash_reason_smem = 421,
+	.firmware_name = "wcnss.mdt",
+	.version = WCSS_QCS404,
+	.aon_reset_required = false,
+	.ssr_name = "mpss",
+	.sysmon_name = "wcnss",
+	.ssctl_id = 0x12,
+	.ops = &q6v5_wcss_qcs404_ops,
+	.pas_handover = q6v5_wcss_handover,
 };
 
 static const struct of_device_id q6v5_wcss_of_match[] = {
 	{ .compatible = "qcom,ipq8074-wcss-pil", .data = &wcss_ipq8074_res_init },
+	{ .compatible = "qcom,qcs404-wcss-pil", .data = &wcss_qcs404_res_init },
 
 	{ },
 };
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 20+ messages in thread

* [PATCH v3 7/7] remoteproc: qcom: wcss: explicitly request exclusive reset control
  2018-12-15 10:35 [PATCH v3 0/7] Add non PAS wcss Q6 support for QCS404 Govind Singh
                   ` (5 preceding siblings ...)
  2018-12-15 10:35 ` [PATCH v3 6/7] remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404 Govind Singh
@ 2018-12-15 10:35 ` Govind Singh
  6 siblings, 0 replies; 20+ messages in thread
From: Govind Singh @ 2018-12-15 10:35 UTC (permalink / raw)
  To: bjorn.andersson, linux-remoteproc, sboyd
  Cc: linux-clk, sricharan, sibis, linux-arm-msm, andy.gross,
	david.brown, linux-soc, devicetree, Govind Singh

Use request exclusive reset control for wcss reset controls.

Signed-off-by: Govind Singh <govinds@codeaurora.org>
---
 drivers/remoteproc/qcom_q6v5_wcss.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c
index 3f66bd8fa407..b382e5eba26d 100644
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -756,20 +756,20 @@ static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss,
 	struct device *dev = wcss->dev;
 
 	if (aon_reset_required) {
-		wcss->wcss_aon_reset = devm_reset_control_get(dev, "wcss_aon_reset");
+		wcss->wcss_aon_reset = devm_reset_control_get_exclusive(dev, "wcss_aon_reset");
 		if (IS_ERR(wcss->wcss_aon_reset)) {
 			dev_err(wcss->dev, "fail to acquire wcss_aon_reset\n");
 			return PTR_ERR(wcss->wcss_aon_reset);
 		}
 	}
 
-	wcss->wcss_reset = devm_reset_control_get(dev, "wcss_reset");
+	wcss->wcss_reset = devm_reset_control_get_exclusive(dev, "wcss_reset");
 	if (IS_ERR(wcss->wcss_reset)) {
 		dev_err(wcss->dev, "unable to acquire wcss_reset\n");
 		return PTR_ERR(wcss->wcss_reset);
 	}
 
-	wcss->wcss_q6_reset = devm_reset_control_get(dev, "wcss_q6_reset");
+	wcss->wcss_q6_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_reset");
 	if (IS_ERR(wcss->wcss_q6_reset)) {
 		dev_err(wcss->dev, "unable to acquire wcss_q6_reset\n");
 		return PTR_ERR(wcss->wcss_q6_reset);
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v3 4/7] clk: qcom: Add WCSS gcc clock control for QCS404
  2018-12-15 10:35 ` [PATCH v3 4/7] clk: qcom: Add WCSS gcc clock control for QCS404 Govind Singh
@ 2018-12-15 17:56   ` Bjorn Andersson
  2019-02-02 15:32     ` Govind Singh
  2018-12-17 18:53   ` Stephen Boyd
  1 sibling, 1 reply; 20+ messages in thread
From: Bjorn Andersson @ 2018-12-15 17:56 UTC (permalink / raw)
  To: Govind Singh
  Cc: linux-remoteproc, sboyd, linux-clk, sricharan, sibis,
	linux-arm-msm, andy.gross, david.brown, linux-soc, devicetree

On Sat 15 Dec 02:35 PST 2018, Govind Singh wrote:
> diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
[..]
> @@ -2726,6 +2770,11 @@ static int gcc_qcs404_probe(struct platform_device *pdev)
>  			return ret;
>  	}
>  
> +#ifdef CONFIG_QCS_WCSSCC_404

We don't do compile time configuration of things like this, expect all
variants of QCS404 (regardless of security solution) to run off the same
kernel binary.

Instead use the recently introduced "protected-clocks" property.

Regards,
Bjorn

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v3 2/7] clk: qcom: Add WCSS Q6DSP clock controller for QCS404
  2018-12-15 10:35 ` [PATCH v3 2/7] clk: qcom: Add WCSS Q6DSP clock controller for QCS404 Govind Singh
@ 2018-12-17 18:52   ` Stephen Boyd
  2019-02-02 15:45     ` Govind Singh
  0 siblings, 1 reply; 20+ messages in thread
From: Stephen Boyd @ 2018-12-17 18:52 UTC (permalink / raw)
  To: Govind Singh, bjorn.andersson, linux-remoteproc
  Cc: linux-clk, sricharan, sibis, linux-arm-msm, andy.gross,
	david.brown, linux-soc, devicetree, Govind Singh

Quoting Govind Singh (2018-12-15 02:35:52)
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 9fe28b9ceba8..84acc7718691 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -222,6 +222,15 @@ config QCS_GCC_404
>           Say Y if you want to use multimedia devices or peripheral
>           devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc.
>  
> +config QCS_WCSSCC_404
> +       tristate "QCS404 WCSS Clock Controller"
> +       depends on COMMON_CLK_QCOM

This is going away, so you can drop this depends on statement soon.

> +       select QCS_GCC_404
> +       help
> +         Support for the WCSS clock controller on QCS404 devices.
> +         Say Y if you want to use the WCSS branch clocks of the WCSS clock
> +         controller to reset the WCSS subsystem.
> +
>  config SDM_GCC_845
>         tristate "SDM845 Global Clock Controller"
>         select QCOM_GDSC
> diff --git a/drivers/clk/qcom/wcsscc-qcs404.c b/drivers/clk/qcom/wcsscc-qcs404.c
> new file mode 100644
> index 000000000000..bd694ef1b6ac
> --- /dev/null
> +++ b/drivers/clk/qcom/wcsscc-qcs404.c
> @@ -0,0 +1,297 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/bitops.h>
> +#include <linux/err.h>
> +#include <linux/platform_device.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>

Is this used?

> +#include <linux/clk.h>

Is this used?

> +#include <linux/clk-provider.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>

Is this used?

> +
> +#include <dt-bindings/clock/qcom,wcss-qcs404.h>
> +#include <linux/reset-controller.h>

Cool, but where are the resets? Also, please put <linux/*.h> before any
dt-bindings includes.

> +
> +#include "clk-regmap.h"
> +#include "clk-branch.h"
> +#include "common.h"
> +#include "reset.h"
> +
> +/* Q6SSTOP clocks. These clocks are voted
> + * during by remoteproc client when loaded from

This sentence doesn't parse easily. "during by"?

> + * user space, soc hang is seen when CCF turns

SoC? Or just system hang?

> + * off unused clocks. As a temp solution use

Temporary?

> + * CLK_IGNORE_UNUSED flags which prevent these
> + * clocks from being gated during bootup.

Ok.. but userspace is after CLK_IGNORE_UNUSED would process these clks?
So we're keeping them on from the bootloader why? Something is using
these clks during that operation but after that point they need to be
turned off?

> + */
> +
> +static int wcss_clocks_qcs404_probe(struct platform_device *pdev, int index,
> +                                   const struct qcom_cc_desc *desc)
> +{
> +       struct regmap *regmap;
> +       struct resource *res;
> +       void __iomem *base;
> +
> +       res = platform_get_resource(pdev, IORESOURCE_MEM, index);
> +       base = devm_ioremap_resource(&pdev->dev, res);
> +       if (IS_ERR(base))
> +               return -ENOMEM;
> +
> +       regmap = devm_regmap_init_mmio(&pdev->dev, base, desc->config);
> +       if (IS_ERR(regmap))
> +               return PTR_ERR(regmap);
> +
> +       return qcom_cc_really_probe(pdev, desc, regmap);
> +}

You're the second user of this "probe on reg region" logic. Please
extract it out of the lpasscc driver and put it into common.c so it can
be reused by the two drivers.

> +
> +static int wcss_cc_qcs404_probe(struct platform_device *pdev)
> +{
> +       const struct qcom_cc_desc *desc;
> +       int ret;
> +
> +       wcss_regmap_config.name = "wcss_q6sstop";
> +       desc = &wcss_q6sstop_qcs404_desc;
> +
> +       ret = wcss_clocks_qcs404_probe(pdev, 0, desc);
> +       if (ret)
> +               return ret;
> +
> +       wcss_regmap_config.name = "wcnss_tcsr";
> +       desc = &wcnss_tcsr_qcs404_desc;
> +
> +       ret = wcss_clocks_qcs404_probe(pdev, 1, desc);
> +       if (ret)
> +               return ret;
> +
> +       wcss_regmap_config.name = "wcss_qdsp6ss";
> +       desc = &wcnss_qdsp6ss_qcs404_desc;
> +
> +       return wcss_clocks_qcs404_probe(pdev, 2, desc);
> +}
> +
> +static struct platform_driver wcss_cc_qcs404_driver = {
> +       .probe          = wcss_cc_qcs404_probe,
> +       .driver         = {
> +               .name   = "qcs404-wcsscc",
> +               .of_match_table = wcss_cc_qcs404_match_table,
> +       },
> +};
> +
> +static int __init wcss_cc_qcs404_init(void)
> +{
> +       return platform_driver_register(&wcss_cc_qcs404_driver);
> +}
> +subsys_initcall(wcss_cc_qcs404_init);

Where is the driver removal exit function?

> +
> +MODULE_LICENSE("GPL v2");

MODULE_DESCRIPTION?


^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v3 4/7] clk: qcom: Add WCSS gcc clock control for QCS404
  2018-12-15 10:35 ` [PATCH v3 4/7] clk: qcom: Add WCSS gcc clock control for QCS404 Govind Singh
  2018-12-15 17:56   ` Bjorn Andersson
@ 2018-12-17 18:53   ` Stephen Boyd
  1 sibling, 0 replies; 20+ messages in thread
From: Stephen Boyd @ 2018-12-17 18:53 UTC (permalink / raw)
  To: Govind Singh, bjorn.andersson, linux-remoteproc
  Cc: linux-clk, sricharan, sibis, linux-arm-msm, andy.gross,
	david.brown, linux-soc, devicetree, Govind Singh

Quoting Govind Singh (2018-12-15 02:35:54)
> @@ -2726,6 +2770,11 @@ static int gcc_qcs404_probe(struct platform_device *pdev)
>                         return ret;
>         }
>  
> +#ifdef CONFIG_QCS_WCSSCC_404
> +               gcc_qcs404_clocks[GCC_WCSS_Q6_AHB_CBCR_CLK] = &gcc_wdsp_q6ss_ahbs_clk.clkr;
> +               gcc_qcs404_clocks[GCC_WCSS_Q6_AXIM_CBCR_CLK] = &gcc_wdsp_q6ss_axim_clk.clkr;

What is going on with the tabs here? Why is it under an ifdef?

> +#endif
> +
>         return qcom_cc_really_probe(pdev, &gcc_qcs404_desc, regmap);
>  }
>  
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v3 5/7] remoteproc: qcom: wcss: populate hardcoded param using driver data
  2018-12-15 10:35 ` [PATCH v3 5/7] remoteproc: qcom: wcss: populate hardcoded param using driver data Govind Singh
@ 2018-12-17 18:55   ` Stephen Boyd
  0 siblings, 0 replies; 20+ messages in thread
From: Stephen Boyd @ 2018-12-17 18:55 UTC (permalink / raw)
  To: Govind Singh, bjorn.andersson, linux-remoteproc
  Cc: linux-clk, sricharan, sibis, linux-arm-msm, andy.gross,
	david.brown, linux-soc, devicetree, Govind Singh

Quoting Govind Singh (2018-12-15 02:35:55)
> diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c
> index f93e1e4a1cc0..129f82404656 100644
> --- a/drivers/remoteproc/qcom_q6v5_wcss.c
> +++ b/drivers/remoteproc/qcom_q6v5_wcss.c
> @@ -16,7 +17,6 @@
>  #include "qcom_common.h"
>  #include "qcom_q6v5.h"
>  
> -#define WCSS_CRASH_REASON              421
>  
>  /* Q6SS Register Offsets */
>  #define Q6SS_RESET_REG         0x014
> @@ -70,6 +70,14 @@
>  #define TCSR_WCSS_CLK_MASK     0x1F
>  #define TCSR_WCSS_CLK_ENABLE   0x14
>  
> +struct wcss_data {
> +       void (*pas_handover)(struct qcom_q6v5 *q6v5);
> +       const char *firmware_name;
> +       int crash_reason_smem;
> +       int version;

version can be negative?

> +       int pas_id;

And the pas_id can be negative too?

> +};
> +
>  struct q6v5_wcss {
>         struct device *dev;
>  
> @@ -553,7 +573,8 @@ static int q6v5_wcss_probe(struct platform_device *pdev)
>         if (ret)
>                 goto free_rproc;
>  
> -       ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, WCSS_CRASH_REASON, NULL);
> +       ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, desc->crash_reason_smem,
> +                            desc->pas_handover);
>         if (ret)
>                 goto free_rproc;
>  
> @@ -581,8 +602,15 @@ static int q6v5_wcss_remove(struct platform_device *pdev)
>         return 0;
>  }
>  
> +static const struct wcss_data wcss_ipq8074_res_init = {
> +       .firmware_name = "IPQ8074/q6_fw.mdt",
> +       .crash_reason_smem = 421,

Why destroy the #define and inline it here? Keep the define around and
use it here instead?

> +       .pas_handover = NULL,

This surely isn't needed to be assigned to NULL.


^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v3 6/7] remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404
  2018-12-15 10:35 ` [PATCH v3 6/7] remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404 Govind Singh
@ 2018-12-17 19:00   ` Stephen Boyd
  2018-12-17 20:48   ` Rob Herring
  1 sibling, 0 replies; 20+ messages in thread
From: Stephen Boyd @ 2018-12-17 19:00 UTC (permalink / raw)
  To: Govind Singh, bjorn.andersson, linux-remoteproc
  Cc: linux-clk, sricharan, sibis, linux-arm-msm, andy.gross,
	david.brown, linux-soc, devicetree, Govind Singh

Quoting Govind Singh (2018-12-15 02:35:56)
> diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c
> index 129f82404656..3f66bd8fa407 100644
> --- a/drivers/remoteproc/qcom_q6v5_wcss.c
> +++ b/drivers/remoteproc/qcom_q6v5_wcss.c
> @@ -83,12 +105,32 @@ struct q6v5_wcss {
>  
>         void __iomem *reg_base;
>         void __iomem *rmb_base;
> +       void __iomem *q6stop_base;
>  
>         struct regmap *halt_map;
>         u32 halt_q6;
>         u32 halt_wcss;
>         u32 halt_nc;
>  
> +       struct clk *xo;
> +       struct clk *ahbfabric_cbcr_clk;
> +       struct clk *gcc_abhs_cbcr;
> +       struct clk *gcc_axim_cbcr;
> +       struct clk *lcc_csr_cbcr;
> +       struct clk *ahbs_cbcr;
> +       struct clk *tcm_slave_cbcr;
> +       struct clk *qdsp6ss_abhm_cbcr;
> +       struct clk *qdsp6ss_sleep_cbcr;
> +       struct clk *qdsp6ss_axim_cbcr;
> +       struct clk *qdsp6ss_xo_cbcr;
> +       struct clk *qdsp6ss_core_gfmux;
> +       struct clk *wcss_bcr_cbcr;

You should look into clk_bulk_prepare_enable() or just
clk_bulk_get_all() to greatly simplify this patch.

> +       struct regulator *cx_supply;
> +
> +       struct qcom_rproc_glink glink_subdev;
> +       struct qcom_rproc_ssr ssr_subdev;
> +       struct qcom_sysmon *sysmon;
> +
>         struct reset_control *wcss_aon_reset;
>         struct reset_control *wcss_reset;
>         struct reset_control *wcss_q6_reset;
> @@ -99,9 +141,7 @@ struct q6v5_wcss {
>         phys_addr_t mem_reloc;
>         void *mem_region;
>         size_t mem_size;
> -
>         int crash_reason_smem;
> -       int pas_id;
>         int version;
>  };
>  
> @@ -245,6 +285,197 @@ static int q6v5_wcss_start(struct rproc *rproc)
>         return ret;
>  }
>  
[...]
> +
> +       /* Assert resets, stop core */
> +       val = readl(wcss->reg_base + Q6SS_RESET_REG);
> +       val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
> +       writel(val, wcss->reg_base + Q6SS_RESET_REG);
> +
> +       /* Program the QDSP6SS PWR_CTL register */
> +       writel(0x01700000, wcss->reg_base + Q6SS_PWR_CTL_REG);
> +
> +       writel(0x03700000, wcss->reg_base + Q6SS_PWR_CTL_REG);
> +
> +       writel(0x03300000, wcss->reg_base + Q6SS_PWR_CTL_REG);
> +
> +       writel(0x033C0000, wcss->reg_base + Q6SS_PWR_CTL_REG);
> +
> +       /*
> +        * Enable memories by turning on the QDSP6 memory foot/head switch, one
> +        * bank at a time to avoid in-rush current
> +        */
> +       for (idx = 28; idx >= 0; idx--) {
> +               writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) |
> +                       (1 << idx)), wcss->reg_base + Q6SS_MEM_PWR_CTL);
> +       }

Smells like it should be in a power domain driver, but I guess it gets a
little hard because clks have to be powered on first and in some order.

> +
> +       writel(0x031C0000, wcss->reg_base + Q6SS_PWR_CTL_REG);
> +       writel(0x030C0000, wcss->reg_base + Q6SS_PWR_CTL_REG);
> +
> +       val = readl(wcss->reg_base + Q6SS_RESET_REG);
> +       val &= ~Q6SS_CORE_ARES;
> +       writel(val, wcss->reg_base + Q6SS_RESET_REG);
> +
> +       /* Enable the Q6 core clock at the GFM, Q6SSTOP_QDSP6SS_GFMUX_CTL */
> +       ret = clk_prepare_enable(wcss->qdsp6ss_core_gfmux);
> +       if (ret)
> +               goto disable_gcc_axim_cbcr_clk;
> +
> +       /* Enable sleep clock branch needed for BCR circuit */
> +       ret = clk_prepare_enable(wcss->wcss_bcr_cbcr);
> +       if (ret)
> +               goto disable_core_gfmux_clk;
> +
> +       return 0;
> @@ -475,35 +781,60 @@ static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss)
>  static int q6v5_wcss_init_mmio(struct q6v5_wcss *wcss,
>                                struct platform_device *pdev)
>  {
> -       struct of_phandle_args args;
> +       unsigned int halt_reg[MAX_HALT_REG] = {0};
> +       struct device_node *syscon;
>         struct resource *res;
>         int ret;
>  
>         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
> -       wcss->reg_base = devm_ioremap_resource(&pdev->dev, res);
> +       wcss->reg_base = devm_ioremap(&pdev->dev, res->start,
> +                                     resource_size(res));
>         if (IS_ERR(wcss->reg_base))
>                 return PTR_ERR(wcss->reg_base);
>  
> -       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
> -       wcss->rmb_base = devm_ioremap_resource(&pdev->dev, res);
> -       if (IS_ERR(wcss->rmb_base))
> -               return PTR_ERR(wcss->rmb_base);
> +       if (wcss->version == WCSS_QCS404) {
> +               res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> +                                                  "q6stop");
> +               if (!res) {
> +                       dev_err(&pdev->dev, "invalid q6stop_base resource\n");
> +                       return -EINVAL;
> +               }
> +
> +               wcss->q6stop_base = devm_ioremap(&pdev->dev, res->start,
> +                                                resource_size(res));

Why can't devm_ioremap_resource() be used here?

> +               if (IS_ERR(wcss->q6stop_base))
> +                       return PTR_ERR(wcss->q6stop_base);
> +       } else {
> +               res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
> +               wcss->rmb_base = devm_ioremap_resource(&pdev->dev, res);
> +               if (IS_ERR(wcss->rmb_base))
> +                       return PTR_ERR(wcss->rmb_base);
> +       }
>  
> -       ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
> -                                              "qcom,halt-regs", 3, 0, &args);
> -       if (ret < 0) {
> +       syscon = of_parse_phandle(pdev->dev.of_node,
> +                                 "qcom,halt-regs", 0);
> +       if (!syscon) {
>                 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
>                 return -EINVAL;
>         }

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v3 1/7] dt-bindings: clock: qcom: Introduce QCOM WCSS Q6DSP clock bindings
  2018-12-15 10:35 ` [PATCH v3 1/7] dt-bindings: clock: qcom: Introduce QCOM WCSS Q6DSP clock bindings Govind Singh
@ 2018-12-17 19:33   ` Stephen Boyd
  2019-02-02 15:35     ` Govind Singh
  0 siblings, 1 reply; 20+ messages in thread
From: Stephen Boyd @ 2018-12-17 19:33 UTC (permalink / raw)
  To: Govind Singh, bjorn.andersson, linux-remoteproc
  Cc: linux-clk, sricharan, sibis, linux-arm-msm, andy.gross,
	david.brown, linux-soc, devicetree, Govind Singh

Quoting Govind Singh (2018-12-15 02:35:51)
> Add device tree bindings for WiFi QDSP subsystem clock controls
> found in OCS405 soc.
> 
> Signed-off-by: Govind Singh <govinds@codeaurora.org>
> Reviewed-by: Rob Herring <robh@kernel.org>

It was?

> diff --git a/Documentation/devicetree/bindings/clock/qcom,wcsscc.txt b/Documentation/devicetree/bindings/clock/qcom,wcsscc.txt
> new file mode 100644
> index 000000000000..2b19ef0b5689
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,wcsscc.txt
> @@ -0,0 +1,26 @@
> +Qualcomm WCSS Clock Controller Binding
> +-----------------------------------------------
> +
> +Required properties :
> +- compatible           : shall contain "qcom,qcs404-wcsscc"
> +- #clock-cells         : from common clock binding, shall contain 1.

Drop the full-stop please.

> +- reg                  : shall contain base register address and size,
> +                         in the order
> +                       Index-0 maps to WCSS_Q6SSTOP clocks register region
> +                       Index-1 maps to WCSS_TCSR register region
> +                       Index-2 maps to WCSS_QDSP6SS register region
> +

Index 0, Index 1, Index 2? Not sure why there's a hyphen there.

> +Optional properties :
> +- reg-names    : register names of WCSS domain
> +                "wcss_q6sstop", "wcnss_tcsr", "wcss_qdsp6ss".
> +
> +Example:
> +The below node has to be defined in the cases where the WCSS peripheral loader
> +would bring the subsystem out of reset.
> +
> +       clock_wcsscc: qcom,wcsscc@7000000 {

clock-controller@7000000

> +               compatible = "qcom,qcs404-wcsscc";
> +               reg = <0x07500000 0x4e000>, <0x07550000 0x8012>, <0x07400000 0x104>;

And then that unit address doesn't match the first offset so that needs
fixing too.

> +               reg-names = "wcss_q6sstop", "wcnss_tcsr", "wcss_qdsp6ss";
> +               #clock-cells = <1>;
> +       };

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v3 3/7] dt-bindings: clock: qcom: Add QCOM WCSS GCC clock bindings
  2018-12-15 10:35 ` [PATCH v3 3/7] dt-bindings: clock: qcom: Add QCOM WCSS GCC clock bindings Govind Singh
@ 2018-12-17 19:34   ` Stephen Boyd
  2019-02-02 15:33     ` Govind Singh
  0 siblings, 1 reply; 20+ messages in thread
From: Stephen Boyd @ 2018-12-17 19:34 UTC (permalink / raw)
  To: Govind Singh, bjorn.andersson, linux-remoteproc
  Cc: linux-clk, sricharan, sibis, linux-arm-msm, andy.gross,
	david.brown, linux-soc, devicetree, Govind Singh

Quoting Govind Singh (2018-12-15 02:35:53)
> Add device tree bindings for WiFi QDSP gcc clock controls found in
> QCS404 soc.
> 
> Signed-off-by: Govind Singh <govinds@codeaurora.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
>  include/dt-bindings/clock/qcom,gcc-qcs404.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h
> index 00ab0d77b38a..8f800adda225 100644
> --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h
> +++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
> @@ -146,6 +146,8 @@
>  #define GCC_MDP_TBU_CLK                                        138
>  #define GCC_QDSS_DAP_CLK                               139
>  #define GCC_DCC_XO_CLK                                 140
> +#define GCC_WCSS_Q6_AHB_CBCR_CLK                       141
> +#define GCC_WCSS_Q6_AXIM_CBCR_CLK                      142

Does the register really call it FOO_CBCR_CLK? I'd prefer we drop the
CBCR part unless you really want it to keep it.

>  
>  #define GCC_GENI_IR_BCR                                        0
>  #define GCC_USB_HS_BCR                                 1

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v3 6/7] remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404
  2018-12-15 10:35 ` [PATCH v3 6/7] remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404 Govind Singh
  2018-12-17 19:00   ` Stephen Boyd
@ 2018-12-17 20:48   ` Rob Herring
  1 sibling, 0 replies; 20+ messages in thread
From: Rob Herring @ 2018-12-17 20:48 UTC (permalink / raw)
  To: Govind Singh
  Cc: bjorn.andersson, linux-remoteproc, sboyd, linux-clk, sricharan,
	sibis, linux-arm-msm, andy.gross, david.brown, linux-soc,
	devicetree

On Sat, Dec 15, 2018 at 04:05:56PM +0530, Govind Singh wrote:
> Add non PAS WCSS remoteproc driver support for QCS404 SOC.
> Add WCSS q6 bootup and shutdown sequence handled from
> Application Processor SubSystem(APSS).
> 
> Signed-off-by: Govind Singh <govinds@codeaurora.org>
> ---
>  .../bindings/remoteproc/qcom,q6v5.txt         |  61 ++

Please add acks/reviewed-bys when posting new versions.

In the future, please split bindings to a separate patch.

>  drivers/remoteproc/qcom_q6v5_wcss.c           | 544 +++++++++++++++++-
>  2 files changed, 577 insertions(+), 28 deletions(-)

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v3 4/7] clk: qcom: Add WCSS gcc clock control for QCS404
  2018-12-15 17:56   ` Bjorn Andersson
@ 2019-02-02 15:32     ` Govind Singh
  0 siblings, 0 replies; 20+ messages in thread
From: Govind Singh @ 2019-02-02 15:32 UTC (permalink / raw)
  To: Bjorn Andersson
  Cc: linux-remoteproc, sboyd, linux-clk, sricharan, sibis,
	linux-arm-msm, andy.gross, david.brown, linux-soc, devicetree

On 2018-12-15 23:26, Bjorn Andersson wrote:
> On Sat 15 Dec 02:35 PST 2018, Govind Singh wrote:
>> diff --git a/drivers/clk/qcom/gcc-qcs404.c 
>> b/drivers/clk/qcom/gcc-qcs404.c
> [..]
>> @@ -2726,6 +2770,11 @@ static int gcc_qcs404_probe(struct 
>> platform_device *pdev)
>>  			return ret;
>>  	}
>> 
>> +#ifdef CONFIG_QCS_WCSSCC_404
> 
> We don't do compile time configuration of things like this, expect all
> variants of QCS404 (regardless of security solution) to run off the 
> same
> kernel binary.
> 
> Instead use the recently introduced "protected-clocks" property.
> 

Fixed in v4. Seems LPASS is no more using "protected-clocks", i used 
"unprotected-clocks" property to avoid inverted logic.

> Regards,
> Bjorn

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v3 3/7] dt-bindings: clock: qcom: Add QCOM WCSS GCC clock bindings
  2018-12-17 19:34   ` Stephen Boyd
@ 2019-02-02 15:33     ` Govind Singh
  0 siblings, 0 replies; 20+ messages in thread
From: Govind Singh @ 2019-02-02 15:33 UTC (permalink / raw)
  To: Stephen Boyd
  Cc: bjorn.andersson, linux-remoteproc, linux-clk, sricharan, sibis,
	linux-arm-msm, andy.gross, david.brown, linux-soc, devicetree

On 2018-12-18 01:04, Stephen Boyd wrote:
> Quoting Govind Singh (2018-12-15 02:35:53)
>> Add device tree bindings for WiFi QDSP gcc clock controls found in
>> QCS404 soc.
>> 
>> Signed-off-by: Govind Singh <govinds@codeaurora.org>
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> ---
>>  include/dt-bindings/clock/qcom,gcc-qcs404.h | 3 +++
>>  1 file changed, 3 insertions(+)
>> 
>> diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h 
>> b/include/dt-bindings/clock/qcom,gcc-qcs404.h
>> index 00ab0d77b38a..8f800adda225 100644
>> --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h
>> +++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
>> @@ -146,6 +146,8 @@
>>  #define GCC_MDP_TBU_CLK                                        138
>>  #define GCC_QDSS_DAP_CLK                               139
>>  #define GCC_DCC_XO_CLK                                 140
>> +#define GCC_WCSS_Q6_AHB_CBCR_CLK                       141
>> +#define GCC_WCSS_Q6_AXIM_CBCR_CLK                      142
> 
> Does the register really call it FOO_CBCR_CLK? I'd prefer we drop the
> CBCR part unless you really want it to keep it.
> 

Thanks, removed CBCR in v4.

>> 
>>  #define GCC_GENI_IR_BCR                                        0
>>  #define GCC_USB_HS_BCR                                 1

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v3 1/7] dt-bindings: clock: qcom: Introduce QCOM WCSS Q6DSP clock bindings
  2018-12-17 19:33   ` Stephen Boyd
@ 2019-02-02 15:35     ` Govind Singh
  0 siblings, 0 replies; 20+ messages in thread
From: Govind Singh @ 2019-02-02 15:35 UTC (permalink / raw)
  To: Stephen Boyd
  Cc: bjorn.andersson, linux-remoteproc, linux-clk, sricharan, sibis,
	linux-arm-msm, andy.gross, david.brown, linux-soc, devicetree

On 2018-12-18 01:03, Stephen Boyd wrote:
> Quoting Govind Singh (2018-12-15 02:35:51)
>> Add device tree bindings for WiFi QDSP subsystem clock controls
>> found in OCS405 soc.


> 
>> +- reg                  : shall contain base register address and 
>> size,
>> +                         in the order
>> +                       Index-0 maps to WCSS_Q6SSTOP clocks register 
>> region
>> +                       Index-1 maps to WCSS_TCSR register region
>> +                       Index-2 maps to WCSS_QDSP6SS register region
>> +
> 
> Index 0, Index 1, Index 2? Not sure why there's a hyphen there.
> 

Fixed in v4.

>> +Optional properties :
>> +- reg-names    : register names of WCSS domain
>> +                "wcss_q6sstop", "wcnss_tcsr", "wcss_qdsp6ss".
>> +
>> +Example:
>> +The below node has to be defined in the cases where the WCSS 
>> peripheral loader
>> +would bring the subsystem out of reset.
>> +
>> +       clock_wcsscc: qcom,wcsscc@7000000 {
> 
> clock-controller@7000000
> 
>> +               compatible = "qcom,qcs404-wcsscc";
>> +               reg = <0x07500000 0x4e000>, <0x07550000 0x8012>, 
>> <0x07400000 0x104>;
> 
> And then that unit address doesn't match the first offset so that needs
> fixing too.
> 

Fixed in V4.

>> +               reg-names = "wcss_q6sstop", "wcnss_tcsr", 
>> "wcss_qdsp6ss";
>> +               #clock-cells = <1>;
>> +       };

BR,
Govind

^ permalink raw reply	[flat|nested] 20+ messages in thread

* Re: [PATCH v3 2/7] clk: qcom: Add WCSS Q6DSP clock controller for QCS404
  2018-12-17 18:52   ` Stephen Boyd
@ 2019-02-02 15:45     ` Govind Singh
  0 siblings, 0 replies; 20+ messages in thread
From: Govind Singh @ 2019-02-02 15:45 UTC (permalink / raw)
  To: Stephen Boyd
  Cc: bjorn.andersson, linux-remoteproc, linux-clk, sricharan, sibis,
	linux-arm-msm, andy.gross, david.brown, linux-soc, devicetree


On 2018-12-18 00:22, Stephen Boyd wrote:
> Quoting Govind Singh (2018-12-15 02:35:52)
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index 9fe28b9ceba8..84acc7718691 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -222,6 +222,15 @@ config QCS_GCC_404
>>           Say Y if you want to use multimedia devices or peripheral
>>           devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc.
>> 
>> +config QCS_WCSSCC_404
>> +       tristate "QCS404 WCSS Clock Controller"
>> +       depends on COMMON_CLK_QCOM
> 
> This is going away, so you can drop this depends on statement soon.
> 

Removed in v4.

>> +       select QCS_GCC_404
>> +       help
>> +         Support for the WCSS clock controller on QCS404 devices.
>> +         Say Y if you want to use the WCSS branch clocks of the WCSS 
>> clock
>> +         controller to reset the WCSS subsystem.
>> +
>>  config SDM_GCC_845
>>         tristate "SDM845 Global Clock Controller"
>>         select QCOM_GDSC
>> diff --git a/drivers/clk/qcom/wcsscc-qcs404.c 
>> b/drivers/clk/qcom/wcsscc-qcs404.c
>> new file mode 100644
>> index 000000000000..bd694ef1b6ac
>> --- /dev/null
>> +++ b/drivers/clk/qcom/wcsscc-qcs404.c
>> @@ -0,0 +1,297 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include <linux/bitops.h>
>> +#include <linux/err.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/module.h>
>> +#include <linux/of_address.h>
> 
> Is this used?
> 
>> +#include <linux/clk.h>
> 
> Is this used?
> 

Removed unnecessary includes and cleanup suggested by you in v4.

> 
>> + * CLK_IGNORE_UNUSED flags which prevent these
>> + * clocks from being gated during bootup.
> 
> Ok.. but userspace is after CLK_IGNORE_UNUSED would process these clks?
> So we're keeping them on from the bootloader why? Something is using
> these clks during that operation but after that point they need to be
> turned off?
> 

Yes remote proc will process this clock during rproc start. I discussed 
this issue with Bjorn.
I will seek his help.
Need to root cause why these clocks are voted from bootloader.

>> + */
>> +
>> +static int wcss_clocks_qcs404_probe(struct platform_device *pdev, int 
>> index,
>> +                                   const struct qcom_cc_desc *desc)
>> +{
>> +       struct regmap *regmap;
>> +       struct resource *res;
>> +       void __iomem *base;
>> +
>> +       res = platform_get_resource(pdev, IORESOURCE_MEM, index);
>> +       base = devm_ioremap_resource(&pdev->dev, res);
>> +       if (IS_ERR(base))
>> +               return -ENOMEM;
>> +
>> +       regmap = devm_regmap_init_mmio(&pdev->dev, base, 
>> desc->config);
>> +       if (IS_ERR(regmap))
>> +               return PTR_ERR(regmap);
>> +
>> +       return qcom_cc_really_probe(pdev, desc, regmap);
>> +}
> 
> You're the second user of this "probe on reg region" logic. Please
> extract it out of the lpasscc driver and put it into common.c so it can
> be reused by the two drivers.
> 

I have addressed in v4.

>> +
>> +static int wcss_cc_qcs404_probe(struct platform_device *pdev)
>> +{
>> +       const struct qcom_cc_desc *desc;
>> +       int ret;
>> +
>> +       wcss_regmap_config.name = "wcss_q6sstop";
>> +       desc = &wcss_q6sstop_qcs404_desc;
>> +
>> +       ret = wcss_clocks_qcs404_probe(pdev, 0, desc);
>> +       if (ret)
>> +               return ret;
>> +
>> +       wcss_regmap_config.name = "wcnss_tcsr";
>> +       desc = &wcnss_tcsr_qcs404_desc;
>> +
>> +       ret = wcss_clocks_qcs404_probe(pdev, 1, desc);
>> +       if (ret)
>> +               return ret;
>> +
>> +       wcss_regmap_config.name = "wcss_qdsp6ss";
>> +       desc = &wcnss_qdsp6ss_qcs404_desc;
>> +
>> +       return wcss_clocks_qcs404_probe(pdev, 2, desc);
>> +}
>> +
>> +static struct platform_driver wcss_cc_qcs404_driver = {
>> +       .probe          = wcss_cc_qcs404_probe,
>> +       .driver         = {
>> +               .name   = "qcs404-wcsscc",
>> +               .of_match_table = wcss_cc_qcs404_match_table,
>> +       },
>> +};
>> +
>> +static int __init wcss_cc_qcs404_init(void)
>> +{
>> +       return platform_driver_register(&wcss_cc_qcs404_driver);
>> +}
>> +subsys_initcall(wcss_cc_qcs404_init);
> 
> Where is the driver removal exit function?
> 

My bad, added in v4.

>> +
>> +MODULE_LICENSE("GPL v2");
> 
> MODULE_DESCRIPTION?

BR,
Govind

^ permalink raw reply	[flat|nested] 20+ messages in thread

end of thread, back to index

Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-12-15 10:35 [PATCH v3 0/7] Add non PAS wcss Q6 support for QCS404 Govind Singh
2018-12-15 10:35 ` [PATCH v3 1/7] dt-bindings: clock: qcom: Introduce QCOM WCSS Q6DSP clock bindings Govind Singh
2018-12-17 19:33   ` Stephen Boyd
2019-02-02 15:35     ` Govind Singh
2018-12-15 10:35 ` [PATCH v3 2/7] clk: qcom: Add WCSS Q6DSP clock controller for QCS404 Govind Singh
2018-12-17 18:52   ` Stephen Boyd
2019-02-02 15:45     ` Govind Singh
2018-12-15 10:35 ` [PATCH v3 3/7] dt-bindings: clock: qcom: Add QCOM WCSS GCC clock bindings Govind Singh
2018-12-17 19:34   ` Stephen Boyd
2019-02-02 15:33     ` Govind Singh
2018-12-15 10:35 ` [PATCH v3 4/7] clk: qcom: Add WCSS gcc clock control for QCS404 Govind Singh
2018-12-15 17:56   ` Bjorn Andersson
2019-02-02 15:32     ` Govind Singh
2018-12-17 18:53   ` Stephen Boyd
2018-12-15 10:35 ` [PATCH v3 5/7] remoteproc: qcom: wcss: populate hardcoded param using driver data Govind Singh
2018-12-17 18:55   ` Stephen Boyd
2018-12-15 10:35 ` [PATCH v3 6/7] remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404 Govind Singh
2018-12-17 19:00   ` Stephen Boyd
2018-12-17 20:48   ` Rob Herring
2018-12-15 10:35 ` [PATCH v3 7/7] remoteproc: qcom: wcss: explicitly request exclusive reset control Govind Singh

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