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From: Maxime Ripard <maxime.ripard@bootlin.com>
To: Icenowy Zheng <icenowy@aosc.io>
Cc: Rob Herring <robh+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
	Linus Walleij <linus.walleij@linaro.org>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com
Subject: Re: [PATCH v4 6/8] ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs
Date: Sat, 20 Jul 2019 11:48:14 +0200	[thread overview]
Message-ID: <20190720094814.s6qik6ja2ympwpmp@flea> (raw)
In-Reply-To: <20190713034634.44585-7-icenowy@aosc.io>

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On Sat, Jul 13, 2019 at 11:46:32AM +0800, Icenowy Zheng wrote:
> The Allwinner S3/S3L/V3 SoCs all share the same die with the V3s SoC,
> but with more GPIO wired out of the package.
>
> Add DTSI files for these SoCs. The DTSI file for V3 just replaces the
> pinctrl compatible string, and the S3/S3L DTSI files just include the V3
> DTSI file.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> No changes since v2.
>
>  arch/arm/boot/dts/sun8i-s3.dtsi  |  6 ++++++
>  arch/arm/boot/dts/sun8i-s3l.dtsi |  6 ++++++
>  arch/arm/boot/dts/sun8i-v3.dtsi  | 14 ++++++++++++++
>  3 files changed, 26 insertions(+)
>  create mode 100644 arch/arm/boot/dts/sun8i-s3.dtsi
>  create mode 100644 arch/arm/boot/dts/sun8i-s3l.dtsi
>  create mode 100644 arch/arm/boot/dts/sun8i-v3.dtsi
>
> diff --git a/arch/arm/boot/dts/sun8i-s3.dtsi b/arch/arm/boot/dts/sun8i-s3.dtsi
> new file mode 100644
> index 000000000000..0f41a25ecb30
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-s3.dtsi
> @@ -0,0 +1,6 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
> + */
> +
> +#include "sun8i-v3.dtsi"
> diff --git a/arch/arm/boot/dts/sun8i-s3l.dtsi b/arch/arm/boot/dts/sun8i-s3l.dtsi
> new file mode 100644
> index 000000000000..0f41a25ecb30
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-s3l.dtsi
> @@ -0,0 +1,6 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
> + */
> +
> +#include "sun8i-v3.dtsi"
> diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/sun8i-v3.dtsi
> new file mode 100644
> index 000000000000..6ae8645ade50
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-v3.dtsi
> @@ -0,0 +1,14 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
> + */
> +
> +#include "sun8i-v3s.dtsi"
> +
> +&ccu {
> +	compatible = "allwinner,sun8i-v3-ccu";
> +};
> +
> +&pio {
> +	compatible = "allwinner,sun8i-v3-pinctrl";
> +};

Is there any difference between the S3, S3L and V3?

If not, then we don't need all those DTSI, just add the v3

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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  reply	other threads:[~2019-07-20  9:48 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-13  3:46 [PATCH v4 0/8] Support for Allwinner V3/S3L and Sochip S3 Icenowy Zheng
2019-07-13  3:46 ` [PATCH v4 1/8] pinctrl: sunxi: v3s: introduce support for V3 Icenowy Zheng
2019-07-20  9:20   ` Maxime Ripard
2019-07-13  3:46 ` [PATCH v4 2/8] clk: sunxi-ng: v3s: add the missing PLL_DDR1 Icenowy Zheng
2019-07-20  9:43   ` Maxime Ripard
2019-07-13  3:46 ` [PATCH v4 3/8] dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU Icenowy Zheng
2019-07-20  9:44   ` Maxime Ripard
2019-07-13  3:46 ` [PATCH v4 4/8] clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks Icenowy Zheng
2019-07-20  9:44   ` Maxime Ripard
2019-07-20  9:45     ` Icenowy Zheng
2019-07-13  3:46 ` [PATCH v4 5/8] clk: sunxi-ng: v3s: add Allwinner V3 support Icenowy Zheng
2019-07-20  9:46   ` Maxime Ripard
2019-07-22 17:07   ` Rob Herring
2019-07-13  3:46 ` [PATCH v4 6/8] ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs Icenowy Zheng
2019-07-20  9:48   ` Maxime Ripard [this message]
2019-07-20  9:50     ` Icenowy Zheng
2019-07-13  3:46 ` [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board Icenowy Zheng
2019-07-15 17:03   ` Rob Herring
2019-07-20 10:13   ` Maxime Ripard
2019-07-20 11:39     ` Icenowy Zheng
2019-07-22 19:29       ` Maxime Ripard
2019-07-24 13:09         ` Icenowy Zheng
2019-07-24 14:14           ` Maxime Ripard
2019-07-13  3:46 ` [PATCH v4 8/8] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 Icenowy Zheng
2019-07-20 10:12   ` Maxime Ripard

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