From: Maxime Ripard <maxime.ripard@bootlin.com>
To: Icenowy Zheng <icenowy@aosc.io>
Cc: Rob Herring <robh+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Linus Walleij <linus.walleij@linaro.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-sunxi@googlegroups.com
Subject: Re: [PATCH v4 8/8] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3
Date: Sat, 20 Jul 2019 12:12:39 +0200 [thread overview]
Message-ID: <20190720101239.dg2oe3jazzfmtzvw@flea> (raw)
In-Reply-To: <20190713034634.44585-9-icenowy@aosc.io>
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On Sat, Jul 13, 2019 at 11:46:34AM +0800, Icenowy Zheng wrote:
> Lichee zero plus is a core board made by Sipeed, which includes on-board
> TF slot or SMT SD NAND, and optional SPI NOR or eMMC, a UART debug
> header, a microUSB slot and a gold finger connector for expansion. It
> can use either Sochip S3 or Allwinner S3L SoC.
>
> Add the basic device tree for the core board, w/o optional onboard
> storage, and with S3 SoC.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> No changes in v4.
>
> Changes in v3:
> - Drop common regulator DTSI usage and added vcc3v3 regulator.
>
> arch/arm/boot/dts/Makefile | 1 +
> .../boot/dts/sun8i-s3-lichee-zero-plus.dts | 8 ++++
> .../dts/sun8i-s3-s3l-lichee-zero-plus.dtsi | 46 +++++++++++++++++++
> 3 files changed, 55 insertions(+)
> create mode 100644 arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts
> create mode 100644 arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 9159fa2cea90..e320460a952b 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1114,6 +1114,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
> sun8i-r16-nintendo-super-nes-classic.dtb \
> sun8i-r16-parrot.dtb \
> sun8i-r40-bananapi-m2-ultra.dtb \
> + sun8i-s3-lichee-zero-plus.dtb \
> sun8i-t3-cqa3t-bv3.dtb \
> sun8i-v3s-licheepi-zero.dtb \
> sun8i-v3s-licheepi-zero-dock.dtb \
> diff --git a/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts
> new file mode 100644
> index 000000000000..7d2f6b145190
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-s3-lichee-zero-plus.dts
> @@ -0,0 +1,8 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
> + */
> +
> +/dts-v1/;
> +#include "sun8i-s3.dtsi"
> +#include "sun8i-s3-s3l-lichee-zero-plus.dtsi"
Why do we need to mention both the S3 and S3l in the name? What are
the differences between the two, and why do you need to share a DTSI?
> diff --git a/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi
> new file mode 100644
> index 000000000000..2677d319fb29
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-s3-s3l-lichee-zero-plus.dtsi
> @@ -0,0 +1,46 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + reg_vcc3v3: vcc3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +};
> +
> +&mmc0 {
> + broken-cd;
> + bus-width = <4>;
> + vmmc-supply = <®_vcc3v3>;
> + status = "okay";
> +};
> +
> +&uart0 {
> + pinctrl-0 = <&uart0_pb_pins>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&usb_otg {
> + dr_mode = "otg";
> + status = "okay";
> +};
> +
> +&usbphy {
> + usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
> + status = "okay";
How can it do OTG if there's no controlable VBUS?
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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prev parent reply other threads:[~2019-07-20 10:12 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-13 3:46 [PATCH v4 0/8] Support for Allwinner V3/S3L and Sochip S3 Icenowy Zheng
2019-07-13 3:46 ` [PATCH v4 1/8] pinctrl: sunxi: v3s: introduce support for V3 Icenowy Zheng
2019-07-20 9:20 ` Maxime Ripard
2019-07-13 3:46 ` [PATCH v4 2/8] clk: sunxi-ng: v3s: add the missing PLL_DDR1 Icenowy Zheng
2019-07-20 9:43 ` Maxime Ripard
2019-07-13 3:46 ` [PATCH v4 3/8] dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU Icenowy Zheng
2019-07-20 9:44 ` Maxime Ripard
2019-07-13 3:46 ` [PATCH v4 4/8] clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks Icenowy Zheng
2019-07-20 9:44 ` Maxime Ripard
2019-07-20 9:45 ` Icenowy Zheng
2019-07-13 3:46 ` [PATCH v4 5/8] clk: sunxi-ng: v3s: add Allwinner V3 support Icenowy Zheng
2019-07-20 9:46 ` Maxime Ripard
2019-07-22 17:07 ` Rob Herring
2019-07-13 3:46 ` [PATCH v4 6/8] ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs Icenowy Zheng
2019-07-20 9:48 ` Maxime Ripard
2019-07-20 9:50 ` Icenowy Zheng
2019-07-13 3:46 ` [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board Icenowy Zheng
2019-07-15 17:03 ` Rob Herring
2019-07-20 10:13 ` Maxime Ripard
2019-07-20 11:39 ` Icenowy Zheng
2019-07-22 19:29 ` Maxime Ripard
2019-07-24 13:09 ` Icenowy Zheng
2019-07-24 14:14 ` Maxime Ripard
2019-07-13 3:46 ` [PATCH v4 8/8] ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3 Icenowy Zheng
2019-07-20 10:12 ` Maxime Ripard [this message]
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