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From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
	Jerome Brunet <jbrunet@baylibre.com>,
	Sasha Levin <sashal@kernel.org>,
	linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH AUTOSEL 5.5 049/542] clk: meson: meson8b: make the CCF use the glitch-free mali mux
Date: Fri, 14 Feb 2020 10:40:41 -0500
Message-ID: <20200214154854.6746-49-sashal@kernel.org> (raw)
In-Reply-To: <20200214154854.6746-1-sashal@kernel.org>

From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

[ Upstream commit 8daeaea99caabe24a0929fac17977ebfb882fa86 ]

The "mali_0" or "mali_1" clock trees should not be updated while the
clock is running. Enforce this by setting CLK_SET_RATE_GATE on the
"mali_0" and "mali_1" gates. This makes the CCF switch to the "mali_1"
tree when "mali_0" is currently active and vice versa, which is exactly
what the vendor driver does when updating the frequency of the mali
clock.

This fixes a potential hang when changing the GPU frequency at runtime.

Fixes: 74e1f2521f16ff ("clk: meson: meson8b: add the GPU clock tree")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/clk/meson/meson8b.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index 67e6691e080c1..8856ce476ccfa 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -1764,8 +1764,11 @@ static struct clk_regmap meson8b_hdmi_sys = {
 
 /*
  * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
- * muxed by a glitch-free switch on Meson8b and Meson8m2. Meson8 only
- * has mali_0 and no glitch-free mux.
+ * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
+ * actually manage this glitch-free mux because it does top-to-bottom
+ * updates the each clock tree and switches to the "inactive" one when
+ * CLK_SET_RATE_GATE is set.
+ * Meson8 only has mali_0 and no glitch-free mux.
  */
 static const struct clk_hw *meson8b_mali_0_1_parent_hws[] = {
 	&meson8b_xtal.hw,
@@ -1830,7 +1833,7 @@ static struct clk_regmap meson8b_mali_0 = {
 			&meson8b_mali_0_div.hw
 		},
 		.num_parents = 1,
-		.flags = CLK_SET_RATE_PARENT,
+		.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -1885,7 +1888,7 @@ static struct clk_regmap meson8b_mali_1 = {
 			&meson8b_mali_1_div.hw
 		},
 		.num_parents = 1,
-		.flags = CLK_SET_RATE_PARENT,
+		.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
 	},
 };
 
-- 
2.20.1


  parent reply index

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20200214154854.6746-1-sashal@kernel.org>
2020-02-14 15:40 ` [PATCH AUTOSEL 5.5 020/542] clk: meson: g12a: fix missing uart2 in regmap table Sasha Levin
2020-02-14 15:40 ` [PATCH AUTOSEL 5.5 021/542] clk: meson: pll: Fix by 0 division in __pll_params_to_rate() Sasha Levin
2020-02-14 15:40 ` [PATCH AUTOSEL 5.5 047/542] clk: at91: sam9x60: fix programmable clock prescaler Sasha Levin
2020-02-14 15:40 ` Sasha Levin [this message]
2020-02-14 15:41 ` [PATCH AUTOSEL 5.5 085/542] clk: ti: dra7: fix parent for gmac_clkctrl Sasha Levin
2020-02-14 15:42 ` [PATCH AUTOSEL 5.5 129/542] clk: qcom: Don't overwrite 'cfg' in clk_rcg2_dfs_populate_freq() Sasha Levin
2020-02-14 15:42 ` [PATCH AUTOSEL 5.5 130/542] clk: qcom: rcg2: Don't crash if our parent can't be found; return an error Sasha Levin
2020-02-14 15:43 ` [PATCH AUTOSEL 5.5 196/542] clk: imx: Add correct failure handling for clk based helpers Sasha Levin
2020-02-14 15:43 ` [PATCH AUTOSEL 5.5 236/542] clk: qcom: smd: Add missing bimc clock Sasha Levin
2020-02-14 15:43 ` [PATCH AUTOSEL 5.5 245/542] clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocks Sasha Levin
2020-02-14 15:44 ` [PATCH AUTOSEL 5.5 257/542] clk: qcom: Add missing msm8998 gcc_bimc_gfx_clk Sasha Levin
2020-02-14 15:44 ` [PATCH AUTOSEL 5.5 258/542] clk: actually call the clock init before any other callback of the clock Sasha Levin
2020-02-14 15:44 ` [PATCH AUTOSEL 5.5 260/542] clk: bm1800: Remove set but not used variable 'fref' Sasha Levin
2020-02-14 15:44 ` [PATCH AUTOSEL 5.5 279/542] clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock Sasha Levin
2020-02-14 15:44 ` [PATCH AUTOSEL 5.5 281/542] clk: Use parent node pointer during registration if necessary Sasha Levin
2020-02-14 15:44 ` [PATCH AUTOSEL 5.5 282/542] clk: uniphier: Add SCSSI clock gate for each channel Sasha Levin

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