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From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Grygorii Strashko <grygorii.strashko@ti.com>,
	Tero Kristo <t-kristo@ti.com>, Sasha Levin <sashal@kernel.org>,
	linux-omap@vger.kernel.org, linux-clk@vger.kernel.org
Subject: [PATCH AUTOSEL 5.5 085/542] clk: ti: dra7: fix parent for gmac_clkctrl
Date: Fri, 14 Feb 2020 10:41:17 -0500
Message-ID: <20200214154854.6746-85-sashal@kernel.org> (raw)
In-Reply-To: <20200214154854.6746-1-sashal@kernel.org>

From: Grygorii Strashko <grygorii.strashko@ti.com>

[ Upstream commit 69e300283796dae7e8c2e6acdabcd31336c0c93e ]

The parent clk for gmac clk ctrl has to be gmac_main_clk (125MHz) instead
of dpll_gmac_ck (1GHz). This is caused incorrect CPSW MDIO operation.
Hence, fix it.

Fixes: dffa9051d546 ('clk: ti: dra7: add new clkctrl data')
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/clk/ti/clk-7xx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index 5f46782cebeb2..b656ba2abcf7e 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -405,7 +405,7 @@ static const struct omap_clkctrl_bit_data dra7_gmac_bit_data[] __initconst = {
 };
 
 static const struct omap_clkctrl_reg_data dra7_gmac_clkctrl_regs[] __initconst = {
-	{ DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "dpll_gmac_ck" },
+	{ DRA7_GMAC_GMAC_CLKCTRL, dra7_gmac_bit_data, CLKF_SW_SUP, "gmac_main_clk" },
 	{ 0 },
 };
 
-- 
2.20.1


  parent reply index

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20200214154854.6746-1-sashal@kernel.org>
2020-02-14 15:40 ` [PATCH AUTOSEL 5.5 020/542] clk: meson: g12a: fix missing uart2 in regmap table Sasha Levin
2020-02-14 15:40 ` [PATCH AUTOSEL 5.5 021/542] clk: meson: pll: Fix by 0 division in __pll_params_to_rate() Sasha Levin
2020-02-14 15:40 ` [PATCH AUTOSEL 5.5 047/542] clk: at91: sam9x60: fix programmable clock prescaler Sasha Levin
2020-02-14 15:40 ` [PATCH AUTOSEL 5.5 049/542] clk: meson: meson8b: make the CCF use the glitch-free mali mux Sasha Levin
2020-02-14 15:41 ` Sasha Levin [this message]
2020-02-14 15:42 ` [PATCH AUTOSEL 5.5 129/542] clk: qcom: Don't overwrite 'cfg' in clk_rcg2_dfs_populate_freq() Sasha Levin
2020-02-14 15:42 ` [PATCH AUTOSEL 5.5 130/542] clk: qcom: rcg2: Don't crash if our parent can't be found; return an error Sasha Levin
2020-02-14 15:43 ` [PATCH AUTOSEL 5.5 196/542] clk: imx: Add correct failure handling for clk based helpers Sasha Levin
2020-02-14 15:43 ` [PATCH AUTOSEL 5.5 236/542] clk: qcom: smd: Add missing bimc clock Sasha Levin
2020-02-14 15:43 ` [PATCH AUTOSEL 5.5 245/542] clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocks Sasha Levin
2020-02-14 15:44 ` [PATCH AUTOSEL 5.5 257/542] clk: qcom: Add missing msm8998 gcc_bimc_gfx_clk Sasha Levin
2020-02-14 15:44 ` [PATCH AUTOSEL 5.5 258/542] clk: actually call the clock init before any other callback of the clock Sasha Levin
2020-02-14 15:44 ` [PATCH AUTOSEL 5.5 260/542] clk: bm1800: Remove set but not used variable 'fref' Sasha Levin
2020-02-14 15:44 ` [PATCH AUTOSEL 5.5 279/542] clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock Sasha Levin
2020-02-14 15:44 ` [PATCH AUTOSEL 5.5 281/542] clk: Use parent node pointer during registration if necessary Sasha Levin
2020-02-14 15:44 ` [PATCH AUTOSEL 5.5 282/542] clk: uniphier: Add SCSSI clock gate for each channel Sasha Levin

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