From: Maxime Ripard <maxime@cerno.tech>
To: Mike Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-clk@vger.kernel.org
Cc: Alexander Stein <alexander.stein@ew.tq-group.com>,
Yassine Oudjana <y.oudjana@protonmail.com>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Naresh Kamboju <naresh.kamboju@linaro.org>,
Tony Lindgren <tony@atomide.com>,
Neil Armstrong <narmstrong@baylibre.com>,
Marek Szyprowski <m.szyprowski@samsung.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Maxime Ripard <maxime@cerno.tech>
Subject: [PATCH v7 12/28] clk: tests: Add tests for single parent mux
Date: Fri, 15 Jul 2022 17:59:58 +0200 [thread overview]
Message-ID: <20220715160014.2623107-13-maxime@cerno.tech> (raw)
In-Reply-To: <20220715160014.2623107-1-maxime@cerno.tech>
We have a few tests for a mux with a single parent, testing the case
where it used to be orphan.
Let's leverage most of the code but register the clock properly to test
a few trivial things.
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> # imx8mp
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> # exynos4210, meson g12b
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
---
drivers/clk/clk_test.c | 194 +++++++++++++++++++++++++++++++++++++++--
1 file changed, 185 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c
index b269420dafcc..06c9220873bb 100644
--- a/drivers/clk/clk_test.c
+++ b/drivers/clk/clk_test.c
@@ -365,6 +365,189 @@ struct clk_single_parent_ctx {
struct clk_hw hw;
};
+static int clk_single_parent_mux_test_init(struct kunit *test)
+{
+ struct clk_single_parent_ctx *ctx;
+ int ret;
+
+ ctx = kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL);
+ if (!ctx)
+ return -ENOMEM;
+ test->priv = ctx;
+
+ ctx->parent_ctx.rate = DUMMY_CLOCK_INIT_RATE;
+ ctx->parent_ctx.hw.init =
+ CLK_HW_INIT_NO_PARENT("parent-clk",
+ &clk_dummy_rate_ops,
+ 0);
+
+ ret = clk_hw_register(NULL, &ctx->parent_ctx.hw);
+ if (ret)
+ return ret;
+
+ ctx->hw.init = CLK_HW_INIT("test-clk", "parent-clk",
+ &clk_dummy_single_parent_ops,
+ CLK_SET_RATE_PARENT);
+
+ ret = clk_hw_register(NULL, &ctx->hw);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void
+clk_single_parent_mux_test_exit(struct kunit *test)
+{
+ struct clk_single_parent_ctx *ctx = test->priv;
+
+ clk_hw_unregister(&ctx->hw);
+ clk_hw_unregister(&ctx->parent_ctx.hw);
+}
+
+/*
+ * Test that for a clock with a single parent, clk_get_parent() actually
+ * returns the parent.
+ */
+static void
+clk_test_single_parent_mux_get_parent(struct kunit *test)
+{
+ struct clk_single_parent_ctx *ctx = test->priv;
+ struct clk_hw *hw = &ctx->hw;
+ struct clk *clk = clk_hw_get_clk(hw, NULL);
+ struct clk *parent = clk_hw_get_clk(&ctx->parent_ctx.hw, NULL);
+
+ KUNIT_EXPECT_TRUE(test, clk_is_match(clk_get_parent(clk), parent));
+
+ clk_put(parent);
+ clk_put(clk);
+}
+
+/*
+ * Test that for a clock that can't modify its rate and with a single
+ * parent, if we set disjoints range on the parent and then the child,
+ * the second will return an error.
+ *
+ * FIXME: clk_set_rate_range() only considers the current clock when
+ * evaluating whether ranges are disjoints and not the upstream clocks
+ * ranges.
+ */
+static void
+clk_test_single_parent_mux_set_range_disjoint_child_last(struct kunit *test)
+{
+ struct clk_single_parent_ctx *ctx = test->priv;
+ struct clk_hw *hw = &ctx->hw;
+ struct clk *clk = clk_hw_get_clk(hw, NULL);
+ struct clk *parent;
+ int ret;
+
+ kunit_skip(test, "This needs to be fixed in the core.");
+
+ parent = clk_get_parent(clk);
+ KUNIT_ASSERT_PTR_NE(test, parent, NULL);
+
+ ret = clk_set_rate_range(parent, 1000, 2000);
+ KUNIT_ASSERT_EQ(test, ret, 0);
+
+ ret = clk_set_rate_range(clk, 3000, 4000);
+ KUNIT_EXPECT_LT(test, ret, 0);
+
+ clk_put(clk);
+}
+
+/*
+ * Test that for a clock that can't modify its rate and with a single
+ * parent, if we set disjoints range on the child and then the parent,
+ * the second will return an error.
+ *
+ * FIXME: clk_set_rate_range() only considers the current clock when
+ * evaluating whether ranges are disjoints and not the downstream clocks
+ * ranges.
+ */
+static void
+clk_test_single_parent_mux_set_range_disjoint_parent_last(struct kunit *test)
+{
+ struct clk_single_parent_ctx *ctx = test->priv;
+ struct clk_hw *hw = &ctx->hw;
+ struct clk *clk = clk_hw_get_clk(hw, NULL);
+ struct clk *parent;
+ int ret;
+
+ kunit_skip(test, "This needs to be fixed in the core.");
+
+ parent = clk_get_parent(clk);
+ KUNIT_ASSERT_PTR_NE(test, parent, NULL);
+
+ ret = clk_set_rate_range(clk, 1000, 2000);
+ KUNIT_ASSERT_EQ(test, ret, 0);
+
+ ret = clk_set_rate_range(parent, 3000, 4000);
+ KUNIT_EXPECT_LT(test, ret, 0);
+
+ clk_put(clk);
+}
+
+/*
+ * Test that for a clock that can't modify its rate and with a single
+ * parent, if we set a range on the parent and a more restrictive one on
+ * the child, and then call clk_round_rate(), the boundaries of the
+ * two clocks are taken into account.
+ */
+static void
+clk_test_single_parent_mux_set_range_round_rate_child_smaller(struct kunit *test)
+{
+ struct clk_single_parent_ctx *ctx = test->priv;
+ struct clk_hw *hw = &ctx->hw;
+ struct clk *clk = clk_hw_get_clk(hw, NULL);
+ struct clk *parent;
+ unsigned long rate;
+ int ret;
+
+ parent = clk_get_parent(clk);
+ KUNIT_ASSERT_PTR_NE(test, parent, NULL);
+
+ ret = clk_set_rate_range(parent, DUMMY_CLOCK_RATE_1, DUMMY_CLOCK_RATE_2);
+ KUNIT_ASSERT_EQ(test, ret, 0);
+
+ ret = clk_set_rate_range(clk, DUMMY_CLOCK_RATE_1 + 1000, DUMMY_CLOCK_RATE_2 - 1000);
+ KUNIT_ASSERT_EQ(test, ret, 0);
+
+ rate = clk_round_rate(clk, DUMMY_CLOCK_RATE_1 - 1000);
+ KUNIT_ASSERT_GT(test, rate, 0);
+ KUNIT_EXPECT_GE(test, rate, DUMMY_CLOCK_RATE_1 + 1000);
+ KUNIT_EXPECT_LE(test, rate, DUMMY_CLOCK_RATE_2 - 1000);
+
+ rate = clk_round_rate(clk, DUMMY_CLOCK_RATE_2 + 1000);
+ KUNIT_ASSERT_GT(test, rate, 0);
+ KUNIT_EXPECT_GE(test, rate, DUMMY_CLOCK_RATE_1 + 1000);
+ KUNIT_EXPECT_LE(test, rate, DUMMY_CLOCK_RATE_2 - 1000);
+
+ clk_put(clk);
+}
+
+static struct kunit_case clk_single_parent_mux_test_cases[] = {
+ KUNIT_CASE(clk_test_single_parent_mux_get_parent),
+ KUNIT_CASE(clk_test_single_parent_mux_set_range_disjoint_child_last),
+ KUNIT_CASE(clk_test_single_parent_mux_set_range_disjoint_parent_last),
+ KUNIT_CASE(clk_test_single_parent_mux_set_range_round_rate_child_smaller),
+ {}
+};
+
+/*
+ * Test suite for a basic mux clock with one parent, with
+ * CLK_SET_RATE_PARENT on the child.
+ *
+ * These tests exercise the consumer API and check that the state of the
+ * child and parent are sane and consistent.
+ */
+static struct kunit_suite
+clk_single_parent_mux_test_suite = {
+ .name = "clk-single-parent-mux-test",
+ .init = clk_single_parent_mux_test_init,
+ .exit = clk_single_parent_mux_test_exit,
+ .test_cases = clk_single_parent_mux_test_cases,
+};
+
static int clk_orphan_transparent_single_parent_mux_test_init(struct kunit *test)
{
struct clk_single_parent_ctx *ctx;
@@ -401,14 +584,6 @@ static int clk_orphan_transparent_single_parent_mux_test_init(struct kunit *test
return 0;
}
-static void clk_orphan_transparent_single_parent_mux_test_exit(struct kunit *test)
-{
- struct clk_single_parent_ctx *ctx = test->priv;
-
- clk_hw_unregister(&ctx->hw);
- clk_hw_unregister(&ctx->parent_ctx.hw);
-}
-
/*
* Test that a mux-only clock, with an initial rate within a range,
* will still have the same rate after the range has been enforced.
@@ -455,7 +630,7 @@ static struct kunit_case clk_orphan_transparent_single_parent_mux_test_cases[] =
static struct kunit_suite clk_orphan_transparent_single_parent_test_suite = {
.name = "clk-orphan-transparent-single-parent-test",
.init = clk_orphan_transparent_single_parent_mux_test_init,
- .exit = clk_orphan_transparent_single_parent_mux_test_exit,
+ .exit = clk_single_parent_mux_test_exit,
.test_cases = clk_orphan_transparent_single_parent_mux_test_cases,
};
@@ -1168,6 +1343,7 @@ kunit_test_suites(
&clk_range_test_suite,
&clk_range_maximize_test_suite,
&clk_range_minimize_test_suite,
+ &clk_single_parent_mux_test_suite,
&clk_uncached_test_suite
);
MODULE_LICENSE("GPL v2");
--
2.36.1
next prev parent reply other threads:[~2022-07-15 16:01 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-15 15:59 [PATCH v7 00/28] clk: More clock rate fixes and tests Maxime Ripard
2022-07-15 15:59 ` [PATCH v7 01/28] clk: bcm: rpi: Create helper to retrieve private data Maxime Ripard
2022-07-15 15:59 ` [PATCH v7 02/28] clk: bcm: rpi: Add a function to retrieve the maximum Maxime Ripard
2022-07-15 15:59 ` [PATCH v7 03/28] drm/vc4: hdmi: Rework hdmi_enable_4kp60 detection Maxime Ripard
2022-07-15 15:59 ` [PATCH v7 04/28] clk: test: Switch to clk_hw_get_clk Maxime Ripard
2022-07-15 15:59 ` [PATCH v7 05/28] clk: Drop the rate range on clk_put() Maxime Ripard
2022-07-15 15:59 ` [PATCH v7 06/28] clk: Skip clamping when rounding if there's no boundaries Maxime Ripard
2022-07-15 15:59 ` [PATCH v7 07/28] clk: Mention that .recalc_rate can return 0 on error Maxime Ripard
2022-07-15 15:59 ` [PATCH v7 08/28] clk: Clarify clk_get_rate() expectations Maxime Ripard
2022-07-15 15:59 ` [PATCH v7 09/28] clk: tests: Add test suites description Maxime Ripard
2022-07-15 15:59 ` [PATCH v7 10/28] clk: tests: Add reference to the orphan mux bug report Maxime Ripard
2022-07-15 15:59 ` [PATCH v7 11/28] clk: tests: Add tests for uncached clock Maxime Ripard
2022-07-15 15:59 ` Maxime Ripard [this message]
2022-07-15 15:59 ` [PATCH v7 13/28] clk: tests: Add tests for mux with multiple parents Maxime Ripard
2022-07-15 16:00 ` [PATCH v7 14/28] clk: tests: Add some tests for orphan " Maxime Ripard
2022-07-15 16:00 ` [PATCH v7 15/28] clk: Take into account uncached clocks in clk_set_rate_range() Maxime Ripard
2022-07-15 16:00 ` [PATCH v7 16/28] clk: Set req_rate on reparenting Maxime Ripard
2022-07-15 16:00 ` [PATCH v7 17/28] clk: Change clk_core_init_rate_req prototype Maxime Ripard
2022-07-15 16:00 ` [PATCH v7 18/28] clk: Move clk_core_init_rate_req() from clk_core_round_rate_nolock() to its caller Maxime Ripard
2022-07-15 16:00 ` [PATCH v7 19/28] clk: Introduce clk_hw_init_rate_request() Maxime Ripard
2022-07-15 16:00 ` [PATCH v7 20/28] clk: Add our request boundaries in clk_core_init_rate_req Maxime Ripard
2022-07-15 16:00 ` [PATCH v7 21/28] clk: Switch from __clk_determine_rate to clk_core_round_rate_nolock Maxime Ripard
2022-07-15 16:00 ` [PATCH v7 22/28] clk: Introduce clk_core_has_parent() Maxime Ripard
2022-07-15 16:00 ` [PATCH v7 23/28] clk: Constify clk_has_parent() Maxime Ripard
2022-07-15 16:00 ` [PATCH v7 24/28] clk: Stop forwarding clk_rate_requests to the parent Maxime Ripard
2022-07-15 16:00 ` [PATCH v7 25/28] clk: Zero the clk_rate_request structure Maxime Ripard
2022-07-15 16:00 ` [PATCH v7 26/28] clk: Introduce the clk_hw_get_rate_range function Maxime Ripard
2022-07-15 16:00 ` [PATCH v7 27/28] clk: qcom: clk-rcg2: Take clock boundaries into consideration for gfx3d Maxime Ripard
2022-07-15 16:00 ` [PATCH v7 28/28] clk: tests: Add missing test case for ranges Maxime Ripard
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