* [PATCH 3/5] clk: renesas: r8a774c0: Add TMU clock
[not found] <1549015841-33536-1-git-send-email-biju.das@bp.renesas.com>
@ 2019-02-01 10:10 ` Biju Das
2019-02-01 13:52 ` Geert Uytterhoeven
0 siblings, 1 reply; 3+ messages in thread
From: Biju Das @ 2019-02-01 10:10 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Simon Horman, Chris Paterson, Fabrizio Castro
This patch adds TMU clock to the R8A774C0 SoC.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
drivers/clk/renesas/r8a774c0-cpg-mssr.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index 10b9689..5953f5c 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -119,6 +119,11 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
};
static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
+ DEF_MOD("tmu4", 121, R8A774C0_CLK_S0D6),
+ DEF_MOD("tmu3", 122, R8A774C0_CLK_S3D2),
+ DEF_MOD("tmu2", 123, R8A774C0_CLK_S3D2),
+ DEF_MOD("tmu1", 124, R8A774C0_CLK_S3D2),
+ DEF_MOD("tmu0", 125, R8A774C0_CLK_CP),
DEF_MOD("scif5", 202, R8A774C0_CLK_S3D4C),
DEF_MOD("scif4", 203, R8A774C0_CLK_S3D4C),
DEF_MOD("scif3", 204, R8A774C0_CLK_S3D4C),
--
2.7.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 3/5] clk: renesas: r8a774c0: Add TMU clock
2019-02-01 10:10 ` [PATCH 3/5] clk: renesas: r8a774c0: Add TMU clock Biju Das
@ 2019-02-01 13:52 ` Geert Uytterhoeven
2019-02-01 14:02 ` Biju Das
0 siblings, 1 reply; 3+ messages in thread
From: Geert Uytterhoeven @ 2019-02-01 13:52 UTC (permalink / raw)
To: Biju Das
Cc: Michael Turquette, Stephen Boyd, Geert Uytterhoeven,
Linux-Renesas, linux-clk, Simon Horman, Chris Paterson,
Fabrizio Castro
Hi Biju,
On Fri, Feb 1, 2019 at 11:16 AM Biju Das <biju.das@bp.renesas.com> wrote:
> This patch adds TMU clock to the R8A774C0 SoC.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Thanks for your patch!
> --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> @@ -119,6 +119,11 @@ static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
> };
>
> static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
> + DEF_MOD("tmu4", 121, R8A774C0_CLK_S0D6),
RZ/G2 Hardware User's Manual rev. 0.61 says S0D6C?
> + DEF_MOD("tmu3", 122, R8A774C0_CLK_S3D2),
> + DEF_MOD("tmu2", 123, R8A774C0_CLK_S3D2),
> + DEF_MOD("tmu1", 124, R8A774C0_CLK_S3D2),
S3D2C? (all three)
Since these are timers, it should be easy to verify the actual parent
clock rates.
> + DEF_MOD("tmu0", 125, R8A774C0_CLK_CP),
> DEF_MOD("scif5", 202, R8A774C0_CLK_S3D4C),
> DEF_MOD("scif4", 203, R8A774C0_CLK_S3D4C),
> DEF_MOD("scif3", 204, R8A774C0_CLK_S3D4C),
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [PATCH 3/5] clk: renesas: r8a774c0: Add TMU clock
2019-02-01 13:52 ` Geert Uytterhoeven
@ 2019-02-01 14:02 ` Biju Das
0 siblings, 0 replies; 3+ messages in thread
From: Biju Das @ 2019-02-01 14:02 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Geert Uytterhoeven,
Linux-Renesas, linux-clk, Simon Horman, Chris Paterson,
Fabrizio Castro
Hi Geert,
Thanks for the feedback.
Regards,
Biju
> Subject: Re: [PATCH 3/5] clk: renesas: r8a774c0: Add TMU clock
>
> Hi Biju,
>
> On Fri, Feb 1, 2019 at 11:16 AM Biju Das <biju.das@bp.renesas.com> wrote:
> > This patch adds TMU clock to the R8A774C0 SoC.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> > +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
> > @@ -119,6 +119,11 @@ static const struct cpg_core_clk
> > r8a774c0_core_clks[] __initconst = { };
> >
> > static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
> > + DEF_MOD("tmu4", 121, R8A774C0_CLK_S0D6),
>
> RZ/G2 Hardware User's Manual rev. 0.61 says S0D6C?
>
Yes you are correct, I missed it.
> > + DEF_MOD("tmu3", 122, R8A774C0_CLK_S3D2),
> > + DEF_MOD("tmu2", 123, R8A774C0_CLK_S3D2),
> > + DEF_MOD("tmu1", 124, R8A774C0_CLK_S3D2),
>
> S3D2C? (all three)
Yes you are correct. Will send v2.
> Since these are timers, it should be easy to verify the actual parent clock
> rates.
Will check.
> > + DEF_MOD("tmu0", 125, R8A774C0_CLK_CP),
> > DEF_MOD("scif5", 202, R8A774C0_CLK_S3D4C),
> > DEF_MOD("scif4", 203, R8A774C0_CLK_S3D4C),
> > DEF_MOD("scif3", 204, R8A774C0_CLK_S3D4C),
Regards,
Biju
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2019-02-01 10:10 ` [PATCH 3/5] clk: renesas: r8a774c0: Add TMU clock Biju Das
2019-02-01 13:52 ` Geert Uytterhoeven
2019-02-01 14:02 ` Biju Das
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