[PATCH V2 0/3] imx8m: add mu support

[PATCH V2 0/3] imx8m: add mu support

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

V2:
 Add dt-bindings
 Merge dts changes into one patch, since all is to add mu node

Add mu dt bindings
Add mu node
Add i.MX8MP mu root clk

Peng Fan (3):
  dt-bindings: mailbox: imx-mu: support i.MX8M
  arm64: dts: imx8m: add mu node
  clk: imx8mp: add mu root clk

 Documentation/devicetree/bindings/mailbox/fsl,mu.txt | 3 ++-
 arch/arm64/boot/dts/freescale/imx8mm.dtsi            | 9 +++++++++
 arch/arm64/boot/dts/freescale/imx8mn.dtsi            | 9 +++++++++
 arch/arm64/boot/dts/freescale/imx8mp.dtsi            | 9 +++++++++
 arch/arm64/boot/dts/freescale/imx8mq.dtsi            | 9 +++++++++
 drivers/clk/imx/clk-imx8mp.c                         | 1 +
 6 files changed, 39 insertions(+), 1 deletion(-)

-- 
2.16.4

[PATCH V2 1/3] dt-bindings: mailbox: imx-mu: support i.MX8M

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

Add i.MX8MQ/M/N/P compatible string to support i.MX8M SoCs

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 Documentation/devicetree/bindings/mailbox/fsl,mu.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
index 26b7a88c2fea..906377acf2cd 100644
--- a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
+++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
@@ -18,7 +18,8 @@ Messaging Unit Device Node:
 Required properties:
 -------------------
 - compatible :	should be "fsl,<chip>-mu", the supported chips include
-		imx6sx, imx7s, imx8qxp, imx8qm.
+		imx6sx, imx7s, imx8qxp, imx8qm, imx8mq, imx8mm, imx8mn,
+		imx8mp.
 		The "fsl,imx6sx-mu" compatible is seen as generic and should
 		be included together with SoC specific compatible.
 		There is a version 1.0 MU on imx7ulp, use "fsl,imx7ulp-mu"
-- 
2.16.4

RE: [PATCH V2 1/3] dt-bindings: mailbox: imx-mu: support i.MX8M

[Aisheng Dong]

> From: Peng Fan <peng.fan@nxp.com>
> Sent: Monday, June 1, 2020 11:43 AM
> 
> Add i.MX8MQ/M/N/P compatible string to support i.MX8M SoCs
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>

BTW, Anson, 
will you continue to help convert MU binding into json schemas?

Regards
Aisheng

RE: [PATCH V2 1/3] dt-bindings: mailbox: imx-mu: support i.MX8M

[Anson Huang]

> Subject: RE: [PATCH V2 1/3] dt-bindings: mailbox: imx-mu: support i.MX8M
> 
> > From: Peng Fan <peng.fan@nxp.com>
> > Sent: Monday, June 1, 2020 11:43 AM
> >
> > Add i.MX8MQ/M/N/P compatible string to support i.MX8M SoCs
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> 
> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
> 
> BTW, Anson,
> will you continue to help convert MU binding into json schemas?

Ok.

[PATCH V2 2/3] arm64: dts: imx8m: add mu node

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

Add mu node to let A53 could communicate with M Core.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 9 +++++++++
 arch/arm64/boot/dts/freescale/imx8mn.dtsi | 9 +++++++++
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 9 +++++++++
 arch/arm64/boot/dts/freescale/imx8mq.dtsi | 9 +++++++++
 4 files changed, 36 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index aaf6e71101a1..fc001fb971e9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -775,6 +775,15 @@
 				status = "disabled";
 			};
 
+			mu: mailbox@30aa0000 {
+				compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
+				reg = <0x30aa0000 0x10000>;
+				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_MU_ROOT>;
+				clock-names = "mu";
+				#mbox-cells = <2>;
+			};
+
 			usdhc1: mmc@30b40000 {
 				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
 				reg = <0x30b40000 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 9a4b65a267d4..c8290d21ccc9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -675,6 +675,15 @@
 				status = "disabled";
 			};
 
+			mu: mailbox@30aa0000 {
+				compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
+				reg = <0x30aa0000 0x10000>;
+				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MN_CLK_MU_ROOT>;
+				clock-names = "mu";
+				#mbox-cells = <2>;
+			};
+
 			usdhc1: mmc@30b40000 {
 				compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
 				reg = <0x30b40000 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 45e2c0a4e889..b530804f763e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -621,6 +621,15 @@
 				status = "disabled";
 			};
 
+			mu: mailbox@30aa0000 {
+				compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
+				reg = <0x30aa0000 0x10000>;
+				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MP_CLK_MU_ROOT>;
+				clock-names = "mu";
+				#mbox-cells = <2>;
+			};
+
 			i2c5: i2c@30ad0000 {
 				compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
 				#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 978f8122c0d2..66ba8da704f6 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -959,6 +959,15 @@
 				status = "disabled";
 			};
 
+			mu: mailbox@30aa0000 {
+				compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
+				reg = <0x30aa0000 0x10000>;
+				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_MU_ROOT>;
+				clock-names = "mu";
+				#mbox-cells = <2>;
+			};
+
 			usdhc1: mmc@30b40000 {
 				compatible = "fsl,imx8mq-usdhc",
 				             "fsl,imx7d-usdhc";
-- 
2.16.4

RE: [PATCH V2 2/3] arm64: dts: imx8m: add mu node

[Aisheng Dong]

> From: Peng Fan <peng.fan@nxp.com>
> Sent: Monday, June 1, 2020 11:43 AM
> 
> Add mu node to let A53 could communicate with M Core.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi | 9 +++++++++
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 9 +++++++++
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 9 +++++++++
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 9 +++++++++
>  4 files changed, 36 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index aaf6e71101a1..fc001fb971e9 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -775,6 +775,15 @@
>  				status = "disabled";
>  			};
> 
> +			mu: mailbox@30aa0000 {
> +				compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
> +				reg = <0x30aa0000 0x10000>;
> +				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MM_CLK_MU_ROOT>;
> +				clock-names = "mu";

You missed my comments about this unneeded line in the last round of review.
https://lore.kernel.org/patchwork/patch/1244752/

Regards
Aisheng

> +				#mbox-cells = <2>;
> +			};
> +
>  			usdhc1: mmc@30b40000 {
>  				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
>  				reg = <0x30b40000 0x10000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index 9a4b65a267d4..c8290d21ccc9 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -675,6 +675,15 @@
>  				status = "disabled";
>  			};
> 
> +			mu: mailbox@30aa0000 {
> +				compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
> +				reg = <0x30aa0000 0x10000>;
> +				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MN_CLK_MU_ROOT>;
> +				clock-names = "mu";
> +				#mbox-cells = <2>;
> +			};
> +
>  			usdhc1: mmc@30b40000 {
>  				compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
>  				reg = <0x30b40000 0x10000>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index 45e2c0a4e889..b530804f763e 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -621,6 +621,15 @@
>  				status = "disabled";
>  			};
> 
> +			mu: mailbox@30aa0000 {
> +				compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
> +				reg = <0x30aa0000 0x10000>;
> +				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MP_CLK_MU_ROOT>;
> +				clock-names = "mu";
> +				#mbox-cells = <2>;
> +			};
> +
>  			i2c5: i2c@30ad0000 {
>  				compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
>  				#address-cells = <1>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 978f8122c0d2..66ba8da704f6 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -959,6 +959,15 @@
>  				status = "disabled";
>  			};
> 
> +			mu: mailbox@30aa0000 {
> +				compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
> +				reg = <0x30aa0000 0x10000>;
> +				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MQ_CLK_MU_ROOT>;
> +				clock-names = "mu";
> +				#mbox-cells = <2>;
> +			};
> +
>  			usdhc1: mmc@30b40000 {
>  				compatible = "fsl,imx8mq-usdhc",
>  				             "fsl,imx7d-usdhc";
> --
> 2.16.4

RE: [PATCH V2 2/3] arm64: dts: imx8m: add mu node

[Peng Fan]

> Subject: RE: [PATCH V2 2/3] arm64: dts: imx8m: add mu node
> 
> > From: Peng Fan <peng.fan@nxp.com>
> > Sent: Monday, June 1, 2020 11:43 AM
> >
> > Add mu node to let A53 could communicate with M Core.
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/imx8mm.dtsi | 9 +++++++++
> > arch/arm64/boot/dts/freescale/imx8mn.dtsi | 9 +++++++++
> > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 9 +++++++++
> > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 9 +++++++++
> >  4 files changed, 36 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > index aaf6e71101a1..fc001fb971e9 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > @@ -775,6 +775,15 @@
> >  				status = "disabled";
> >  			};
> >
> > +			mu: mailbox@30aa0000 {
> > +				compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
> > +				reg = <0x30aa0000 0x10000>;
> > +				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&clk IMX8MM_CLK_MU_ROOT>;
> > +				clock-names = "mu";
> 
> You missed my comments about this unneeded line in the last round of
> review.
> https://lore.kernel.org/patchwork/patch/1244752/

oops, will update in v3.

Thanks,
Peng.

> 
> Regards
> Aisheng
> 
> > +				#mbox-cells = <2>;
> > +			};
> > +
> >  			usdhc1: mmc@30b40000 {
> >  				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
> >  				reg = <0x30b40000 0x10000>;
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> > index 9a4b65a267d4..c8290d21ccc9 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> > @@ -675,6 +675,15 @@
> >  				status = "disabled";
> >  			};
> >
> > +			mu: mailbox@30aa0000 {
> > +				compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
> > +				reg = <0x30aa0000 0x10000>;
> > +				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&clk IMX8MN_CLK_MU_ROOT>;
> > +				clock-names = "mu";
> > +				#mbox-cells = <2>;
> > +			};
> > +
> >  			usdhc1: mmc@30b40000 {
> >  				compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
> >  				reg = <0x30b40000 0x10000>;
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > index 45e2c0a4e889..b530804f763e 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > @@ -621,6 +621,15 @@
> >  				status = "disabled";
> >  			};
> >
> > +			mu: mailbox@30aa0000 {
> > +				compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
> > +				reg = <0x30aa0000 0x10000>;
> > +				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&clk IMX8MP_CLK_MU_ROOT>;
> > +				clock-names = "mu";
> > +				#mbox-cells = <2>;
> > +			};
> > +
> >  			i2c5: i2c@30ad0000 {
> >  				compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
> >  				#address-cells = <1>;
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > index 978f8122c0d2..66ba8da704f6 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > @@ -959,6 +959,15 @@
> >  				status = "disabled";
> >  			};
> >
> > +			mu: mailbox@30aa0000 {
> > +				compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
> > +				reg = <0x30aa0000 0x10000>;
> > +				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> > +				clocks = <&clk IMX8MQ_CLK_MU_ROOT>;
> > +				clock-names = "mu";
> > +				#mbox-cells = <2>;
> > +			};
> > +
> >  			usdhc1: mmc@30b40000 {
> >  				compatible = "fsl,imx8mq-usdhc",
> >  				             "fsl,imx7d-usdhc";
> > --
> > 2.16.4

[PATCH V2 3/3] clk: imx8mp: add mu root clk

[peng.fan]

From: Peng Fan <peng.fan@nxp.com>

Add mu root clk for mu mailbox usage.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
---
 drivers/clk/imx/clk-imx8mp.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index b4d9db9d5bf1..ca747712400f 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -680,6 +680,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 	hws[IMX8MP_CLK_I2C2_ROOT] = imx_clk_hw_gate4("i2c2_root_clk", "i2c2", ccm_base + 0x4180, 0);
 	hws[IMX8MP_CLK_I2C3_ROOT] = imx_clk_hw_gate4("i2c3_root_clk", "i2c3", ccm_base + 0x4190, 0);
 	hws[IMX8MP_CLK_I2C4_ROOT] = imx_clk_hw_gate4("i2c4_root_clk", "i2c4", ccm_base + 0x41a0, 0);
+	hws[IMX8MP_CLK_MU_ROOT] = imx_clk_hw_gate4("mu_root_clk", "ipg_root", ccm_base + 0x4210, 0);
 	hws[IMX8MP_CLK_OCOTP_ROOT] = imx_clk_hw_gate4("ocotp_root_clk", "ipg_root", ccm_base + 0x4220, 0);
 	hws[IMX8MP_CLK_PCIE_ROOT] = imx_clk_hw_gate4("pcie_root_clk", "pcie_aux", ccm_base + 0x4250, 0);
 	hws[IMX8MP_CLK_PWM1_ROOT] = imx_clk_hw_gate4("pwm1_root_clk", "pwm1", ccm_base + 0x4280, 0);
-- 
2.16.4